From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
Karol Kolacinski <karol.kolacinski@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Milena Olech <milena.olech@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number calculation
Date: Tue, 25 Feb 2025 09:50:21 +0000 [thread overview]
Message-ID: <20250225095021.GK1615191@kernel.org> (raw)
In-Reply-To: <20250221093949.2436728-1-grzegorz.nitka@intel.com>
On Fri, Feb 21, 2025 at 10:39:49AM +0100, Grzegorz Nitka wrote:
> E82X adapters do not have sequential IDs, lane number is PF ID.
>
> Add check for ICE_MAC_GENERIC and skip checking port options.
This I see.
>
> Also, adjust logical port number for specific E825 device with external
> PHY support (PCI device id 0x579F). For this particular device,
> with 2x25G (PHY0) and 2x10G (PHY1) port configuration, modification of
> pf_id -> lane_number mapping is required. PF IDs on the 2nd PHY start
> from 4 in such scenario. Otherwise, the lane number cannot be
> determined correctly, leading to PTP init errors during PF initialization.
>
> Fixes: 258f5f9058159 ("ice: Add correct PHY lane assignment")
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2025-02-25 9:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 9:39 [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number calculation Grzegorz Nitka
2025-02-25 9:50 ` Simon Horman [this message]
2025-02-27 17:27 ` Simon Horman
2025-10-03 7:45 ` Rinitha, SX
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