From: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
To: Tony Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
Faizal Rahim <faizal.abdul.rahim@linux.intel.com>,
Chwee-Lin Choong <chwee.lin.choong@intel.com>
Subject: [Intel-wired-lan] [PATCH iwl-next v1 1/8] igc: move IGC_TXDCTL_QUEUE_ENABLE and IGC_TXDCTL_SWFLUSH
Date: Mon, 28 Apr 2025 02:02:18 -0400 [thread overview]
Message-ID: <20250428060225.1306986-2-faizal.abdul.rahim@linux.intel.com> (raw)
In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com>
Consolidate TXDCTL-related macros for better organization and readability.
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
---
drivers/net/ethernet/intel/igc/igc.h | 6 ++++++
drivers/net/ethernet/intel/igc/igc_base.h | 4 ----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index 859a15e4ccba..e9d180eac015 100644
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -492,6 +492,12 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
#define IGC_RX_WTHRESH 4
#define IGC_TX_WTHRESH 16
+/* Additional Transmit Descriptor Control definitions */
+/* Ena specific Tx Queue */
+#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000
+/* Transmit Software Flush */
+#define IGC_TXDCTL_SWFLUSH 0x04000000
+
#define IGC_RX_DMA_ATTR \
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h
index 6320eabb72fe..4a56c634977b 100644
--- a/drivers/net/ethernet/intel/igc/igc_base.h
+++ b/drivers/net/ethernet/intel/igc/igc_base.h
@@ -86,10 +86,6 @@ union igc_adv_rx_desc {
} wb; /* writeback */
};
-/* Additional Transmit Descriptor Control definitions */
-#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
-#define IGC_TXDCTL_SWFLUSH 0x04000000 /* Transmit Software Flush */
-
/* Additional Receive Descriptor Control definitions */
#define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
#define IGC_RXDCTL_SWFLUSH 0x04000000 /* Receive Software Flush */
--
2.34.1
next prev parent reply other threads:[~2025-04-28 6:03 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 6:02 [Intel-wired-lan] [PATCH iwl-next v1 0/8] igc: harmonize queue priority and add preemptible queue support Faizal Rahim
2025-04-28 6:02 ` Faizal Rahim [this message]
2025-04-28 7:01 ` [Intel-wired-lan] [PATCH iwl-next v1 1/8] igc: move IGC_TXDCTL_QUEUE_ENABLE and IGC_TXDCTL_SWFLUSH Ruinskiy, Dima
2025-04-29 3:36 ` Abdul Rahim, Faizal
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 2/8] igc: add TXDCTL prefix to related macros Faizal Rahim
2025-04-28 6:57 ` Ruinskiy, Dima
2025-04-29 3:37 ` Abdul Rahim, Faizal
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 3/8] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK Faizal Rahim
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 4/8] igc: assign highest TX queue number as highest priority in mqprio Faizal Rahim
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 5/8] igc: add private flag to reverse TX queue priority in TSN mode Faizal Rahim
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio Faizal Rahim
2025-04-28 9:11 ` Loktionov, Aleksandr
2025-04-29 3:39 ` Abdul Rahim, Faizal
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 7/8] igc: add preemptible queue support in mqprio Faizal Rahim
2025-04-28 6:02 ` [Intel-wired-lan] [PATCH iwl-next v1 8/8] igc: SW pad preemptible frames for correct mCRC calculation Faizal Rahim
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