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01 May 2025 15:54:37 -0700 X-CSE-ConnectionGUID: E6KxEKfrT9a2u0mwEVQDkg== X-CSE-MsgGUID: FK0I/ph5TjiDoMB2+j7j6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,254,1739865600"; d="scan'208";a="138514312" Received: from jekeller-desk.jf.intel.com ([10.166.241.15]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2025 15:54:36 -0700 From: Jacob Keller Date: Thu, 01 May 2025 15:54:23 -0700 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250501-kk-tspll-improvements-alignment-v4-12-24c83d0ce7a8@intel.com> References: <20250501-kk-tspll-improvements-alignment-v4-0-24c83d0ce7a8@intel.com> In-Reply-To: <20250501-kk-tspll-improvements-alignment-v4-0-24c83d0ce7a8@intel.com> To: Intel Wired LAN , Anthony Nguyen , netdev Cc: Jacob Keller , Michal Kubiak , Aleksandr Loktionov , Karol Kolacinski , Przemek Kitszel , Milena Olech , Paul Menzel X-Mailer: b4 0.14.2 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746140078; x=1777676078; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=+Buf/9WEdy+t/yBkq3aZ0+eWMnVbx5nWuReq8OY0u2M=; b=hEA2dmSeF0lGt+TJJDjdCsUeqGaIj4xuCwMjoKqK6M7d7aR2PC66BgXh Pmas6Op/mRe/pn2b+DDW7uWtmbTENYT66Y4D3A5ZkeWj5uM5qfOqHg3x6 /eTDb1pHmsGEeebHuJL5aEHEo8rsvKLHi5igjqZPgi4zGri6Q39wQRgj6 Njj/w6W66CJKM4v/l6LPuukP8vqgD+c/8uTqUl3jmAqT8ooNbQeHknlKs 0DZC/0nsU8EFeJmPtATIXCrf/zLXGBFswzwMvSY7LHPm2s8xJTr/Zto8N iEfc8nwG1SEpyXTus9tdl7v5N1QwXQTPjrQ95uELnKM+2XCOP8eK11w2j w==; X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=hEA2dmSe Subject: [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" From: Karol Kolacinski To ensure proper operation, wait for 10 to 20 microseconds before enabling TSPLL. Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms. Those values are empirical and tested on multiple HW configurations. Reviewed-by: Milena Olech Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c index 66ad5ee63f3084d1d54c2445f56d7f61d6be344b..a392b39920aeb7c23008a03baf3df9cd14dcbb7e 100644 --- a/drivers/net/ethernet/intel/ice/ice_tspll.c +++ b/drivers/net/ethernet/intel/ice/ice_tspll.c @@ -229,12 +229,15 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq, r24 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src); ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24); + /* Wait to ensure everything is stable */ + usleep_range(10, 20); + /* Finally, enable the PLL */ r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE; ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24); - /* Wait to verify if the PLL locks */ - usleep_range(1000, 5000); + /* Wait at least 1 ms to verify if the PLL locks */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val); if (!(val & ICE_CGU_RO_BWM_LF_TRUE_LOCK)) { @@ -357,12 +360,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq, /* Clear the R24 register. */ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0); + /* Wait to ensure everything is stable */ + usleep_range(10, 20); + /* Finally, enable the PLL */ r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE; ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23); - /* Wait to verify if the PLL locks */ - usleep_range(1000, 5000); + /* Wait at least 1 ms to verify if the PLL locks */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val); if (!(val & ICE_CGU_RO_LOCK_TRUE_LOCK)) { -- 2.48.1.397.gec9d649cc640