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From: Jacob Keller <jacob.e.keller@intel.com>
To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>,
	 Anthony Nguyen <anthony.l.nguyen@intel.com>,
	 netdev <netdev@vger.kernel.org>
Cc: Jacob Keller <jacob.e.keller@intel.com>,
	 Michal Kubiak <michal.kubiak@intel.com>,
	 Aleksandr Loktionov <aleksandr.loktionov@intel.com>,
	 Karol Kolacinski <karol.kolacinski@intel.com>,
	 Przemek Kitszel <przemyslaw.kitszel@intel.com>,
	 Milena Olech <milena.olech@intel.com>,
	Paul Menzel <pmenzel@molgen.mpg.de>
Subject: [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C
Date: Thu, 01 May 2025 15:54:26 -0700	[thread overview]
Message-ID: <20250501-kk-tspll-improvements-alignment-v4-15-24c83d0ce7a8@intel.com> (raw)
In-Reply-To: <20250501-kk-tspll-improvements-alignment-v4-0-24c83d0ce7a8@intel.com>

The driver currently defaults to the internal oscillator as the clock
source for E825-C hardware. While this clock source is labeled TCXO,
indicating a temperature compensated oscillator, this is only true for some
board designs. Many board designs have a less capable oscillator. The
E825-C hardware may also have its clock source set to the TIME_REF pin.
This pin is connected to the DPLL and is often a more stable clock source.
The choice of the internal oscillator is not suitable for all systems,
especially those which want to enable SyncE support.

There is currently no interface available for users to configure the clock
source. Other variants of the E82x board have the clock source configured
in the NVM, but E825-C lacks this capability, so different board designs
cannot select a different default clock via firmware.

In most setups, the TIME_REF is a suitable default clock source.
Additionally, we now fall back to the internal oscillator automatically if
the TIME_REF clock source cannot be locked.

Change the default clock source for E825-C to TIME_REF. Note that the
driver logs a dev_dbg message upon configuring the TSPLL which includes the
clock source and frequency. This can be enabled to confirm which clock
source is in use.

Longterm a proper interface to dynamically introspect and change the clock
source will be designed (perhaps some extension of the DPLL subsystem?)

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 7d731d1be862311358943c6922354504ba4721ba..742ffbfba73ca3279cec311ae359ebc6a4e6a584 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2344,7 +2344,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
 		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
 	} else {
 		info->clk_freq = ICE_TSPLL_FREQ_156_250;
-		info->clk_src = ICE_CLK_SRC_TCXO;
+		info->clk_src = ICE_CLK_SRC_TIME_REF;
 	}
 
 	if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {

-- 
2.48.1.397.gec9d649cc640


  parent reply	other threads:[~2025-05-01 22:54 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file Jacob Keller
2025-05-22 14:13   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions Jacob Keller
2025-05-22 14:15   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions Jacob Keller
2025-05-22 14:18   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions Jacob Keller
2025-05-22 14:19   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts Jacob Keller
2025-05-22 14:21   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper Jacob Keller
2025-05-22 14:23   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers Jacob Keller
2025-05-22 14:24   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming Jacob Keller
2025-05-22 14:27   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status Jacob Keller
2025-05-22 14:28   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs Jacob Keller
2025-05-22 14:30   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers Jacob Keller
2025-05-22 14:32   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL Jacob Keller
2025-05-22 14:34   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail Jacob Keller
2025-05-22 14:36   ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c Jacob Keller
2025-05-22 14:38   ` Rinitha, SX
2025-05-01 22:54 ` Jacob Keller [this message]
2025-05-22 14:40   ` [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C Rinitha, SX

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