* [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:13 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions Jacob Keller
` (13 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Collect TSPLL related functions and definitions and move them to
a separate file to have all TSPLL functionality in one place.
Move CGU related functions and definitions to ice_common.*
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice.h | 1 +
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 181 -------
drivers/net/ethernet/intel/ice/ice_common.h | 176 +++++++
drivers/net/ethernet/intel/ice/ice_ptp_consts.h | 161 ------
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 43 --
drivers/net/ethernet/intel/ice/ice_tspll.h | 46 ++
drivers/net/ethernet/intel/ice/ice_common.c | 61 +++
drivers/net/ethernet/intel/ice/ice_ptp.c | 1 -
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 542 --------------------
drivers/net/ethernet/intel/ice/ice_tspll.c | 646 ++++++++++++++++++++++++
drivers/net/ethernet/intel/ice/Makefile | 2 +-
11 files changed, 931 insertions(+), 929 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h
index 0693707ceabf2cf185f31eb079ff329a0469d4ee..fe5db9c5fb5515fcd2b96444da28140ca5671374 100644
--- a/drivers/net/ethernet/intel/ice/ice.h
+++ b/drivers/net/ethernet/intel/ice/ice.h
@@ -67,6 +67,7 @@
#include "ice_sriov.h"
#include "ice_vf_mbx.h"
#include "ice_ptp.h"
+#include "ice_tspll.h"
#include "ice_fdir.h"
#include "ice_xsk.h"
#include "ice_arfs.h"
diff --git a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
deleted file mode 100644
index 10d9d74f354555555a61d6f75238bf6703777881..0000000000000000000000000000000000000000
--- a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2018-2021, Intel Corporation. */
-
-#ifndef _ICE_CGU_REGS_H_
-#define _ICE_CGU_REGS_H_
-
-#define NAC_CGU_DWORD9 0x24
-union nac_cgu_dword9 {
- struct {
- u32 time_ref_freq_sel : 3;
- u32 clk_eref1_en : 1;
- u32 clk_eref0_en : 1;
- u32 time_ref_en : 1;
- u32 time_sync_en : 1;
- u32 one_pps_out_en : 1;
- u32 clk_ref_synce_en : 1;
- u32 clk_synce1_en : 1;
- u32 clk_synce0_en : 1;
- u32 net_clk_ref1_en : 1;
- u32 net_clk_ref0_en : 1;
- u32 clk_synce1_amp : 2;
- u32 misc6 : 1;
- u32 clk_synce0_amp : 2;
- u32 one_pps_out_amp : 2;
- u32 misc24 : 12;
- };
- u32 val;
-};
-
-#define NAC_CGU_DWORD16_E825C 0x40
-union nac_cgu_dword16_e825c {
- struct {
- u32 synce_remndr : 6;
- u32 synce_phlmt_en : 1;
- u32 misc13 : 17;
- u32 tspll_ck_refclkfreq : 8;
- };
- u32 val;
-};
-
-#define NAC_CGU_DWORD19 0x4c
-union nac_cgu_dword19 {
- struct {
- u32 tspll_fbdiv_intgr : 8;
- u32 fdpll_ulck_thr : 5;
- u32 misc15 : 3;
- u32 tspll_ndivratio : 4;
- u32 tspll_iref_ndivratio : 3;
- u32 misc19 : 1;
- u32 japll_ndivratio : 4;
- u32 japll_iref_ndivratio : 3;
- u32 misc27 : 1;
- };
- u32 val;
-};
-
-#define NAC_CGU_DWORD22 0x58
-union nac_cgu_dword22 {
- struct {
- u32 fdpll_frac_div_out_nc : 2;
- u32 fdpll_lock_int_for : 1;
- u32 synce_hdov_int_for : 1;
- u32 synce_lock_int_for : 1;
- u32 fdpll_phlead_slip_nc : 1;
- u32 fdpll_acc1_ovfl_nc : 1;
- u32 fdpll_acc2_ovfl_nc : 1;
- u32 synce_status_nc : 6;
- u32 fdpll_acc1f_ovfl : 1;
- u32 misc18 : 1;
- u32 fdpllclk_div : 4;
- u32 time1588clk_div : 4;
- u32 synceclk_div : 4;
- u32 synceclk_sel_div2 : 1;
- u32 fdpllclk_sel_div2 : 1;
- u32 time1588clk_sel_div2 : 1;
- u32 misc3 : 1;
- };
- u32 val;
-};
-
-#define NAC_CGU_DWORD23_E825C 0x5C
-union nac_cgu_dword23_e825c {
- struct {
- u32 cgupll_fbdiv_intgr : 10;
- u32 ux56pll_fbdiv_intgr : 10;
- u32 misc20 : 4;
- u32 ts_pll_enable : 1;
- u32 time_sync_tspll_align_sel : 1;
- u32 ext_synce_sel : 1;
- u32 ref1588_ck_div : 4;
- u32 time_ref_sel : 1;
-
- };
- u32 val;
-};
-
-#define NAC_CGU_DWORD24 0x60
-union nac_cgu_dword24 {
- struct {
- u32 tspll_fbdiv_frac : 22;
- u32 misc20 : 2;
- u32 ts_pll_enable : 1;
- u32 time_sync_tspll_align_sel : 1;
- u32 ext_synce_sel : 1;
- u32 ref1588_ck_div : 4;
- u32 time_ref_sel : 1;
- };
- u32 val;
-};
-
-#define TSPLL_CNTR_BIST_SETTINGS 0x344
-union tspll_cntr_bist_settings {
- struct {
- u32 i_irefgen_settling_time_cntr_7_0 : 8;
- u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
- u32 reserved195 : 5;
- u32 i_plllock_sel_0 : 1;
- u32 i_plllock_sel_1 : 1;
- u32 i_plllock_cnt_6_0 : 7;
- u32 i_plllock_cnt_10_7 : 4;
- u32 reserved200 : 4;
- };
- u32 val;
-};
-
-#define TSPLL_RO_BWM_LF 0x370
-union tspll_ro_bwm_lf {
- struct {
- u32 bw_freqov_high_cri_7_0 : 8;
- u32 bw_freqov_high_cri_9_8 : 2;
- u32 biascaldone_cri : 1;
- u32 plllock_gain_tran_cri : 1;
- u32 plllock_true_lock_cri : 1;
- u32 pllunlock_flag_cri : 1;
- u32 afcerr_cri : 1;
- u32 afcdone_cri : 1;
- u32 feedfwrdgain_cal_cri_7_0 : 8;
- u32 m2fbdivmod_cri_7_0 : 8;
- };
- u32 val;
-};
-
-#define TSPLL_RO_LOCK_E825C 0x3f0
-union tspll_ro_lock_e825c {
- struct {
- u32 bw_freqov_high_cri_7_0 : 8;
- u32 bw_freqov_high_cri_9_8 : 2;
- u32 reserved455 : 1;
- u32 plllock_gain_tran_cri : 1;
- u32 plllock_true_lock_cri : 1;
- u32 pllunlock_flag_cri : 1;
- u32 afcerr_cri : 1;
- u32 afcdone_cri : 1;
- u32 feedfwrdgain_cal_cri_7_0 : 8;
- u32 reserved462 : 8;
- };
- u32 val;
-};
-
-#define TSPLL_BW_TDC_E825C 0x31c
-union tspll_bw_tdc_e825c {
- struct {
- u32 i_tdc_offset_lock_1_0 : 2;
- u32 i_bbthresh1_2_0 : 3;
- u32 i_bbthresh2_2_0 : 3;
- u32 i_tdcsel_1_0 : 2;
- u32 i_tdcovccorr_en_h : 1;
- u32 i_divretimeren : 1;
- u32 i_bw_ampmeas_window : 1;
- u32 i_bw_lowerbound_2_0 : 3;
- u32 i_bw_upperbound_2_0 : 3;
- u32 i_bw_mode_1_0 : 2;
- u32 i_ft_mode_sel_2_0 : 3;
- u32 i_bwphase_4_0 : 5;
- u32 i_plllock_sel_1_0 : 2;
- u32 i_afc_divratio : 1;
- };
- u32 val;
-};
-
-#endif /* _ICE_CGU_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index 6b9264f9262b1b043ea7b3d4955531238c1178ff..1a28dd41d8db46057d684c96b90d3a37fdbc7165 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -39,6 +39,180 @@
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
+#define NAC_CGU_DWORD9 0x24
+union nac_cgu_dword9 {
+ struct {
+ u32 time_ref_freq_sel : 3;
+ u32 clk_eref1_en : 1;
+ u32 clk_eref0_en : 1;
+ u32 time_ref_en : 1;
+ u32 time_sync_en : 1;
+ u32 one_pps_out_en : 1;
+ u32 clk_ref_synce_en : 1;
+ u32 clk_synce1_en : 1;
+ u32 clk_synce0_en : 1;
+ u32 net_clk_ref1_en : 1;
+ u32 net_clk_ref0_en : 1;
+ u32 clk_synce1_amp : 2;
+ u32 misc6 : 1;
+ u32 clk_synce0_amp : 2;
+ u32 one_pps_out_amp : 2;
+ u32 misc24 : 12;
+ };
+ u32 val;
+};
+
+#define NAC_CGU_DWORD16_E825C 0x40
+union nac_cgu_dword16_e825c {
+ struct {
+ u32 synce_remndr : 6;
+ u32 synce_phlmt_en : 1;
+ u32 misc13 : 17;
+ u32 tspll_ck_refclkfreq : 8;
+ };
+ u32 val;
+};
+
+#define NAC_CGU_DWORD19 0x4c
+union nac_cgu_dword19 {
+ struct {
+ u32 tspll_fbdiv_intgr : 8;
+ u32 fdpll_ulck_thr : 5;
+ u32 misc15 : 3;
+ u32 tspll_ndivratio : 4;
+ u32 tspll_iref_ndivratio : 3;
+ u32 misc19 : 1;
+ u32 japll_ndivratio : 4;
+ u32 japll_iref_ndivratio : 3;
+ u32 misc27 : 1;
+ };
+ u32 val;
+};
+
+#define NAC_CGU_DWORD22 0x58
+union nac_cgu_dword22 {
+ struct {
+ u32 fdpll_frac_div_out_nc : 2;
+ u32 fdpll_lock_int_for : 1;
+ u32 synce_hdov_int_for : 1;
+ u32 synce_lock_int_for : 1;
+ u32 fdpll_phlead_slip_nc : 1;
+ u32 fdpll_acc1_ovfl_nc : 1;
+ u32 fdpll_acc2_ovfl_nc : 1;
+ u32 synce_status_nc : 6;
+ u32 fdpll_acc1f_ovfl : 1;
+ u32 misc18 : 1;
+ u32 fdpllclk_div : 4;
+ u32 time1588clk_div : 4;
+ u32 synceclk_div : 4;
+ u32 synceclk_sel_div2 : 1;
+ u32 fdpllclk_sel_div2 : 1;
+ u32 time1588clk_sel_div2 : 1;
+ u32 misc3 : 1;
+ };
+ u32 val;
+};
+
+#define NAC_CGU_DWORD23_E825C 0x5C
+union nac_cgu_dword23_e825c {
+ struct {
+ u32 cgupll_fbdiv_intgr : 10;
+ u32 ux56pll_fbdiv_intgr : 10;
+ u32 misc20 : 4;
+ u32 ts_pll_enable : 1;
+ u32 time_sync_tspll_align_sel : 1;
+ u32 ext_synce_sel : 1;
+ u32 ref1588_ck_div : 4;
+ u32 time_ref_sel : 1;
+
+ };
+ u32 val;
+};
+
+#define NAC_CGU_DWORD24 0x60
+union nac_cgu_dword24 {
+ struct {
+ u32 tspll_fbdiv_frac : 22;
+ u32 misc20 : 2;
+ u32 ts_pll_enable : 1;
+ u32 time_sync_tspll_align_sel : 1;
+ u32 ext_synce_sel : 1;
+ u32 ref1588_ck_div : 4;
+ u32 time_ref_sel : 1;
+ };
+ u32 val;
+};
+
+#define TSPLL_CNTR_BIST_SETTINGS 0x344
+union tspll_cntr_bist_settings {
+ struct {
+ u32 i_irefgen_settling_time_cntr_7_0 : 8;
+ u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
+ u32 reserved195 : 5;
+ u32 i_plllock_sel_0 : 1;
+ u32 i_plllock_sel_1 : 1;
+ u32 i_plllock_cnt_6_0 : 7;
+ u32 i_plllock_cnt_10_7 : 4;
+ u32 reserved200 : 4;
+ };
+ u32 val;
+};
+
+#define TSPLL_RO_BWM_LF 0x370
+union tspll_ro_bwm_lf {
+ struct {
+ u32 bw_freqov_high_cri_7_0 : 8;
+ u32 bw_freqov_high_cri_9_8 : 2;
+ u32 biascaldone_cri : 1;
+ u32 plllock_gain_tran_cri : 1;
+ u32 plllock_true_lock_cri : 1;
+ u32 pllunlock_flag_cri : 1;
+ u32 afcerr_cri : 1;
+ u32 afcdone_cri : 1;
+ u32 feedfwrdgain_cal_cri_7_0 : 8;
+ u32 m2fbdivmod_cri_7_0 : 8;
+ };
+ u32 val;
+};
+
+#define TSPLL_RO_LOCK_E825C 0x3f0
+union tspll_ro_lock_e825c {
+ struct {
+ u32 bw_freqov_high_cri_7_0 : 8;
+ u32 bw_freqov_high_cri_9_8 : 2;
+ u32 reserved455 : 1;
+ u32 plllock_gain_tran_cri : 1;
+ u32 plllock_true_lock_cri : 1;
+ u32 pllunlock_flag_cri : 1;
+ u32 afcerr_cri : 1;
+ u32 afcdone_cri : 1;
+ u32 feedfwrdgain_cal_cri_7_0 : 8;
+ u32 reserved462 : 8;
+ };
+ u32 val;
+};
+
+#define TSPLL_BW_TDC_E825C 0x31c
+union tspll_bw_tdc_e825c {
+ struct {
+ u32 i_tdc_offset_lock_1_0 : 2;
+ u32 i_bbthresh1_2_0 : 3;
+ u32 i_bbthresh2_2_0 : 3;
+ u32 i_tdcsel_1_0 : 2;
+ u32 i_tdcovccorr_en_h : 1;
+ u32 i_divretimeren : 1;
+ u32 i_bw_ampmeas_window : 1;
+ u32 i_bw_lowerbound_2_0 : 3;
+ u32 i_bw_upperbound_2_0 : 3;
+ u32 i_bw_mode_1_0 : 2;
+ u32 i_ft_mode_sel_2_0 : 3;
+ u32 i_bwphase_4_0 : 5;
+ u32 i_plllock_sel_1_0 : 2;
+ u32 i_afc_divratio : 1;
+ };
+ u32 val;
+};
+
int ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
int ice_check_reset(struct ice_hw *hw);
@@ -313,4 +487,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
+int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val);
+int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
index 003cdfada3ca820653e387fe9aec923018fc2427..7b748286f653319ccdd7d5c4adaf8ed055bd4a0a 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
@@ -339,167 +339,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
},
};
-const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
- /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
- {
- /* refclk_pre_div */
- 1,
- /* feedback_div */
- 197,
- /* frac_n_div */
- 2621440,
- /* post_pll_div */
- 6,
- },
-
- /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-
- /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-
- /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
- },
-
- /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
- },
-
- /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
- {
- /* refclk_pre_div */
- 10,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-};
-
-const
-struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
- /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x19,
- /* tspll_ndivratio */
- 1,
- /* tspll_fbdiv_intgr */
- 320,
- /* tspll_fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x29,
- /* tspll_ndivratio */
- 3,
- /* tspll_fbdiv_intgr */
- 195,
- /* tspll_fbdiv_frac */
- 1342177280UL,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x3E,
- /* tspll_ndivratio */
- 2,
- /* tspll_fbdiv_intgr */
- 128,
- /* tspll_fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x33,
- /* tspll_ndivratio */
- 3,
- /* tspll_fbdiv_intgr */
- 156,
- /* tspll_fbdiv_frac */
- 1073741824UL,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x1F,
- /* tspll_ndivratio */
- 5,
- /* tspll_fbdiv_intgr */
- 256,
- /* tspll_fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
- {
- /* tspll_ck_refclkfreq */
- 0x52,
- /* tspll_ndivratio */
- 3,
- /* tspll_fbdiv_intgr */
- 97,
- /* tspll_fbdiv_frac */
- 2818572288UL,
- /* ref1588_ck_div */
- 0,
- },
-};
-
/* struct ice_vernier_info_e82x
*
* E822 hardware calibrates the delay of the timestamp indication from the
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 657ca1b3bf70d25cc92881b5d665f489eabe8827..3bf45fd327ed826505667b986b1353bbb6e110d6 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -194,23 +194,6 @@ struct ice_eth56g_mac_reg_cfg {
extern
const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
-/**
- * struct ice_cgu_pll_params_e82x - E82X CGU parameters
- * @refclk_pre_div: Reference clock pre-divisor
- * @feedback_div: Feedback divisor
- * @frac_n_div: Fractional divisor
- * @post_pll_div: Post PLL divisor
- *
- * Clock Generation Unit parameters used to program the PLL based on the
- * selected TIME_REF frequency.
- */
-struct ice_cgu_pll_params_e82x {
- u32 refclk_pre_div;
- u32 feedback_div;
- u32 frac_n_div;
- u32 post_pll_div;
-};
-
#define E810C_QSFP_C827_0_HANDLE 2
#define E810C_QSFP_C827_1_HANDLE 3
enum ice_e810_c827_idx {
@@ -282,31 +265,6 @@ struct ice_cgu_pin_desc {
struct dpll_pin_frequency *freq_supp;
};
-extern const struct
-ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
-
-/**
- * struct ice_cgu_pll_params_e825c - E825C CGU parameters
- * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
- * @tspll_ndivratio: ndiv ratio that goes directly to the pll
- * @tspll_fbdiv_intgr: TS PLL integer feedback divide
- * @tspll_fbdiv_frac: TS PLL fractional feedback divide
- * @ref1588_ck_div: clock divider for tspll ref
- *
- * Clock Generation Unit parameters used to program the PLL based on the
- * selected TIME_REF/TCXO frequency.
- */
-struct ice_cgu_pll_params_e825c {
- u32 tspll_ck_refclkfreq;
- u32 tspll_ndivratio;
- u32 tspll_fbdiv_intgr;
- u32 tspll_fbdiv_frac;
- u32 ref1588_ck_div;
-};
-
-extern const struct
-ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];
-
#define E810C_QSFP_C827_0_HANDLE 2
#define E810C_QSFP_C827_1_HANDLE 3
@@ -328,7 +286,6 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
/* Device agnostic functions */
u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
-int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable);
bool ice_ptp_lock(struct ice_hw *hw);
void ice_ptp_unlock(struct ice_hw *hw);
void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ethernet/intel/ice/ice_tspll.h
new file mode 100644
index 0000000000000000000000000000000000000000..82ddcf4078fe32f0ade05ff1dc6c23cac742af11
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2025, Intel Corporation. */
+
+#ifndef _ICE_TSPLL_H_
+#define _ICE_TSPLL_H_
+
+/**
+ * struct ice_cgu_pll_params_e82x - E82X CGU parameters
+ * @refclk_pre_div: Reference clock pre-divisor
+ * @feedback_div: Feedback divisor
+ * @frac_n_div: Fractional divisor
+ * @post_pll_div: Post PLL divisor
+ *
+ * Clock Generation Unit parameters used to program the PLL based on the
+ * selected TIME_REF frequency.
+ */
+struct ice_cgu_pll_params_e82x {
+ u32 refclk_pre_div;
+ u32 feedback_div;
+ u32 frac_n_div;
+ u32 post_pll_div;
+};
+
+/**
+ * struct ice_cgu_pll_params_e825c - E825C CGU parameters
+ * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
+ * @tspll_ndivratio: ndiv ratio that goes directly to the pll
+ * @tspll_fbdiv_intgr: TS PLL integer feedback divide
+ * @tspll_fbdiv_frac: TS PLL fractional feedback divide
+ * @ref1588_ck_div: clock divider for tspll ref
+ *
+ * Clock Generation Unit parameters used to program the PLL based on the
+ * selected TIME_REF/TCXO frequency.
+ */
+struct ice_cgu_pll_params_e825c {
+ u32 tspll_ck_refclkfreq;
+ u32 tspll_ndivratio;
+ u32 tspll_fbdiv_intgr;
+ u32 tspll_fbdiv_frac;
+ u32 ref1588_ck_div;
+};
+
+int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable);
+int ice_init_cgu_e82x(struct ice_hw *hw);
+
+#endif /* _ICE_TSPLL_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 6e38d46c2c514a84ca2290a29e31b382e4263291..fd1a51fb2ab150d0b73aca33cd1380a9fc9a5aa1 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -6243,3 +6243,64 @@ u32 ice_get_link_speed(u16 index)
return ice_aq_to_link_speed[index];
}
+
+/**
+ * ice_read_cgu_reg_e82x - Read a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to read
+ * @val: storage for register value read
+ *
+ * Read the contents of a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ *
+ * Return: 0 on success, other error codes when failed to read from CGU.
+ */
+int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
+{
+ struct ice_sbq_msg_input cgu_msg = {
+ .opcode = ice_sbq_msg_rd,
+ .dest_dev = ice_sbq_dev_cgu,
+ .msg_addr_low = addr
+ };
+ int err;
+
+ err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
+ addr, err);
+ return err;
+ }
+
+ *val = cgu_msg.data;
+
+ return 0;
+}
+
+/**
+ * ice_write_cgu_reg_e82x - Write a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to write
+ * @val: value to write into the register
+ *
+ * Write the specified value to a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ *
+ * Return: 0 on success, other error codes when failed to write to CGU.
+ */
+int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
+{
+ struct ice_sbq_msg_input cgu_msg = {
+ .opcode = ice_sbq_msg_wr,
+ .dest_dev = ice_sbq_dev_cgu,
+ .msg_addr_low = addr,
+ .data = val
+ };
+ int err;
+
+ err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD);
+ if (err)
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
+ addr, err);
+
+ return err;
+}
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index b948a6d9226c41858faa3fea1b8ebd68a73b8897..16bf8b6ca928191b5ff5643a05b83362c448df54 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -4,7 +4,6 @@
#include "ice.h"
#include "ice_lib.h"
#include "ice_trace.h"
-#include "ice_cgu_regs.h"
static const char ice_pin_names[][64] = {
"SDP0",
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 0d17b7564cf78f972fadd2a6d2ffeaa1f1096b3a..29af8b958340c81062b1ea206789e69c9405648a 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -6,7 +6,6 @@
#include "ice_common.h"
#include "ice_ptp_hw.h"
#include "ice_ptp_consts.h"
-#include "ice_cgu_regs.h"
static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
DPLL_PIN_FREQUENCY_1PPS,
@@ -225,547 +224,6 @@ static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
}
-/**
- * ice_read_cgu_reg_e82x - Read a CGU register
- * @hw: pointer to the HW struct
- * @addr: Register address to read
- * @val: storage for register value read
- *
- * Read the contents of a register of the Clock Generation Unit. Only
- * applicable to E822 devices.
- *
- * Return: 0 on success, other error codes when failed to read from CGU
- */
-static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
-{
- struct ice_sbq_msg_input cgu_msg = {
- .opcode = ice_sbq_msg_rd,
- .dest_dev = ice_sbq_dev_cgu,
- .msg_addr_low = addr
- };
- int err;
-
- err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
- addr, err);
- return err;
- }
-
- *val = cgu_msg.data;
-
- return 0;
-}
-
-/**
- * ice_write_cgu_reg_e82x - Write a CGU register
- * @hw: pointer to the HW struct
- * @addr: Register address to write
- * @val: value to write into the register
- *
- * Write the specified value to a register of the Clock Generation Unit. Only
- * applicable to E822 devices.
- *
- * Return: 0 on success, other error codes when failed to write to CGU
- */
-static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
-{
- struct ice_sbq_msg_input cgu_msg = {
- .opcode = ice_sbq_msg_wr,
- .dest_dev = ice_sbq_dev_cgu,
- .msg_addr_low = addr,
- .data = val
- };
- int err;
-
- err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
- addr, err);
- return err;
- }
-
- return err;
-}
-
-/**
- * ice_clk_freq_str - Convert time_ref_freq to string
- * @clk_freq: Clock frequency
- *
- * Return: specified TIME_REF clock frequency converted to a string
- */
-static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
-{
- switch (clk_freq) {
- case ICE_TIME_REF_FREQ_25_000:
- return "25 MHz";
- case ICE_TIME_REF_FREQ_122_880:
- return "122.88 MHz";
- case ICE_TIME_REF_FREQ_125_000:
- return "125 MHz";
- case ICE_TIME_REF_FREQ_153_600:
- return "153.6 MHz";
- case ICE_TIME_REF_FREQ_156_250:
- return "156.25 MHz";
- case ICE_TIME_REF_FREQ_245_760:
- return "245.76 MHz";
- default:
- return "Unknown";
- }
-}
-
-/**
- * ice_clk_src_str - Convert time_ref_src to string
- * @clk_src: Clock source
- *
- * Return: specified clock source converted to its string name
- */
-static const char *ice_clk_src_str(enum ice_clk_src clk_src)
-{
- switch (clk_src) {
- case ICE_CLK_SRC_TCXO:
- return "TCXO";
- case ICE_CLK_SRC_TIME_REF:
- return "TIME_REF";
- default:
- return "Unknown";
- }
-}
-
-/**
- * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
- * @hw: pointer to the HW struct
- * @clk_freq: Clock frequency to program
- * @clk_src: Clock source to select (TIME_REF, or TCXO)
- *
- * Configure the Clock Generation Unit with the desired clock frequency and
- * time reference, enabling the PLL which drives the PTP hardware clock.
- *
- * Return:
- * * %0 - success
- * * %-EINVAL - input parameters are incorrect
- * * %-EBUSY - failed to lock TS PLL
- * * %other - CGU read/write failure
- */
-static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
- enum ice_time_ref_freq clk_freq,
- enum ice_clk_src clk_src)
-{
- union tspll_ro_bwm_lf bwm_lf;
- union nac_cgu_dword19 dw19;
- union nac_cgu_dword22 dw22;
- union nac_cgu_dword24 dw24;
- union nac_cgu_dword9 dw9;
- int err;
-
- if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
- dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
- clk_freq);
- return -EINVAL;
- }
-
- if (clk_src >= NUM_ICE_CLK_SRC) {
- dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
- clk_src);
- return -EINVAL;
- }
-
- if (clk_src == ICE_CLK_SRC_TCXO &&
- clk_freq != ICE_TIME_REF_FREQ_25_000) {
- dev_warn(ice_hw_to_dev(hw),
- "TCXO only supports 25 MHz frequency\n");
- return -EINVAL;
- }
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
-
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw24.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
-
- /* Disable the PLL before changing the clock source or frequency */
- if (dw24.ts_pll_enable) {
- dw24.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (err)
- return err;
- }
-
- /* Set the frequency */
- dw9.time_ref_freq_sel = clk_freq;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
- if (err)
- return err;
-
- /* Configure the TS PLL feedback divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
- if (err)
- return err;
-
- dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
- dw19.tspll_ndivratio = 1;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
- if (err)
- return err;
-
- /* Configure the TS PLL post divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
- if (err)
- return err;
-
- dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
- dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
- if (err)
- return err;
-
- /* Configure the TS PLL pre divisor and clock source */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (err)
- return err;
-
- dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
- dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
- dw24.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (err)
- return err;
-
- /* Finally, enable the PLL */
- dw24.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (err)
- return err;
-
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
-
- if (!bwm_lf.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
- return -EBUSY;
- }
-
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw24.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
-
- return 0;
-}
-
-/**
- * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
- * @hw: pointer to the HW struct
- * @clk_freq: Clock frequency to program
- * @clk_src: Clock source to select (TIME_REF, or TCXO)
- *
- * Configure the Clock Generation Unit with the desired clock frequency and
- * time reference, enabling the PLL which drives the PTP hardware clock.
- *
- * Return:
- * * %0 - success
- * * %-EINVAL - input parameters are incorrect
- * * %-EBUSY - failed to lock TS PLL
- * * %other - CGU read/write failure
- */
-static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
- enum ice_time_ref_freq clk_freq,
- enum ice_clk_src clk_src)
-{
- union tspll_ro_lock_e825c ro_lock;
- union nac_cgu_dword16_e825c dw16;
- union nac_cgu_dword23_e825c dw23;
- union nac_cgu_dword19 dw19;
- union nac_cgu_dword22 dw22;
- union nac_cgu_dword24 dw24;
- union nac_cgu_dword9 dw9;
- int err;
-
- if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
- dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
- clk_freq);
- return -EINVAL;
- }
-
- if (clk_src >= NUM_ICE_CLK_SRC) {
- dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
- clk_src);
- return -EINVAL;
- }
-
- if (clk_src == ICE_CLK_SRC_TCXO &&
- clk_freq != ICE_TIME_REF_FREQ_156_250) {
- dev_warn(ice_hw_to_dev(hw),
- "TCXO only supports 156.25 MHz frequency\n");
- return -EINVAL;
- }
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
-
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw23.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
-
- /* Disable the PLL before changing the clock source or frequency */
- if (dw23.ts_pll_enable) {
- dw23.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
- dw23.val);
- if (err)
- return err;
- }
-
- /* Set the frequency */
- dw9.time_ref_freq_sel = clk_freq;
-
- /* Enable the correct receiver */
- if (clk_src == ICE_CLK_SRC_TCXO) {
- dw9.time_ref_en = 0;
- dw9.clk_eref0_en = 1;
- } else {
- dw9.time_ref_en = 1;
- dw9.clk_eref0_en = 0;
- }
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
- if (err)
- return err;
-
- /* Choose the referenced frequency */
- dw16.tspll_ck_refclkfreq =
- e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
- if (err)
- return err;
-
- /* Configure the TS PLL feedback divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
- if (err)
- return err;
-
- dw19.tspll_fbdiv_intgr =
- e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
- dw19.tspll_ndivratio =
- e825c_cgu_params[clk_freq].tspll_ndivratio;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
- if (err)
- return err;
-
- /* Configure the TS PLL post divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
- if (err)
- return err;
-
- /* These two are constant for E825C */
- dw22.time1588clk_div = 5;
- dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
- if (err)
- return err;
-
- /* Configure the TS PLL pre divisor and clock source */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
- if (err)
- return err;
-
- dw23.ref1588_ck_div =
- e825c_cgu_params[clk_freq].ref1588_ck_div;
- dw23.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (err)
- return err;
-
- dw24.tspll_fbdiv_frac =
- e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (err)
- return err;
-
- /* Finally, enable the PLL */
- dw23.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (err)
- return err;
-
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
-
- if (!ro_lock.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
- return -EBUSY;
- }
-
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw23.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
-
- return 0;
-}
-
-#define ICE_ONE_PPS_OUT_AMP_MAX 3
-
-/**
- * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
- * @hw: pointer to the HW struct
- * @enable: true to enable 1PPS output, false to disable it
- *
- * Return: 0 on success, other negative error code when CGU read/write failed
- */
-int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable)
-{
- union nac_cgu_dword9 dw9;
- int err;
-
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
- if (err)
- return err;
-
- dw9.one_pps_out_en = enable;
- dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
- return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
-}
-
-/**
- * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
- * @hw: pointer to the HW struct
- *
- * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
- * losing TS PLL lock, but always show current state.
- *
- * Return: 0 on success, other error codes when failed to read/write CGU
- */
-static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
-{
- union tspll_cntr_bist_settings cntr_bist;
- int err;
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- &cntr_bist.val);
- if (err)
- return err;
-
- /* Disable sticky lock detection so lock err reported is accurate */
- cntr_bist.i_plllock_sel_0 = 0;
- cntr_bist.i_plllock_sel_1 = 0;
-
- return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- cntr_bist.val);
-}
-
-/**
- * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
- * @hw: pointer to the HW struct
- *
- * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
- * losing TS PLL lock, but always show current state.
- *
- * Return: 0 on success, other error codes when failed to read/write CGU
- */
-static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
-{
- union tspll_bw_tdc_e825c bw_tdc;
- int err;
-
- err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
- if (err)
- return err;
-
- bw_tdc.i_plllock_sel_1_0 = 0;
-
- return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
-}
-
-/**
- * ice_init_cgu_e82x - Initialize CGU with settings from firmware
- * @hw: pointer to the HW structure
- *
- * Initialize the Clock Generation Unit of the E822 device.
- *
- * Return: 0 on success, other error codes when failed to read/write/cfg CGU
- */
-static int ice_init_cgu_e82x(struct ice_hw *hw)
-{
- struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
- int err;
-
- /* Disable sticky lock detection so lock err reported is accurate */
- if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
- else
- err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
- if (err)
- return err;
-
- /* Configure the CGU PLL using the parameters from the function
- * capabilities.
- */
- if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
- else
- err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
-
- return err;
-}
-
/**
* ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
* @hw: pointer to HW struct
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
new file mode 100644
index 0000000000000000000000000000000000000000..520996e50d7632a5c6695943840b875cb2f0f9fe
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2025, Intel Corporation. */
+
+#include "ice.h"
+#include "ice_lib.h"
+#include "ice_ptp_hw.h"
+
+static const struct
+ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
+ /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ {
+ /* refclk_pre_div */
+ 1,
+ /* feedback_div */
+ 197,
+ /* frac_n_div */
+ 2621440,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+
+ /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+
+ /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 159,
+ /* frac_n_div */
+ 1572864,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ {
+ /* refclk_pre_div */
+ 5,
+ /* feedback_div */
+ 159,
+ /* frac_n_div */
+ 1572864,
+ /* post_pll_div */
+ 6,
+ },
+
+ /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ {
+ /* refclk_pre_div */
+ 10,
+ /* feedback_div */
+ 223,
+ /* frac_n_div */
+ 524288,
+ /* post_pll_div */
+ 7,
+ },
+};
+
+static const struct
+ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
+ /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x19,
+ /* tspll_ndivratio */
+ 1,
+ /* tspll_fbdiv_intgr */
+ 320,
+ /* tspll_fbdiv_frac */
+ 0,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x29,
+ /* tspll_ndivratio */
+ 3,
+ /* tspll_fbdiv_intgr */
+ 195,
+ /* tspll_fbdiv_frac */
+ 1342177280UL,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x3E,
+ /* tspll_ndivratio */
+ 2,
+ /* tspll_fbdiv_intgr */
+ 128,
+ /* tspll_fbdiv_frac */
+ 0,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x33,
+ /* tspll_ndivratio */
+ 3,
+ /* tspll_fbdiv_intgr */
+ 156,
+ /* tspll_fbdiv_frac */
+ 1073741824UL,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x1F,
+ /* tspll_ndivratio */
+ 5,
+ /* tspll_fbdiv_intgr */
+ 256,
+ /* tspll_fbdiv_frac */
+ 0,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x52,
+ /* tspll_ndivratio */
+ 3,
+ /* tspll_fbdiv_intgr */
+ 97,
+ /* tspll_fbdiv_frac */
+ 2818572288UL,
+ /* ref1588_ck_div */
+ 0,
+ },
+};
+
+/**
+ * ice_clk_freq_str - Convert time_ref_freq to string
+ * @clk_freq: Clock frequency
+ *
+ * Return: specified TIME_REF clock frequency converted to a string
+ */
+static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
+{
+ switch (clk_freq) {
+ case ICE_TIME_REF_FREQ_25_000:
+ return "25 MHz";
+ case ICE_TIME_REF_FREQ_122_880:
+ return "122.88 MHz";
+ case ICE_TIME_REF_FREQ_125_000:
+ return "125 MHz";
+ case ICE_TIME_REF_FREQ_153_600:
+ return "153.6 MHz";
+ case ICE_TIME_REF_FREQ_156_250:
+ return "156.25 MHz";
+ case ICE_TIME_REF_FREQ_245_760:
+ return "245.76 MHz";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_clk_src_str - Convert time_ref_src to string
+ * @clk_src: Clock source
+ *
+ * Return: specified clock source converted to its string name
+ */
+static const char *ice_clk_src_str(enum ice_clk_src clk_src)
+{
+ switch (clk_src) {
+ case ICE_CLK_SRC_TCXO:
+ return "TCXO";
+ case ICE_CLK_SRC_TIME_REF:
+ return "TIME_REF";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCXO)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ *
+ * Return:
+ * * %0 - success
+ * * %-EINVAL - input parameters are incorrect
+ * * %-EBUSY - failed to lock TS PLL
+ * * %other - CGU read/write failure
+ */
+static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
+ enum ice_time_ref_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ union tspll_ro_bwm_lf bwm_lf;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ int err;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
+ clk_freq);
+ return -EINVAL;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
+ clk_src);
+ return -EINVAL;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCXO &&
+ clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ dev_warn(ice_hw_to_dev(hw),
+ "TCXO only supports 25 MHz frequency\n");
+ return -EINVAL;
+ }
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (err)
+ return err;
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ str_enabled_disabled(dw24.ts_pll_enable),
+ ice_clk_src_str(dw24.time_ref_sel),
+ ice_clk_freq_str(dw9.time_ref_freq_sel),
+ bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+
+ /* Disable the PLL before changing the clock source or frequency */
+ if (dw24.ts_pll_enable) {
+ dw24.ts_pll_enable = 0;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
+ }
+
+ /* Set the frequency */
+ dw9.time_ref_freq_sel = clk_freq;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL feedback divisor */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ if (err)
+ return err;
+
+ dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
+ dw19.tspll_ndivratio = 1;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL post divisor */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ if (err)
+ return err;
+
+ dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
+ dw22.time1588clk_sel_div2 = 0;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL pre divisor and clock source */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
+
+ dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
+ dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
+ dw24.time_ref_sel = clk_src;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
+
+ /* Finally, enable the PLL */
+ dw24.ts_pll_enable = 1;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
+
+ /* Wait to verify if the PLL locks */
+ usleep_range(1000, 5000);
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (err)
+ return err;
+
+ if (!bwm_lf.plllock_true_lock_cri) {
+ dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
+ return -EBUSY;
+ }
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ str_enabled_disabled(dw24.ts_pll_enable),
+ ice_clk_src_str(dw24.time_ref_sel),
+ ice_clk_freq_str(dw9.time_ref_freq_sel),
+ bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+
+ return 0;
+}
+
+/**
+ * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
+ * @hw: pointer to the HW struct
+ *
+ * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
+ * losing TS PLL lock, but always show current state.
+ *
+ * Return: 0 on success, other error codes when failed to read/write CGU
+ */
+static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
+{
+ union tspll_cntr_bist_settings cntr_bist;
+ int err;
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
+ &cntr_bist.val);
+ if (err)
+ return err;
+
+ /* Disable sticky lock detection so lock err reported is accurate */
+ cntr_bist.i_plllock_sel_0 = 0;
+ cntr_bist.i_plllock_sel_1 = 0;
+
+ return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
+ cntr_bist.val);
+}
+
+/**
+ * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCXO)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ *
+ * Return:
+ * * %0 - success
+ * * %-EINVAL - input parameters are incorrect
+ * * %-EBUSY - failed to lock TS PLL
+ * * %other - CGU read/write failure
+ */
+static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
+ enum ice_time_ref_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ union tspll_ro_lock_e825c ro_lock;
+ union nac_cgu_dword16_e825c dw16;
+ union nac_cgu_dword23_e825c dw23;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ int err;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
+ clk_freq);
+ return -EINVAL;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
+ clk_src);
+ return -EINVAL;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCXO &&
+ clk_freq != ICE_TIME_REF_FREQ_156_250) {
+ dev_warn(ice_hw_to_dev(hw),
+ "TCXO only supports 156.25 MHz frequency\n");
+ return -EINVAL;
+ }
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ if (err)
+ return err;
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ if (err)
+ return err;
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ str_enabled_disabled(dw24.ts_pll_enable),
+ ice_clk_src_str(dw23.time_ref_sel),
+ ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+
+ /* Disable the PLL before changing the clock source or frequency */
+ if (dw23.ts_pll_enable) {
+ dw23.ts_pll_enable = 0;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
+ dw23.val);
+ if (err)
+ return err;
+ }
+
+ /* Set the frequency */
+ dw9.time_ref_freq_sel = clk_freq;
+
+ /* Enable the correct receiver */
+ if (clk_src == ICE_CLK_SRC_TCXO) {
+ dw9.time_ref_en = 0;
+ dw9.clk_eref0_en = 1;
+ } else {
+ dw9.time_ref_en = 1;
+ dw9.clk_eref0_en = 0;
+ }
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ if (err)
+ return err;
+
+ /* Choose the referenced frequency */
+ dw16.tspll_ck_refclkfreq =
+ e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL feedback divisor */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ if (err)
+ return err;
+
+ dw19.tspll_fbdiv_intgr =
+ e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
+ dw19.tspll_ndivratio =
+ e825c_cgu_params[clk_freq].tspll_ndivratio;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL post divisor */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ if (err)
+ return err;
+
+ /* These two are constant for E825C */
+ dw22.time1588clk_div = 5;
+ dw22.time1588clk_sel_div2 = 0;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ if (err)
+ return err;
+
+ /* Configure the TS PLL pre divisor and clock source */
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ if (err)
+ return err;
+
+ dw23.ref1588_ck_div =
+ e825c_cgu_params[clk_freq].ref1588_ck_div;
+ dw23.time_ref_sel = clk_src;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
+
+ dw24.tspll_fbdiv_frac =
+ e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
+
+ /* Finally, enable the PLL */
+ dw23.ts_pll_enable = 1;
+
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
+
+ /* Wait to verify if the PLL locks */
+ usleep_range(1000, 5000);
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ if (err)
+ return err;
+
+ if (!ro_lock.plllock_true_lock_cri) {
+ dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
+ return -EBUSY;
+ }
+
+ /* Log the current clock configuration */
+ ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ str_enabled_disabled(dw24.ts_pll_enable),
+ ice_clk_src_str(dw23.time_ref_sel),
+ ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+
+ return 0;
+}
+
+/**
+ * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
+ * @hw: pointer to the HW struct
+ *
+ * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
+ * losing TS PLL lock, but always show current state.
+ *
+ * Return: 0 on success, other error codes when failed to read/write CGU
+ */
+static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
+{
+ union tspll_bw_tdc_e825c bw_tdc;
+ int err;
+
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
+ if (err)
+ return err;
+
+ bw_tdc.i_plllock_sel_1_0 = 0;
+
+ return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
+}
+
+#define ICE_ONE_PPS_OUT_AMP_MAX 3
+
+/**
+ * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
+ * @hw: pointer to the HW struct
+ * @enable: true to enable 1PPS output, false to disable it
+ *
+ * Return: 0 on success, other negative error code when CGU read/write failed.
+ */
+int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable)
+{
+ union nac_cgu_dword9 dw9;
+ int err;
+
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (err)
+ return err;
+
+ dw9.one_pps_out_en = enable;
+ dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
+ return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+}
+
+/**
+ * ice_init_cgu_e82x - Initialize CGU with settings from firmware
+ * @hw: pointer to the HW structure
+ *
+ * Initialize the Clock Generation Unit of the E822 device.
+ *
+ * Return: 0 on success, other error codes when failed to read/write/cfg CGU
+ */
+int ice_init_cgu_e82x(struct ice_hw *hw)
+{
+ struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
+ int err;
+
+ /* Disable sticky lock detection so lock err reported is accurate */
+ if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
+ err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
+ else
+ err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
+ if (err)
+ return err;
+
+ /* Configure the CGU PLL using the parameters from the function
+ * capabilities.
+ */
+ if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
+ err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
+ (enum ice_clk_src)ts_info->clk_src);
+ else
+ err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
+ (enum ice_clk_src)ts_info->clk_src);
+
+ return err;
+}
diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile
index 9e0d9f710441192d912d5a5e0e70375ef975697e..d0f9c949236382f185997211e87879a2537cc8c8 100644
--- a/drivers/net/ethernet/intel/ice/Makefile
+++ b/drivers/net/ethernet/intel/ice/Makefile
@@ -53,7 +53,7 @@ ice-$(CONFIG_PCI_IOV) += \
ice_vf_mbx.o \
ice_vf_vsi_vlan_ops.o \
ice_vf_lib.o
-ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o
+ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o ice_tspll.o
ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o
ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o
ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file Jacob Keller
@ 2025-05-22 14:13 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:13 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, > Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Collect TSPLL related functions and definitions and move them to
a separate file to have all TSPLL functionality in one place.
>
> Move CGU related functions and definitions to ice_common.*
>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice.h | 1 +
> drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 181 -------
> drivers/net/ethernet/intel/ice/ice_common.h | 176 +++++++
> drivers/net/ethernet/intel/ice/ice_ptp_consts.h | 161 ------
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 43 --
> drivers/net/ethernet/intel/ice/ice_tspll.h | 46 ++
> drivers/net/ethernet/intel/ice/ice_common.c | 61 +++
> drivers/net/ethernet/intel/ice/ice_ptp.c | 1 -
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 542 --------------------
> drivers/net/ethernet/intel/ice/ice_tspll.c | 646 ++++++++++++++++++++++++
> drivers/net/ethernet/intel/ice/Makefile | 2 +-
> 11 files changed, 931 insertions(+), 929 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:15 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions Jacob Keller
` (12 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Rename TSPLL and CGU functions, definitions etc. to match the file name
and have consistent naming scheme.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 36 +--
drivers/net/ethernet/intel/ice/ice_ptp_consts.h | 16 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 11 +-
drivers/net/ethernet/intel/ice/ice_tspll.h | 32 +--
drivers/net/ethernet/intel/ice/ice_type.h | 20 +-
drivers/net/ethernet/intel/ice/ice_common.c | 28 +-
drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 4 +-
drivers/net/ethernet/intel/ice/ice_tspll.c | 350 ++++++++++++------------
9 files changed, 244 insertions(+), 255 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index 1a28dd41d8db46057d684c96b90d3a37fdbc7165..af88e274e989a03b3e2f793186a2b662c226bf83 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -39,8 +39,8 @@
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
-#define NAC_CGU_DWORD9 0x24
-union nac_cgu_dword9 {
+#define ICE_CGU_R9 0x24
+union ice_cgu_r9 {
struct {
u32 time_ref_freq_sel : 3;
u32 clk_eref1_en : 1;
@@ -62,24 +62,24 @@ union nac_cgu_dword9 {
u32 val;
};
-#define NAC_CGU_DWORD16_E825C 0x40
-union nac_cgu_dword16_e825c {
+#define ICE_CGU_R16 0x40
+union ice_cgu_r16 {
struct {
u32 synce_remndr : 6;
u32 synce_phlmt_en : 1;
u32 misc13 : 17;
- u32 tspll_ck_refclkfreq : 8;
+ u32 ck_refclkfreq : 8;
};
u32 val;
};
-#define NAC_CGU_DWORD19 0x4c
-union nac_cgu_dword19 {
+#define ICE_CGU_R19 0x4c
+union ice_cgu_r19 {
struct {
- u32 tspll_fbdiv_intgr : 8;
+ u32 fbdiv_intgr : 8;
u32 fdpll_ulck_thr : 5;
u32 misc15 : 3;
- u32 tspll_ndivratio : 4;
+ u32 ndivratio : 4;
u32 tspll_iref_ndivratio : 3;
u32 misc19 : 1;
u32 japll_ndivratio : 4;
@@ -89,8 +89,8 @@ union nac_cgu_dword19 {
u32 val;
};
-#define NAC_CGU_DWORD22 0x58
-union nac_cgu_dword22 {
+#define ICE_CGU_R22 0x58
+union ice_cgu_r22 {
struct {
u32 fdpll_frac_div_out_nc : 2;
u32 fdpll_lock_int_for : 1;
@@ -113,8 +113,8 @@ union nac_cgu_dword22 {
u32 val;
};
-#define NAC_CGU_DWORD23_E825C 0x5C
-union nac_cgu_dword23_e825c {
+#define ICE_CGU_R23 0x5C
+union ice_cgu_r23 {
struct {
u32 cgupll_fbdiv_intgr : 10;
u32 ux56pll_fbdiv_intgr : 10;
@@ -129,10 +129,10 @@ union nac_cgu_dword23_e825c {
u32 val;
};
-#define NAC_CGU_DWORD24 0x60
-union nac_cgu_dword24 {
+#define ICE_CGU_R24 0x60
+union ice_cgu_r24 {
struct {
- u32 tspll_fbdiv_frac : 22;
+ u32 fbdiv_frac : 22;
u32 misc20 : 2;
u32 ts_pll_enable : 1;
u32 time_sync_tspll_align_sel : 1;
@@ -487,6 +487,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
-int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val);
-int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val);
+int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);
+int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
index 7b748286f653319ccdd7d5c4adaf8ed055bd4a0a..19dddd9b53dddb0d91654cc1b8f03804ecb828df 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
@@ -281,7 +281,7 @@ struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
/* struct ice_time_ref_info_e82x
*
- * E822 hardware can use different sources as the reference for the PTP
+ * E82X hardware can use different sources as the reference for the PTP
* hardware clock. Each clock has different characteristics such as a slightly
* different frequency, etc.
*
@@ -289,8 +289,8 @@ struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
* reference. See the struct ice_time_ref_info_e82x for information about the
* meaning of each constant.
*/
-const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
- /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TSPLL_FREQ] = {
+ /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
{
/* pll_freq */
823437500, /* 823.4375 MHz PLL */
@@ -298,7 +298,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0x136e44fabULL,
},
- /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
{
/* pll_freq */
783360000, /* 783.36 MHz */
@@ -306,7 +306,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0x146cc2177ULL,
},
- /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
{
/* pll_freq */
796875000, /* 796.875 MHz */
@@ -314,7 +314,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0x141414141ULL,
},
- /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
{
/* pll_freq */
816000000, /* 816 MHz */
@@ -322,7 +322,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0x139b9b9baULL,
},
- /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
{
/* pll_freq */
830078125, /* 830.78125 MHz */
@@ -330,7 +330,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0x134679aceULL,
},
- /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
{
/* pll_freq */
783360000, /* 783.36 MHz */
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 3bf45fd327ed826505667b986b1353bbb6e110d6..5896b346e57901d054ba83470dd0d0f61e6d5fe5 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -272,7 +272,7 @@ struct ice_cgu_pin_desc {
extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
/* Table of constants related to possible TIME_REF sources */
-extern const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ];
+extern const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TSPLL_FREQ];
/* Table of constants for Vernier calibration on E822 */
extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
@@ -314,7 +314,8 @@ void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
*
* Returns the current TIME_REF from the capabilities structure.
*/
-static inline enum ice_time_ref_freq ice_e82x_time_ref(const struct ice_hw *hw)
+
+static inline enum ice_tspll_freq ice_e82x_time_ref(const struct ice_hw *hw)
{
return hw->func_caps.ts_func_info.time_ref;
}
@@ -328,17 +329,17 @@ static inline enum ice_time_ref_freq ice_e82x_time_ref(const struct ice_hw *hw)
* change, such as an update to the CGU registers.
*/
static inline void
-ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
+ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_tspll_freq time_ref)
{
hw->func_caps.ts_func_info.time_ref = time_ref;
}
-static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
+static inline u64 ice_e82x_pll_freq(enum ice_tspll_freq time_ref)
{
return e82x_time_ref[time_ref].pll_freq;
}
-static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
+static inline u64 ice_e82x_nominal_incval(enum ice_tspll_freq time_ref)
{
return e82x_time_ref[time_ref].nominal_incval;
}
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ethernet/intel/ice/ice_tspll.h
index 82ddcf4078fe32f0ade05ff1dc6c23cac742af11..3dcc525bb8292b635b58fe8107af47b895d3c201 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.h
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.h
@@ -5,16 +5,16 @@
#define _ICE_TSPLL_H_
/**
- * struct ice_cgu_pll_params_e82x - E82X CGU parameters
+ * struct ice_tspll_params_e82x - E82X TSPLL parameters
* @refclk_pre_div: Reference clock pre-divisor
* @feedback_div: Feedback divisor
* @frac_n_div: Fractional divisor
* @post_pll_div: Post PLL divisor
*
* Clock Generation Unit parameters used to program the PLL based on the
- * selected TIME_REF frequency.
+ * selected TIME_REF/TCXO frequency.
*/
-struct ice_cgu_pll_params_e82x {
+struct ice_tspll_params_e82x {
u32 refclk_pre_div;
u32 feedback_div;
u32 frac_n_div;
@@ -22,25 +22,25 @@ struct ice_cgu_pll_params_e82x {
};
/**
- * struct ice_cgu_pll_params_e825c - E825C CGU parameters
- * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
- * @tspll_ndivratio: ndiv ratio that goes directly to the pll
- * @tspll_fbdiv_intgr: TS PLL integer feedback divide
- * @tspll_fbdiv_frac: TS PLL fractional feedback divide
- * @ref1588_ck_div: clock divider for tspll ref
+ * struct ice_tspll_params_e825c - E825-C TSPLL parameters
+ * @ck_refclkfreq: ck_refclkfreq selection
+ * @ndivratio: ndiv ratio that goes directly to the PLL
+ * @fbdiv_intgr: TSPLL integer feedback divisor
+ * @fbdiv_frac: TSPLL fractional feedback divisor
+ * @ref1588_ck_div: clock divisor for tspll ref
*
* Clock Generation Unit parameters used to program the PLL based on the
* selected TIME_REF/TCXO frequency.
*/
-struct ice_cgu_pll_params_e825c {
- u32 tspll_ck_refclkfreq;
- u32 tspll_ndivratio;
- u32 tspll_fbdiv_intgr;
- u32 tspll_fbdiv_frac;
+struct ice_tspll_params_e825c {
+ u32 ck_refclkfreq;
+ u32 ndivratio;
+ u32 fbdiv_intgr;
+ u32 fbdiv_frac;
u32 ref1588_ck_div;
};
-int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable);
-int ice_init_cgu_e82x(struct ice_hw *hw);
+int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
+int ice_tspll_init(struct ice_hw *hw);
#endif /* _ICE_TSPLL_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h
index c09629c381e296f77aa31463643f4d187fd2f920..acc3ae3f7c27d95b9e49f33e190fc328d4bb1fa6 100644
--- a/drivers/net/ethernet/intel/ice/ice_type.h
+++ b/drivers/net/ethernet/intel/ice/ice_type.h
@@ -327,17 +327,17 @@ struct ice_hw_common_caps {
#define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
/* TIME_REF clock rate specification */
-enum ice_time_ref_freq {
- ICE_TIME_REF_FREQ_25_000 = 0,
- ICE_TIME_REF_FREQ_122_880 = 1,
- ICE_TIME_REF_FREQ_125_000 = 2,
- ICE_TIME_REF_FREQ_153_600 = 3,
- ICE_TIME_REF_FREQ_156_250 = 4,
- ICE_TIME_REF_FREQ_245_760 = 5,
+enum ice_tspll_freq {
+ ICE_TSPLL_FREQ_25_000 = 0,
+ ICE_TSPLL_FREQ_122_880 = 1,
+ ICE_TSPLL_FREQ_125_000 = 2,
+ ICE_TSPLL_FREQ_153_600 = 3,
+ ICE_TSPLL_FREQ_156_250 = 4,
+ ICE_TSPLL_FREQ_245_760 = 5,
- NUM_ICE_TIME_REF_FREQ,
+ NUM_ICE_TSPLL_FREQ,
- ICE_TIME_REF_FREQ_INVALID = -1,
+ ICE_TSPLL_FREQ_INVALID = -1,
};
/* Clock source specification */
@@ -350,7 +350,7 @@ enum ice_clk_src {
struct ice_ts_func_info {
/* Function specific info */
- enum ice_time_ref_freq time_ref;
+ enum ice_tspll_freq time_ref;
u8 clk_freq;
u8 clk_src;
u8 tmr_index_assoc;
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index fd1a51fb2ab150d0b73aca33cd1380a9fc9a5aa1..7d731d1be862311358943c6922354504ba4721ba 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2343,12 +2343,12 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
} else {
- info->clk_freq = ICE_TIME_REF_FREQ_156_250;
+ info->clk_freq = ICE_TSPLL_FREQ_156_250;
info->clk_src = ICE_CLK_SRC_TCXO;
}
- if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
- info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
+ if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {
+ info->time_ref = (enum ice_tspll_freq)info->clk_freq;
} else {
/* Unknown clock frequency, so assume a (probably incorrect)
* default to avoid out-of-bounds look ups of frequency
@@ -2356,7 +2356,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
*/
ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
info->clk_freq);
- info->time_ref = ICE_TIME_REF_FREQ_25_000;
+ info->time_ref = ICE_TSPLL_FREQ_25_000;
}
ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
@@ -6245,17 +6245,17 @@ u32 ice_get_link_speed(u16 index)
}
/**
- * ice_read_cgu_reg_e82x - Read a CGU register
- * @hw: pointer to the HW struct
+ * ice_read_cgu_reg - Read a CGU register
+ * @hw: Pointer to the HW struct
* @addr: Register address to read
- * @val: storage for register value read
+ * @val: Storage for register value read
*
* Read the contents of a register of the Clock Generation Unit. Only
- * applicable to E822 devices.
+ * applicable to E82X devices.
*
* Return: 0 on success, other error codes when failed to read from CGU.
*/
-int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
+int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val)
{
struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_rd,
@@ -6277,17 +6277,17 @@ int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
}
/**
- * ice_write_cgu_reg_e82x - Write a CGU register
- * @hw: pointer to the HW struct
+ * ice_write_cgu_reg - Write a CGU register
+ * @hw: Pointer to the HW struct
* @addr: Register address to write
- * @val: value to write into the register
+ * @val: Value to write into the register
*
* Write the specified value to a register of the Clock Generation Unit. Only
- * applicable to E822 devices.
+ * applicable to E82X devices.
*
* Return: 0 on success, other error codes when failed to write to CGU.
*/
-int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
+int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val)
{
struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_wr,
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 16bf8b6ca928191b5ff5643a05b83362c448df54..083f50f827441792d3b7a838c3359e05d2bbdf7c 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1636,7 +1636,7 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan,
int err;
/* Enable/disable CGU 1PPS output for E825C */
- err = ice_cgu_cfg_pps_out(hw, !!period);
+ err = ice_tspll_cfg_pps_out_e825c(hw, !!period);
if (err)
return err;
}
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 29af8b958340c81062b1ea206789e69c9405648a..6da82025934cb709d06f12cc26f9b494c6f4d772 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2126,7 +2126,7 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
static int ice_ptp_init_phc_e825(struct ice_hw *hw)
{
/* Initialize the Clock Generation Unit */
- return ice_init_cgu_e82x(hw);
+ return ice_tspll_init(hw);
}
/**
@@ -2799,7 +2799,7 @@ static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
wr32(hw, PF_SB_REM_DEV_CTL, val);
/* Initialize the Clock Generation Unit */
- err = ice_init_cgu_e82x(hw);
+ err = ice_tspll_init(hw);
if (err)
return err;
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 520996e50d7632a5c6695943840b875cb2f0f9fe..2fe619214a1a15d8d1d7bd5ac350c6ab58b75e81 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -6,8 +6,8 @@
#include "ice_ptp_hw.h"
static const struct
-ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
- /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
+ /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
{
/* refclk_pre_div */
1,
@@ -19,7 +19,7 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
6,
},
- /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
{
/* refclk_pre_div */
5,
@@ -31,7 +31,7 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
7,
},
- /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
{
/* refclk_pre_div */
5,
@@ -43,7 +43,7 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
7,
},
- /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
{
/* refclk_pre_div */
5,
@@ -55,7 +55,7 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
6,
},
- /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
{
/* refclk_pre_div */
5,
@@ -67,7 +67,7 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
6,
},
- /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
{
/* refclk_pre_div */
10,
@@ -81,86 +81,86 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
};
static const struct
-ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
- /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ice_tspll_params_e825c e825c_tspll_params[NUM_ICE_TSPLL_FREQ] = {
+ /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x19,
- /* tspll_ndivratio */
+ /* ndivratio */
1,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
320,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
- /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x29,
- /* tspll_ndivratio */
+ /* ndivratio */
3,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
195,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
1342177280UL,
/* ref1588_ck_div */
0,
},
- /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x3E,
- /* tspll_ndivratio */
+ /* ndivratio */
2,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
128,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
- /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x33,
- /* tspll_ndivratio */
+ /* ndivratio */
3,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
156,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
1073741824UL,
/* ref1588_ck_div */
0,
},
- /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
+ /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x1F,
- /* tspll_ndivratio */
+ /* ndivratio */
5,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
256,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
- /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
+ /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
{
- /* tspll_ck_refclkfreq */
+ /* ck_refclkfreq */
0x52,
- /* tspll_ndivratio */
+ /* ndivratio */
3,
- /* tspll_fbdiv_intgr */
+ /* fbdiv_intgr */
97,
- /* tspll_fbdiv_frac */
+ /* fbdiv_frac */
2818572288UL,
/* ref1588_ck_div */
0,
@@ -168,25 +168,25 @@ ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
};
/**
- * ice_clk_freq_str - Convert time_ref_freq to string
+ * ice_tspll_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
*
- * Return: specified TIME_REF clock frequency converted to a string
+ * Return: specified TIME_REF clock frequency converted to a string.
*/
-static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
+static const char *ice_tspll_clk_freq_str(enum ice_tspll_freq clk_freq)
{
switch (clk_freq) {
- case ICE_TIME_REF_FREQ_25_000:
+ case ICE_TSPLL_FREQ_25_000:
return "25 MHz";
- case ICE_TIME_REF_FREQ_122_880:
+ case ICE_TSPLL_FREQ_122_880:
return "122.88 MHz";
- case ICE_TIME_REF_FREQ_125_000:
+ case ICE_TSPLL_FREQ_125_000:
return "125 MHz";
- case ICE_TIME_REF_FREQ_153_600:
+ case ICE_TSPLL_FREQ_153_600:
return "153.6 MHz";
- case ICE_TIME_REF_FREQ_156_250:
+ case ICE_TSPLL_FREQ_156_250:
return "156.25 MHz";
- case ICE_TIME_REF_FREQ_245_760:
+ case ICE_TSPLL_FREQ_245_760:
return "245.76 MHz";
default:
return "Unknown";
@@ -194,12 +194,12 @@ static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
}
/**
- * ice_clk_src_str - Convert time_ref_src to string
+ * ice_tspll_clk_src_str - Convert time_ref_src to string
* @clk_src: Clock source
*
* Return: specified clock source converted to its string name
*/
-static const char *ice_clk_src_str(enum ice_clk_src clk_src)
+static const char *ice_tspll_clk_src_str(enum ice_clk_src clk_src)
{
switch (clk_src) {
case ICE_CLK_SRC_TCXO:
@@ -212,8 +212,8 @@ static const char *ice_clk_src_str(enum ice_clk_src clk_src)
}
/**
- * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
- * @hw: pointer to the HW struct
+ * ice_tspll_cfg_e82x - Configure the Clock Generation Unit TSPLL
+ * @hw: Pointer to the HW struct
* @clk_freq: Clock frequency to program
* @clk_src: Clock source to select (TIME_REF, or TCXO)
*
@@ -223,21 +223,20 @@ static const char *ice_clk_src_str(enum ice_clk_src clk_src)
* Return:
* * %0 - success
* * %-EINVAL - input parameters are incorrect
- * * %-EBUSY - failed to lock TS PLL
+ * * %-EBUSY - failed to lock TSPLL
* * %other - CGU read/write failure
*/
-static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
- enum ice_time_ref_freq clk_freq,
- enum ice_clk_src clk_src)
+static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
+ enum ice_clk_src clk_src)
{
union tspll_ro_bwm_lf bwm_lf;
- union nac_cgu_dword19 dw19;
- union nac_cgu_dword22 dw22;
- union nac_cgu_dword24 dw24;
- union nac_cgu_dword9 dw9;
+ union ice_cgu_r19 dw19;
+ union ice_cgu_r22 dw22;
+ union ice_cgu_r24 dw24;
+ union ice_cgu_r9 dw9;
int err;
- if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
clk_freq);
return -EINVAL;
@@ -249,129 +248,127 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
return -EINVAL;
}
- if (clk_src == ICE_CLK_SRC_TCXO &&
- clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_25_000) {
dev_warn(ice_hw_to_dev(hw),
"TCXO only supports 25 MHz frequency\n");
return -EINVAL;
}
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
/* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw24.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ice_tspll_clk_src_str(dw24.time_ref_sel),
+ ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
dw24.ts_pll_enable = 0;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
if (err)
return err;
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
if (err)
return err;
- /* Configure the TS PLL feedback divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ /* Configure the TSPLL feedback divisor */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
if (err)
return err;
- dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
- dw19.tspll_ndivratio = 1;
+ dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
+ dw19.ndivratio = 1;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
return err;
- /* Configure the TS PLL post divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ /* Configure the TSPLL post divisor */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
if (err)
return err;
- dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
+ dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
dw22.time1588clk_sel_div2 = 0;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
if (err)
return err;
- /* Configure the TS PLL pre divisor and clock source */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ /* Configure the TSPLL pre divisor and clock source */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
if (err)
return err;
- dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
- dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
+ dw24.ref1588_ck_div = e82x_tspll_params[clk_freq].refclk_pre_div;
+ dw24.fbdiv_frac = e82x_tspll_params[clk_freq].frac_n_div;
dw24.time_ref_sel = clk_src;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
if (err)
return err;
/* Finally, enable the PLL */
dw24.ts_pll_enable = 1;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
if (err)
return err;
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
if (!bwm_lf.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
+ dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
}
/* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw24.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ice_tspll_clk_src_str(dw24.time_ref_sel),
+ ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
return 0;
}
/**
- * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
- * @hw: pointer to the HW struct
+ * ice_tspll_dis_sticky_bits_e82x - disable TSPLL sticky bits
+ * @hw: Pointer to the HW struct
*
- * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
- * losing TS PLL lock, but always show current state.
+ * Configure the Clock Generation Unit TSPLL sticky bits so they don't latch on
+ * losing TSPLL lock, but always show current state.
*
- * Return: 0 on success, other error codes when failed to read/write CGU
+ * Return: 0 on success, other error codes when failed to read/write CGU.
*/
-static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
+static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
{
union tspll_cntr_bist_settings cntr_bist;
int err;
- err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- &cntr_bist.val);
+ err = ice_read_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
if (err)
return err;
@@ -379,13 +376,12 @@ static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
cntr_bist.i_plllock_sel_0 = 0;
cntr_bist.i_plllock_sel_1 = 0;
- return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- cntr_bist.val);
+ return ice_write_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, cntr_bist.val);
}
/**
- * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
- * @hw: pointer to the HW struct
+ * ice_tspll_cfg_e825c - Configure the TSPLL for E825-C
+ * @hw: Pointer to the HW struct
* @clk_freq: Clock frequency to program
* @clk_src: Clock source to select (TIME_REF, or TCXO)
*
@@ -395,23 +391,22 @@ static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
* Return:
* * %0 - success
* * %-EINVAL - input parameters are incorrect
- * * %-EBUSY - failed to lock TS PLL
+ * * %-EBUSY - failed to lock TSPLL
* * %other - CGU read/write failure
*/
-static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
- enum ice_time_ref_freq clk_freq,
- enum ice_clk_src clk_src)
+static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
+ enum ice_clk_src clk_src)
{
union tspll_ro_lock_e825c ro_lock;
- union nac_cgu_dword16_e825c dw16;
- union nac_cgu_dword23_e825c dw23;
- union nac_cgu_dword19 dw19;
- union nac_cgu_dword22 dw22;
- union nac_cgu_dword24 dw24;
- union nac_cgu_dword9 dw9;
+ union ice_cgu_r16 dw16;
+ union ice_cgu_r23 dw23;
+ union ice_cgu_r19 dw19;
+ union ice_cgu_r22 dw22;
+ union ice_cgu_r24 dw24;
+ union ice_cgu_r9 dw9;
int err;
- if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
clk_freq);
return -EINVAL;
@@ -423,46 +418,44 @@ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
return -EINVAL;
}
- if (clk_src == ICE_CLK_SRC_TCXO &&
- clk_freq != ICE_TIME_REF_FREQ_156_250) {
+ if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_156_250) {
dev_warn(ice_hw_to_dev(hw),
"TCXO only supports 156.25 MHz frequency\n");
return -EINVAL;
}
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R16, &dw16.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
if (err)
return err;
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (err)
return err;
/* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw23.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ice_tspll_clk_src_str(dw23.time_ref_sel),
+ ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
dw23.ts_pll_enable = 0;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
- dw23.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
}
@@ -478,33 +471,30 @@ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
if (err)
return err;
/* Choose the referenced frequency */
- dw16.tspll_ck_refclkfreq =
- e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
+ dw16.ck_refclkfreq = e825c_tspll_params[clk_freq].ck_refclkfreq;
+ err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
if (err)
return err;
- /* Configure the TS PLL feedback divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ /* Configure the TSPLL feedback divisor */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
if (err)
return err;
- dw19.tspll_fbdiv_intgr =
- e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
- dw19.tspll_ndivratio =
- e825c_cgu_params[clk_freq].tspll_ndivratio;
+ dw19.fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
+ dw19.ndivratio = e825c_tspll_params[clk_freq].ndivratio;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
return err;
- /* Configure the TS PLL post divisor */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ /* Configure the TSPLL post divisor */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
if (err)
return err;
@@ -512,135 +502,133 @@ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
dw22.time1588clk_div = 5;
dw22.time1588clk_sel_div2 = 0;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
if (err)
return err;
- /* Configure the TS PLL pre divisor and clock source */
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ /* Configure the TSPLL pre divisor and clock source */
+ err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
if (err)
return err;
- dw23.ref1588_ck_div =
- e825c_cgu_params[clk_freq].ref1588_ck_div;
+ dw23.ref1588_ck_div = e825c_tspll_params[clk_freq].ref1588_ck_div;
dw23.time_ref_sel = clk_src;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
- dw24.tspll_fbdiv_frac =
- e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
+ dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
if (err)
return err;
/* Finally, enable the PLL */
dw23.ts_pll_enable = 1;
- err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (err)
return err;
if (!ro_lock.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
+ dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
}
/* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
+ ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
str_enabled_disabled(dw24.ts_pll_enable),
- ice_clk_src_str(dw23.time_ref_sel),
- ice_clk_freq_str(dw9.time_ref_freq_sel),
+ ice_tspll_clk_src_str(dw23.time_ref_sel),
+ ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
return 0;
}
/**
- * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
- * @hw: pointer to the HW struct
+ * ice_tspll_dis_sticky_bits_e825c - disable TSPLL sticky bits for E825-C
+ * @hw: Pointer to the HW struct
*
- * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
- * losing TS PLL lock, but always show current state.
+ * Configure the Clock Generation Unit TSPLL sticky bits so they don't latch on
+ * losing TSPLL lock, but always show current state.
*
- * Return: 0 on success, other error codes when failed to read/write CGU
+ * Return: 0 on success, other error codes when failed to read/write CGU.
*/
-static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
+static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
union tspll_bw_tdc_e825c bw_tdc;
int err;
- err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
+ err = ice_read_cgu_reg(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
if (err)
return err;
bw_tdc.i_plllock_sel_1_0 = 0;
- return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
+ return ice_write_cgu_reg(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
}
#define ICE_ONE_PPS_OUT_AMP_MAX 3
/**
- * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
+ * ice_tspll_cfg_pps_out_e825c - Enable/disable 1PPS output and set amplitude
* @hw: pointer to the HW struct
* @enable: true to enable 1PPS output, false to disable it
*
* Return: 0 on success, other negative error code when CGU read/write failed.
*/
-int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable)
+int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
{
- union nac_cgu_dword9 dw9;
+ union ice_cgu_r9 r9;
int err;
- err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9.val);
if (err)
return err;
- dw9.one_pps_out_en = enable;
- dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
- return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ r9.one_pps_out_en = enable;
+ r9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
+ return ice_write_cgu_reg(hw, ICE_CGU_R9, r9.val);
}
/**
- * ice_init_cgu_e82x - Initialize CGU with settings from firmware
- * @hw: pointer to the HW structure
+ * ice_tspll_init - Initialize TSPLL with settings from firmware
+ * @hw: Pointer to the HW structure
*
- * Initialize the Clock Generation Unit of the E822 device.
+ * Initialize the Clock Generation Unit of the E82X/E825 device.
*
- * Return: 0 on success, other error codes when failed to read/write/cfg CGU
+ * Return: 0 on success, other error codes when failed to read/write/cfg CGU.
*/
-int ice_init_cgu_e82x(struct ice_hw *hw)
+int ice_tspll_init(struct ice_hw *hw)
{
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
int err;
- /* Disable sticky lock detection so lock err reported is accurate */
+ /* Disable sticky lock detection so lock err reported is accurate. */
if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
+ err = ice_tspll_dis_sticky_bits_e825c(hw);
else
- err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
+ err = ice_tspll_dis_sticky_bits_e82x(hw);
if (err)
return err;
- /* Configure the CGU PLL using the parameters from the function
+ /* Configure the TSPLL using the parameters from the function
* capabilities.
*/
if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
+ err = ice_tspll_cfg_e825c(hw, ts_info->time_ref,
+ (enum ice_clk_src)ts_info->clk_src);
else
- err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
+ err = ice_tspll_cfg_e82x(hw, ts_info->time_ref,
+ (enum ice_clk_src)ts_info->clk_src);
return err;
}
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions Jacob Keller
@ 2025-05-22 14:15 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:15 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Rename TSPLL and CGU functions, definitions etc. to match the file name and have consistent naming scheme.
>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.h | 36 +--
> drivers/net/ethernet/intel/ice/ice_ptp_consts.h | 16 +-
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 11 +-
> drivers/net/ethernet/intel/ice/ice_tspll.h | 32 +--
> drivers/net/ethernet/intel/ice/ice_type.h | 20 +-
> drivers/net/ethernet/intel/ice/ice_common.c | 28 +-
> drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +-
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 4 +-
> drivers/net/ethernet/intel/ice/ice_tspll.c | 350 ++++++++++++------------
> 9 files changed, 244 insertions(+), 255 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 01/15] ice: move TSPLL functions to a separate file Jacob Keller
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:18 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions Jacob Keller
` (11 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
The E825-C hardware has a slightly different register layout for register
19 of the Clock Generation Unit and TSPLL. The fbdiv_intgr value can be 10
bits wide.
Additionally, most of the fields that were in register 24 are made
available in register 23 instead. The programming logic already has a
corrected definition for register 23, but it incorrectly still used the
8-bit definition of fbdiv_intgr. This results in truncating some of the
values of fbdiv_intgr, including the value used for the 156.25MHz signal.
The driver only used register 24 to obtain the enable status, which we
should read from register 23. This results in an incorrect output for the
log messages, but does not change any functionality besides
disabled-by-default dynamic debug messages.
Fix the register definitions, and adjust the code to properly reflect the
enable/disable status in the log messages.
Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 17 ++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_tspll.c | 17 +++++++----------
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index af88e274e989a03b3e2f793186a2b662c226bf83..86b34fb02d41b01640ee8b913ff2fc82fde85b68 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -74,7 +74,7 @@ union ice_cgu_r16 {
};
#define ICE_CGU_R19 0x4c
-union ice_cgu_r19 {
+union ice_cgu_r19_e82x {
struct {
u32 fbdiv_intgr : 8;
u32 fdpll_ulck_thr : 5;
@@ -89,6 +89,21 @@ union ice_cgu_r19 {
u32 val;
};
+union ice_cgu_r19_e825 {
+ struct {
+ u32 tspll_fbdiv_intgr : 10;
+ u32 fdpll_ulck_thr : 5;
+ u32 misc15 : 1;
+ u32 tspll_ndivratio : 4;
+ u32 tspll_iref_ndivratio : 3;
+ u32 misc19 : 1;
+ u32 japll_ndivratio : 4;
+ u32 japll_postdiv_pdivratio : 3;
+ u32 misc27 : 1;
+ };
+ u32 val;
+};
+
#define ICE_CGU_R22 0x58
union ice_cgu_r22 {
struct {
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 2fe619214a1a15d8d1d7bd5ac350c6ab58b75e81..74a9fc35fb1a6bc1011fe8142566a14673e867d9 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -230,7 +230,7 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_bwm_lf bwm_lf;
- union ice_cgu_r19 dw19;
+ union ice_cgu_r19_e82x dw19;
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
@@ -398,9 +398,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_lock_e825c ro_lock;
+ union ice_cgu_r19_e825 dw19;
union ice_cgu_r16 dw16;
union ice_cgu_r23 dw23;
- union ice_cgu_r19 dw19;
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
@@ -428,10 +428,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
err = ice_read_cgu_reg(hw, ICE_CGU_R16, &dw16.val);
if (err)
return err;
@@ -446,7 +442,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
+ str_enabled_disabled(dw23.ts_pll_enable),
ice_tspll_clk_src_str(dw23.time_ref_sel),
ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
@@ -486,8 +482,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- dw19.fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
- dw19.ndivratio = e825c_tspll_params[clk_freq].ndivratio;
+ dw19.tspll_fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
+ dw19.tspll_ndivratio = e825c_tspll_params[clk_freq].ndivratio;
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
@@ -518,6 +514,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
+ dw24.val = 0;
dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
@@ -545,7 +542,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
+ str_enabled_disabled(dw23.ts_pll_enable),
ice_tspll_clk_src_str(dw23.time_ref_sel),
ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions Jacob Keller
@ 2025-05-22 14:18 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:18 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, > Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions
>
> The E825-C hardware has a slightly different register layout for register
19 of the Clock Generation Unit and TSPLL. The fbdiv_intgr value can be 10 bits wide.
>
> Additionally, most of the fields that were in register 24 are made available in register 23 instead. The programming logic already has a corrected definition for register 23, but it incorrectly still used the 8-bit definition of fbdiv_intgr. This results in truncating some of the values of fbdiv_intgr, including the value used for the 156.25MHz signal.
>
> The driver only used register 24 to obtain the enable status, which we should read from register 23. This results in an incorrect output for the log messages, but does not change any functionality besides disabled-by-default dynamic debug messages.
>
> Fix the register definitions, and adjust the code to properly reflect the enable/disable status in the log messages.
>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.h | 17 ++++++++++++++++- drivers/net/ethernet/intel/ice/ice_tspll.c | 17 +++++++----------
> 2 files changed, 23 insertions(+), 11 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (2 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:19 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts Jacob Keller
` (10 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Remove ice_tspll_params_e825 definitions as according to EDS (Electrical
Design Specification) doc, E825 devices support only 156.25 MHz TSPLL
frequency for both TCXO and TIME_REF clock source.
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.h | 21 +-----
drivers/net/ethernet/intel/ice/ice_tspll.c | 107 +++--------------------------
2 files changed, 11 insertions(+), 117 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ethernet/intel/ice/ice_tspll.h
index 3dcc525bb8292b635b58fe8107af47b895d3c201..7aef430258e23e8e65cfc37ef8436ac158fa7ee5 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.h
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.h
@@ -21,24 +21,9 @@ struct ice_tspll_params_e82x {
u32 post_pll_div;
};
-/**
- * struct ice_tspll_params_e825c - E825-C TSPLL parameters
- * @ck_refclkfreq: ck_refclkfreq selection
- * @ndivratio: ndiv ratio that goes directly to the PLL
- * @fbdiv_intgr: TSPLL integer feedback divisor
- * @fbdiv_frac: TSPLL fractional feedback divisor
- * @ref1588_ck_div: clock divisor for tspll ref
- *
- * Clock Generation Unit parameters used to program the PLL based on the
- * selected TIME_REF/TCXO frequency.
- */
-struct ice_tspll_params_e825c {
- u32 ck_refclkfreq;
- u32 ndivratio;
- u32 fbdiv_intgr;
- u32 fbdiv_frac;
- u32 ref1588_ck_div;
-};
+#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
+#define ICE_TSPLL_NDIVRATIO_E825 5
+#define ICE_TSPLL_FBDIV_INTGR_E825 256
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
int ice_tspll_init(struct ice_hw *hw);
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 74a9fc35fb1a6bc1011fe8142566a14673e867d9..eb7fbae719843e8b446f78943a2edcc4d5a9de6c 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -80,93 +80,6 @@ ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
},
};
-static const struct
-ice_tspll_params_e825c e825c_tspll_params[NUM_ICE_TSPLL_FREQ] = {
- /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
- {
- /* ck_refclkfreq */
- 0x19,
- /* ndivratio */
- 1,
- /* fbdiv_intgr */
- 320,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
- {
- /* ck_refclkfreq */
- 0x29,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 195,
- /* fbdiv_frac */
- 1342177280UL,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
- {
- /* ck_refclkfreq */
- 0x3E,
- /* ndivratio */
- 2,
- /* fbdiv_intgr */
- 128,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
- {
- /* ck_refclkfreq */
- 0x33,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 156,
- /* fbdiv_frac */
- 1073741824UL,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
- {
- /* ck_refclkfreq */
- 0x1F,
- /* ndivratio */
- 5,
- /* fbdiv_intgr */
- 256,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
- {
- /* ck_refclkfreq */
- 0x52,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 97,
- /* fbdiv_frac */
- 2818572288UL,
- /* ref1588_ck_div */
- 0,
- },
-};
-
/**
* ice_tspll_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
@@ -402,7 +315,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r16 dw16;
union ice_cgu_r23 dw23;
union ice_cgu_r22 dw22;
- union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
int err;
@@ -418,9 +330,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_156_250) {
- dev_warn(ice_hw_to_dev(hw),
- "TCXO only supports 156.25 MHz frequency\n");
+ if (clk_freq != ICE_TSPLL_FREQ_156_250) {
+ dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
return -EINVAL;
}
@@ -472,7 +383,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return err;
/* Choose the referenced frequency */
- dw16.ck_refclkfreq = e825c_tspll_params[clk_freq].ck_refclkfreq;
+ dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
if (err)
return err;
@@ -482,8 +393,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- dw19.tspll_fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
- dw19.tspll_ndivratio = e825c_tspll_params[clk_freq].ndivratio;
+ dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
+ dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
@@ -507,17 +418,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- dw23.ref1588_ck_div = e825c_tspll_params[clk_freq].ref1588_ck_div;
+ dw23.ref1588_ck_div = 0;
dw23.time_ref_sel = clk_src;
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
- dw24.val = 0;
- dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
+ /* Clear the R24 register. */
+ err = ice_write_cgu_reg(hw, ICE_CGU_R24, 0);
if (err)
return err;
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions Jacob Keller
@ 2025-05-22 14:19 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:19 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, > Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Remove ice_tspll_params_e825 definitions as according to EDS (Electrical Design Specification) doc, E825 devices support only 156.25 MHz TSPLL frequency for both TCXO and TIME_REF clock source.
>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.h | 21 +----- drivers/net/ethernet/intel/ice/ice_tspll.c | 107 +++--------------------------
> 2 files changed, 11 insertions(+), 117 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (3 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:21 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper Jacob Keller
` (9 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Instead of multiple comments, use designated initializers for TSPLL
consts.
Adjust ice_tspll_params_e82x fields sizes.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.h | 8 +--
drivers/net/ethernet/intel/ice/ice_tspll.c | 95 ++++++++++--------------------
2 files changed, 34 insertions(+), 69 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ethernet/intel/ice/ice_tspll.h
index 7aef430258e23e8e65cfc37ef8436ac158fa7ee5..c0b1232cc07c3ebd73264d16fc9cd8bfaec29fec 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.h
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.h
@@ -7,18 +7,18 @@
/**
* struct ice_tspll_params_e82x - E82X TSPLL parameters
* @refclk_pre_div: Reference clock pre-divisor
+ * @post_pll_div: Post PLL divisor
* @feedback_div: Feedback divisor
* @frac_n_div: Fractional divisor
- * @post_pll_div: Post PLL divisor
*
* Clock Generation Unit parameters used to program the PLL based on the
* selected TIME_REF/TCXO frequency.
*/
struct ice_tspll_params_e82x {
- u32 refclk_pre_div;
- u32 feedback_div;
+ u8 refclk_pre_div;
+ u8 post_pll_div;
+ u8 feedback_div;
u32 frac_n_div;
- u32 post_pll_div;
};
#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index eb7fbae719843e8b446f78943a2edcc4d5a9de6c..cf0e37296796c5bbda011d027dc8ef007b0e2021 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -7,76 +7,41 @@
static const struct
ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
- /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
- {
- /* refclk_pre_div */
- 1,
- /* feedback_div */
- 197,
- /* frac_n_div */
- 2621440,
- /* post_pll_div */
- 6,
+ [ICE_TSPLL_FREQ_25_000] = {
+ .refclk_pre_div = 1,
+ .post_pll_div = 6,
+ .feedback_div = 197,
+ .frac_n_div = 2621440,
},
-
- /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
+ [ICE_TSPLL_FREQ_122_880] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
},
-
- /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
+ [ICE_TSPLL_FREQ_125_000] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
},
-
- /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
+ [ICE_TSPLL_FREQ_153_600] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 6,
+ .feedback_div = 159,
+ .frac_n_div = 1572864
},
-
- /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
+ [ICE_TSPLL_FREQ_156_250] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 6,
+ .feedback_div = 159,
+ .frac_n_div = 1572864
},
-
- /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
- {
- /* refclk_pre_div */
- 10,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
+ [ICE_TSPLL_FREQ_245_760] = {
+ .refclk_pre_div = 10,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
},
};
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts Jacob Keller
@ 2025-05-22 14:21 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:21 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Instead of multiple comments, use designated initializers for TSPLL consts.
>
> Adjust ice_tspll_params_e82x fields sizes.
>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.h | 8 +-- drivers/net/ethernet/intel/ice/ice_tspll.c | 95 ++++++++++--------------------
> 2 files changed, 34 insertions(+), 69 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (4 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 05/15] ice: use designated initializers for TSPLL consts Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:23 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers Jacob Keller
` (8 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Add a helper function to print new/current TSPLL config. This helps
avoid unnecessary casts from u8 to enums.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 54 +++++++++++++++++-------------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index cf0e37296796c5bbda011d027dc8ef007b0e2021..08af4ced50eb877dce5944d87a90d0dcdb49ff2e 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -89,6 +89,26 @@ static const char *ice_tspll_clk_src_str(enum ice_clk_src clk_src)
}
}
+/**
+ * ice_tspll_log_cfg - Log current/new TSPLL configuration
+ * @hw: Pointer to the HW struct
+ * @enable: CGU enabled/disabled
+ * @clk_src: Current clock source
+ * @tspll_freq: Current clock frequency
+ * @lock: CGU lock status
+ * @new_cfg: true if this is a new config
+ */
+static void ice_tspll_log_cfg(struct ice_hw *hw, bool enable, u8 clk_src,
+ u8 tspll_freq, bool lock, bool new_cfg)
+{
+ dev_dbg(ice_hw_to_dev(hw),
+ "%s TSPLL configuration -- %s, src %s, freq %s, PLL %s\n",
+ new_cfg ? "New" : "Current", str_enabled_disabled(enable),
+ ice_tspll_clk_src_str((enum ice_clk_src)clk_src),
+ ice_tspll_clk_freq_str((enum ice_tspll_freq)tspll_freq),
+ lock ? "locked" : "unlocked");
+}
+
/**
* ice_tspll_cfg_e82x - Configure the Clock Generation Unit TSPLL
* @hw: Pointer to the HW struct
@@ -144,12 +164,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_tspll_clk_src_str(dw24.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
+ dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
+ false);
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
@@ -222,12 +239,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_tspll_clk_src_str(dw24.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw24.ts_pll_enable, clk_src, clk_freq, true,
+ true);
return 0;
}
@@ -316,12 +329,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw23.ts_pll_enable),
- ice_tspll_clk_src_str(dw23.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
+ dw9.time_ref_freq_sel,
+ ro_lock.plllock_true_lock_cri, false);
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
@@ -414,12 +424,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw23.ts_pll_enable),
- ice_tspll_clk_src_str(dw23.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw23.ts_pll_enable, clk_src, clk_freq, true,
+ true);
return 0;
}
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper Jacob Keller
@ 2025-05-22 14:23 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:23 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Add a helper function to print new/current TSPLL config. This helps avoid unnecessary casts from u8 to enums.
>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 54 +++++++++++++++++-------------
> 1 file changed, 30 insertions(+), 24 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (5 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:24 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming Jacob Keller
` (7 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Add ICE_READ_CGU_REG_OR_DIE() and ICE_WRITE_CGU_REG_OR_DIE() helpers to
avoid multiple error checks after calling read/write functions.
Suggested-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 15 +++
drivers/net/ethernet/intel/ice/ice_tspll.c | 160 ++++++----------------------
2 files changed, 47 insertions(+), 128 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index 86b34fb02d41b01640ee8b913ff2fc82fde85b68..65016843ddb0685d8e7c3bc11538b2b136530915 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -503,5 +503,20 @@ int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);
+#define ICE_READ_CGU_REG_OR_DIE(hw, addr, val) \
+ do { \
+ int __err = ice_read_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);
+#define ICE_WRITE_CGU_REG_OR_DIE(hw, addr, val) \
+ do { \
+ int __err = ice_write_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
+
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 08af4ced50eb877dce5944d87a90d0dcdb49ff2e..2cc728c2b67897940af75cb0bc3bfaf5fd8e6869 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -132,7 +132,6 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
- int err;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -152,17 +151,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
@@ -171,69 +162,40 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
dw24.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
- err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Configure the TSPLL feedback divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
dw19.ndivratio = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
/* Configure the TSPLL post divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
/* Configure the TSPLL pre divisor and clock source */
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
dw24.ref1588_ck_div = e82x_tspll_params[clk_freq].refclk_pre_div;
dw24.fbdiv_frac = e82x_tspll_params[clk_freq].frac_n_div;
dw24.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
/* Finally, enable the PLL */
dw24.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (!bwm_lf.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
@@ -257,12 +219,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
{
union tspll_cntr_bist_settings cntr_bist;
- int err;
-
- err = ice_read_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
/* Disable sticky lock detection so lock err reported is accurate */
cntr_bist.i_plllock_sel_0 = 0;
cntr_bist.i_plllock_sel_1 = 0;
@@ -294,7 +252,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r23 dw23;
union ice_cgu_r22 dw22;
union ice_cgu_r9 dw9;
- int err;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -313,21 +270,10 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R16, &dw16.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R16, &dw16.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
dw9.time_ref_freq_sel,
@@ -336,10 +282,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
dw23.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
}
/* Set the frequency */
@@ -353,72 +296,42 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
- err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Choose the referenced frequency */
dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
- err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R16, dw16.val);
/* Configure the TSPLL feedback divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
/* Configure the TSPLL post divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
/* These two are constant for E825C */
dw22.time1588clk_div = 5;
dw22.time1588clk_sel_div2 = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
/* Configure the TSPLL pre divisor and clock source */
- err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
dw23.ref1588_ck_div = 0;
dw23.time_ref_sel = clk_src;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
/* Clear the R24 register. */
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, 0);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0);
/* Finally, enable the PLL */
dw23.ts_pll_enable = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (!ro_lock.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
return -EBUSY;
@@ -442,14 +355,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
union tspll_bw_tdc_e825c bw_tdc;
- int err;
-
- err = ice_read_cgu_reg(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
bw_tdc.i_plllock_sel_1_0 = 0;
-
return ice_write_cgu_reg(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
}
@@ -465,12 +373,8 @@ static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
{
union ice_cgu_r9 r9;
- int err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9.val);
r9.one_pps_out_en = enable;
r9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
return ice_write_cgu_reg(hw, ICE_CGU_R9, r9.val);
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers Jacob Keller
@ 2025-05-22 14:24 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:24 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Add ICE_READ_CGU_REG_OR_DIE() and ICE_WRITE_CGU_REG_OR_DIE() helpers to avoid multiple error checks after calling read/write functions.
>
> Suggested-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.h | 15 +++ drivers/net/ethernet/intel/ice/ice_tspll.c | 160 ++++++----------------------
> 2 files changed, 47 insertions(+), 128 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (6 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:27 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status Jacob Keller
` (6 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
When programming the Clock Generation Unit for E285-C hardware, we need
to clear the time_sync_en bit of the DWORD 9 before we set the
frequency.
Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 2cc728c2b67897940af75cb0bc3bfaf5fd8e6869..8de1ad1da8346d4be4224b923de3baeffc954198 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -285,6 +285,11 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
}
+ if (dw9.time_sync_en) {
+ dw9.time_sync_en = 0;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
+ }
+
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
@@ -296,6 +301,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
+ dw9.time_sync_en = 1;
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Choose the referenced frequency */
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming Jacob Keller
@ 2025-05-22 14:27 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:27 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming
>
> When programming the Clock Generation Unit for E285-C hardware, we need to clear the time_sync_en bit of the DWORD 9 before we set the frequency.
>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (7 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:28 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs Jacob Keller
` (5 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
After programming the TSPLL, re-read the registers before reporting status.
This ensures the debug log message will show what was actually programmed,
rather than relying on a cached value.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 8de1ad1da8346d4be4224b923de3baeffc954198..74384725869399b4aa999d5b1fe33a5b19e0c2fd 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -201,8 +201,11 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- ice_tspll_log_cfg(hw, dw24.ts_pll_enable, clk_src, clk_freq, true,
- true);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
+
+ ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
+ dw9.time_ref_freq_sel, true, false);
return 0;
}
@@ -343,8 +346,11 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- ice_tspll_log_cfg(hw, dw23.ts_pll_enable, clk_src, clk_freq, true,
- true);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
+
+ ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
+ dw9.time_ref_freq_sel, true, true);
return 0;
}
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status Jacob Keller
@ 2025-05-22 14:28 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:28 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status
>
> After programming the TSPLL, re-read the registers before reporting status.
> This ensures the debug log message will show what was actually programmed, rather than relying on a cached value.
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (8 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 09/15] ice: read TSPLL registers again before reporting status Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:30 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers Jacob Keller
` (4 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Switch from unions with bitfield structs to definitions with bitfield
masks. This is necessary, because some registers have different
field definitions or even use a different register for the same fields
based on HW type.
Remove unused register fields.
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 212 ++++---------------------
drivers/net/ethernet/intel/ice/ice_tspll.c | 234 ++++++++++++++--------------
2 files changed, 153 insertions(+), 293 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index 65016843ddb0685d8e7c3bc11538b2b136530915..3f74570b99bf539b1cc58c22fa6f6880ad853793 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -39,194 +39,46 @@
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
-#define ICE_CGU_R9 0x24
-union ice_cgu_r9 {
- struct {
- u32 time_ref_freq_sel : 3;
- u32 clk_eref1_en : 1;
- u32 clk_eref0_en : 1;
- u32 time_ref_en : 1;
- u32 time_sync_en : 1;
- u32 one_pps_out_en : 1;
- u32 clk_ref_synce_en : 1;
- u32 clk_synce1_en : 1;
- u32 clk_synce0_en : 1;
- u32 net_clk_ref1_en : 1;
- u32 net_clk_ref0_en : 1;
- u32 clk_synce1_amp : 2;
- u32 misc6 : 1;
- u32 clk_synce0_amp : 2;
- u32 one_pps_out_amp : 2;
- u32 misc24 : 12;
- };
- u32 val;
-};
+#define ICE_CGU_R9 0x24
+#define ICE_CGU_R9_TIME_REF_FREQ_SEL GENMASK(2, 0)
+#define ICE_CGU_R9_CLK_EREF0_EN BIT(4)
+#define ICE_CGU_R9_TIME_REF_EN BIT(5)
+#define ICE_CGU_R9_TIME_SYNC_EN BIT(6)
+#define ICE_CGU_R9_ONE_PPS_OUT_EN BIT(7)
+#define ICE_CGU_R9_ONE_PPS_OUT_AMP GENMASK(19, 18)
-#define ICE_CGU_R16 0x40
-union ice_cgu_r16 {
- struct {
- u32 synce_remndr : 6;
- u32 synce_phlmt_en : 1;
- u32 misc13 : 17;
- u32 ck_refclkfreq : 8;
- };
- u32 val;
-};
+#define ICE_CGU_R16 0x40
+#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ GENMASK(31, 24)
-#define ICE_CGU_R19 0x4c
-union ice_cgu_r19_e82x {
- struct {
- u32 fbdiv_intgr : 8;
- u32 fdpll_ulck_thr : 5;
- u32 misc15 : 3;
- u32 ndivratio : 4;
- u32 tspll_iref_ndivratio : 3;
- u32 misc19 : 1;
- u32 japll_ndivratio : 4;
- u32 japll_iref_ndivratio : 3;
- u32 misc27 : 1;
- };
- u32 val;
-};
+#define ICE_CGU_R19 0x4C
+#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X GENMASK(7, 0)
+#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 GENMASK(9, 0)
+#define ICE_CGU_R19_TSPLL_NDIVRATIO GENMASK(19, 16)
-union ice_cgu_r19_e825 {
- struct {
- u32 tspll_fbdiv_intgr : 10;
- u32 fdpll_ulck_thr : 5;
- u32 misc15 : 1;
- u32 tspll_ndivratio : 4;
- u32 tspll_iref_ndivratio : 3;
- u32 misc19 : 1;
- u32 japll_ndivratio : 4;
- u32 japll_postdiv_pdivratio : 3;
- u32 misc27 : 1;
- };
- u32 val;
-};
+#define ICE_CGU_R22 0x58
+#define ICE_CGU_R22_TIME1588CLK_DIV GENMASK(23, 20)
+#define ICE_CGU_R22_TIME1588CLK_DIV2 BIT(30)
-#define ICE_CGU_R22 0x58
-union ice_cgu_r22 {
- struct {
- u32 fdpll_frac_div_out_nc : 2;
- u32 fdpll_lock_int_for : 1;
- u32 synce_hdov_int_for : 1;
- u32 synce_lock_int_for : 1;
- u32 fdpll_phlead_slip_nc : 1;
- u32 fdpll_acc1_ovfl_nc : 1;
- u32 fdpll_acc2_ovfl_nc : 1;
- u32 synce_status_nc : 6;
- u32 fdpll_acc1f_ovfl : 1;
- u32 misc18 : 1;
- u32 fdpllclk_div : 4;
- u32 time1588clk_div : 4;
- u32 synceclk_div : 4;
- u32 synceclk_sel_div2 : 1;
- u32 fdpllclk_sel_div2 : 1;
- u32 time1588clk_sel_div2 : 1;
- u32 misc3 : 1;
- };
- u32 val;
-};
+#define ICE_CGU_R23 0x5C
+#define ICE_CGU_R24 0x60
+#define ICE_CGU_R24_FBDIV_FRAC GENMASK(21, 0)
+#define ICE_CGU_R23_R24_TSPLL_ENABLE BIT(24)
+#define ICE_CGU_R23_R24_REF1588_CK_DIV GENMASK(30, 27)
+#define ICE_CGU_R23_R24_TIME_REF_SEL BIT(31)
-#define ICE_CGU_R23 0x5C
-union ice_cgu_r23 {
- struct {
- u32 cgupll_fbdiv_intgr : 10;
- u32 ux56pll_fbdiv_intgr : 10;
- u32 misc20 : 4;
- u32 ts_pll_enable : 1;
- u32 time_sync_tspll_align_sel : 1;
- u32 ext_synce_sel : 1;
- u32 ref1588_ck_div : 4;
- u32 time_ref_sel : 1;
+#define ICE_CGU_BW_TDC 0x31C
+#define ICE_CGU_BW_TDC_PLLLOCK_SEL GENMASK(30, 29)
- };
- u32 val;
-};
+#define ICE_CGU_RO_LOCK 0x3F0
+#define ICE_CGU_RO_LOCK_TRUE_LOCK BIT(12)
+#define ICE_CGU_RO_LOCK_UNLOCK BIT(13)
-#define ICE_CGU_R24 0x60
-union ice_cgu_r24 {
- struct {
- u32 fbdiv_frac : 22;
- u32 misc20 : 2;
- u32 ts_pll_enable : 1;
- u32 time_sync_tspll_align_sel : 1;
- u32 ext_synce_sel : 1;
- u32 ref1588_ck_div : 4;
- u32 time_ref_sel : 1;
- };
- u32 val;
-};
+#define ICE_CGU_CNTR_BIST 0x344
+#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0 BIT(15)
+#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1 BIT(16)
-#define TSPLL_CNTR_BIST_SETTINGS 0x344
-union tspll_cntr_bist_settings {
- struct {
- u32 i_irefgen_settling_time_cntr_7_0 : 8;
- u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
- u32 reserved195 : 5;
- u32 i_plllock_sel_0 : 1;
- u32 i_plllock_sel_1 : 1;
- u32 i_plllock_cnt_6_0 : 7;
- u32 i_plllock_cnt_10_7 : 4;
- u32 reserved200 : 4;
- };
- u32 val;
-};
-
-#define TSPLL_RO_BWM_LF 0x370
-union tspll_ro_bwm_lf {
- struct {
- u32 bw_freqov_high_cri_7_0 : 8;
- u32 bw_freqov_high_cri_9_8 : 2;
- u32 biascaldone_cri : 1;
- u32 plllock_gain_tran_cri : 1;
- u32 plllock_true_lock_cri : 1;
- u32 pllunlock_flag_cri : 1;
- u32 afcerr_cri : 1;
- u32 afcdone_cri : 1;
- u32 feedfwrdgain_cal_cri_7_0 : 8;
- u32 m2fbdivmod_cri_7_0 : 8;
- };
- u32 val;
-};
-
-#define TSPLL_RO_LOCK_E825C 0x3f0
-union tspll_ro_lock_e825c {
- struct {
- u32 bw_freqov_high_cri_7_0 : 8;
- u32 bw_freqov_high_cri_9_8 : 2;
- u32 reserved455 : 1;
- u32 plllock_gain_tran_cri : 1;
- u32 plllock_true_lock_cri : 1;
- u32 pllunlock_flag_cri : 1;
- u32 afcerr_cri : 1;
- u32 afcdone_cri : 1;
- u32 feedfwrdgain_cal_cri_7_0 : 8;
- u32 reserved462 : 8;
- };
- u32 val;
-};
-
-#define TSPLL_BW_TDC_E825C 0x31c
-union tspll_bw_tdc_e825c {
- struct {
- u32 i_tdc_offset_lock_1_0 : 2;
- u32 i_bbthresh1_2_0 : 3;
- u32 i_bbthresh2_2_0 : 3;
- u32 i_tdcsel_1_0 : 2;
- u32 i_tdcovccorr_en_h : 1;
- u32 i_divretimeren : 1;
- u32 i_bw_ampmeas_window : 1;
- u32 i_bw_lowerbound_2_0 : 3;
- u32 i_bw_upperbound_2_0 : 3;
- u32 i_bw_mode_1_0 : 2;
- u32 i_ft_mode_sel_2_0 : 3;
- u32 i_bwphase_4_0 : 5;
- u32 i_plllock_sel_1_0 : 2;
- u32 i_afc_divratio : 1;
- };
- u32 val;
-};
+#define ICE_CGU_RO_BWM_LF 0x370
+#define ICE_CGU_RO_BWM_LF_TRUE_LOCK BIT(12)
int ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 74384725869399b4aa999d5b1fe33a5b19e0c2fd..54f7b8a18a2f48b1866d2fe6e505d32b6717965c 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -127,11 +127,7 @@ static void ice_tspll_log_cfg(struct ice_hw *hw, bool enable, u8 clk_src,
static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
- union tspll_ro_bwm_lf bwm_lf;
- union ice_cgu_r19_e82x dw19;
- union ice_cgu_r22 dw22;
- union ice_cgu_r24 dw24;
- union ice_cgu_r9 dw9;
+ u32 val, r9, r24;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -151,61 +147,74 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &r24);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val);
- ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
- dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
+ ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24),
+ FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r24),
+ FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
+ !!FIELD_GET(ICE_CGU_RO_BWM_LF_TRUE_LOCK, val),
false);
/* Disable the PLL before changing the clock source or frequency */
- if (dw24.ts_pll_enable) {
- dw24.ts_pll_enable = 0;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
+ if (FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24)) {
+ r24 &= ~ICE_CGU_R23_R24_TSPLL_ENABLE;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
}
/* Set the frequency */
- dw9.time_ref_freq_sel = clk_freq;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
+ r9 &= ~ICE_CGU_R9_TIME_REF_FREQ_SEL;
+ r9 |= FIELD_PREP(ICE_CGU_R9_TIME_REF_FREQ_SEL, clk_freq);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, r9);
/* Configure the TSPLL feedback divisor */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
- dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
- dw19.ndivratio = 1;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &val);
+ val &= ~(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X | ICE_CGU_R19_TSPLL_NDIVRATIO);
+ val |= FIELD_PREP(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X,
+ e82x_tspll_params[clk_freq].feedback_div);
+ val |= FIELD_PREP(ICE_CGU_R19_TSPLL_NDIVRATIO, 1);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, val);
/* Configure the TSPLL post divisor */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
- dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
- dw22.time1588clk_sel_div2 = 0;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &val);
+ val &= ~(ICE_CGU_R22_TIME1588CLK_DIV |
+ ICE_CGU_R22_TIME1588CLK_DIV2);
+ val |= FIELD_PREP(ICE_CGU_R22_TIME1588CLK_DIV,
+ e82x_tspll_params[clk_freq].post_pll_div);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, val);
/* Configure the TSPLL pre divisor and clock source */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
- dw24.ref1588_ck_div = e82x_tspll_params[clk_freq].refclk_pre_div;
- dw24.fbdiv_frac = e82x_tspll_params[clk_freq].frac_n_div;
- dw24.time_ref_sel = clk_src;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &r24);
+ r24 &= ~(ICE_CGU_R23_R24_REF1588_CK_DIV | ICE_CGU_R24_FBDIV_FRAC |
+ ICE_CGU_R23_R24_TIME_REF_SEL);
+ r24 |= FIELD_PREP(ICE_CGU_R23_R24_REF1588_CK_DIV,
+ e82x_tspll_params[clk_freq].refclk_pre_div);
+ r24 |= FIELD_PREP(ICE_CGU_R24_FBDIV_FRAC,
+ e82x_tspll_params[clk_freq].frac_n_div);
+ r24 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
/* Finally, enable the PLL */
- dw24.ts_pll_enable = 1;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
+ r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (!bwm_lf.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val);
+ if (!(val & ICE_CGU_RO_BWM_LF_TRUE_LOCK)) {
+ dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
return -EBUSY;
}
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &r24);
- ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
- dw9.time_ref_freq_sel, true, false);
+ ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24),
+ FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r24),
+ FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
+ true, true);
return 0;
}
@@ -221,14 +230,12 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
*/
static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
{
- union tspll_cntr_bist_settings cntr_bist;
+ u32 val;
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
- /* Disable sticky lock detection so lock err reported is accurate */
- cntr_bist.i_plllock_sel_0 = 0;
- cntr_bist.i_plllock_sel_1 = 0;
-
- return ice_write_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, cntr_bist.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_CNTR_BIST, &val);
+ val &= ~(ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0 |
+ ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1);
+ return ice_write_cgu_reg(hw, ICE_CGU_CNTR_BIST, val);
}
/**
@@ -249,12 +256,7 @@ static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
- union tspll_ro_lock_e825c ro_lock;
- union ice_cgu_r19_e825 dw19;
- union ice_cgu_r16 dw16;
- union ice_cgu_r23 dw23;
- union ice_cgu_r22 dw22;
- union ice_cgu_r9 dw9;
+ u32 val, r9, r23;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -273,84 +275,91 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R16, &dw16.val);
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &r23);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val);
- ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
- dw9.time_ref_freq_sel,
- ro_lock.plllock_true_lock_cri, false);
+ ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
+ FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
+ FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
+ !!FIELD_GET(ICE_CGU_RO_LOCK_TRUE_LOCK, val),
+ false);
/* Disable the PLL before changing the clock source or frequency */
- if (dw23.ts_pll_enable) {
- dw23.ts_pll_enable = 0;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
+ if (FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23)) {
+ r23 &= ~ICE_CGU_R23_R24_TSPLL_ENABLE;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23);
}
- if (dw9.time_sync_en) {
- dw9.time_sync_en = 0;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
+ if (FIELD_GET(ICE_CGU_R9_TIME_SYNC_EN, r9)) {
+ r9 &= ~ICE_CGU_R9_TIME_SYNC_EN;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, r9);
}
- /* Set the frequency */
- dw9.time_ref_freq_sel = clk_freq;
-
- /* Enable the correct receiver */
- if (clk_src == ICE_CLK_SRC_TCXO) {
- dw9.time_ref_en = 0;
- dw9.clk_eref0_en = 1;
- } else {
- dw9.time_ref_en = 1;
- dw9.clk_eref0_en = 0;
- }
- dw9.time_sync_en = 1;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
+ /* Set the frequency and enable the correct receiver */
+ r9 &= ~(ICE_CGU_R9_TIME_REF_FREQ_SEL | ICE_CGU_R9_CLK_EREF0_EN |
+ ICE_CGU_R9_TIME_REF_EN);
+ r9 |= FIELD_PREP(ICE_CGU_R9_TIME_REF_FREQ_SEL, clk_freq);
+ if (clk_src == ICE_CLK_SRC_TCXO)
+ r9 |= ICE_CGU_R9_CLK_EREF0_EN;
+ else
+ r9 |= ICE_CGU_R9_TIME_REF_EN;
+ r9 |= ICE_CGU_R9_TIME_SYNC_EN;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, r9);
/* Choose the referenced frequency */
- dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R16, dw16.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R16, &val);
+ val &= ~ICE_CGU_R16_TSPLL_CK_REFCLKFREQ;
+ val |= FIELD_PREP(ICE_CGU_R16_TSPLL_CK_REFCLKFREQ,
+ ICE_TSPLL_CK_REFCLKFREQ_E825);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R16, val);
/* Configure the TSPLL feedback divisor */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
- dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
- dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &val);
+ val &= ~(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 |
+ ICE_CGU_R19_TSPLL_NDIVRATIO);
+ val |= FIELD_PREP(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825,
+ ICE_TSPLL_FBDIV_INTGR_E825);
+ val |= FIELD_PREP(ICE_CGU_R19_TSPLL_NDIVRATIO,
+ ICE_TSPLL_NDIVRATIO_E825);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, val);
- /* Configure the TSPLL post divisor */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
- /* These two are constant for E825C */
- dw22.time1588clk_div = 5;
- dw22.time1588clk_sel_div2 = 0;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, dw22.val);
+ /* Configure the TSPLL post divisor, these two are constant */
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &val);
+ val &= ~(ICE_CGU_R22_TIME1588CLK_DIV |
+ ICE_CGU_R22_TIME1588CLK_DIV2);
+ val |= FIELD_PREP(ICE_CGU_R22_TIME1588CLK_DIV, 5);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R22, val);
- /* Configure the TSPLL pre divisor and clock source */
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
- dw23.ref1588_ck_div = 0;
- dw23.time_ref_sel = clk_src;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
+ /* Configure the TSPLL pre divisor (constant) and clock source */
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &r23);
+ r23 &= ~(ICE_CGU_R23_R24_REF1588_CK_DIV | ICE_CGU_R23_R24_TIME_REF_SEL);
+ r23 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23);
/* Clear the R24 register. */
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0);
/* Finally, enable the PLL */
- dw23.ts_pll_enable = 1;
- ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, dw23.val);
+ r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23);
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (!ro_lock.plllock_true_lock_cri) {
- dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val);
+ if (!(val & ICE_CGU_RO_LOCK_TRUE_LOCK)) {
+ dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
return -EBUSY;
}
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &dw23.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &r23);
- ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
- dw9.time_ref_freq_sel, true, true);
+ ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
+ FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
+ FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
+ true, true);
return 0;
}
@@ -366,15 +375,13 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
*/
static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
- union tspll_bw_tdc_e825c bw_tdc;
+ u32 val;
- ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
- bw_tdc.i_plllock_sel_1_0 = 0;
- return ice_write_cgu_reg(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_BW_TDC, &val);
+ val &= ~ICE_CGU_BW_TDC_PLLLOCK_SEL;
+ return ice_write_cgu_reg(hw, ICE_CGU_BW_TDC, val);
}
-#define ICE_ONE_PPS_OUT_AMP_MAX 3
-
/**
* ice_tspll_cfg_pps_out_e825c - Enable/disable 1PPS output and set amplitude
* @hw: pointer to the HW struct
@@ -384,12 +391,13 @@ static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
*/
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
{
- union ice_cgu_r9 r9;
+ u32 val;
- ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9.val);
- r9.one_pps_out_en = enable;
- r9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
- return ice_write_cgu_reg(hw, ICE_CGU_R9, r9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &val);
+ val &= ~(ICE_CGU_R9_ONE_PPS_OUT_EN | ICE_CGU_R9_ONE_PPS_OUT_AMP);
+ val |= FIELD_PREP(ICE_CGU_R9_ONE_PPS_OUT_EN, enable) |
+ ICE_CGU_R9_ONE_PPS_OUT_AMP;
+ return ice_write_cgu_reg(hw, ICE_CGU_R9, val);
}
/**
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs Jacob Keller
@ 2025-05-22 14:30 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:30 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Switch from unions with bitfield structs to definitions with bitfield masks. This is necessary, because some registers have different field definitions or even use a different register for the same fields based on HW type.
>
> Remove unused register fields.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.h | 212 ++++--------------------- drivers/net/ethernet/intel/ice/ice_tspll.c | 234 ++++++++++++++--------------
> 2 files changed, 153 insertions(+), 293 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (9 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:32 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL Jacob Keller
` (3 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Add helpers for checking TSPLL params, disabling sticky bits,
configuring TSPLL and getting default clock frequency to simplify
the code flows.
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 156 ++++++++++++++++++++---------
1 file changed, 108 insertions(+), 48 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 54f7b8a18a2f48b1866d2fe6e505d32b6717965c..66ad5ee63f3084d1d54c2445f56d7f61d6be344b 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -71,6 +71,58 @@ static const char *ice_tspll_clk_freq_str(enum ice_tspll_freq clk_freq)
}
}
+/**
+ * ice_tspll_default_freq - Return default frequency for a MAC type
+ * @mac_type: MAC type
+ *
+ * Return: default TSPLL frequency for a correct MAC type, -ERANGE otherwise.
+ */
+static enum ice_tspll_freq ice_tspll_default_freq(enum ice_mac_type mac_type)
+{
+ switch (mac_type) {
+ case ICE_MAC_GENERIC:
+ return ICE_TSPLL_FREQ_25_000;
+ case ICE_MAC_GENERIC_3K_E825:
+ return ICE_TSPLL_FREQ_156_250;
+ default:
+ return -ERANGE;
+ }
+}
+
+/**
+ * ice_tspll_check_params - Check if TSPLL params are correct
+ * @hw: Pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF or TCXO)
+ *
+ * Return: true if TSPLL params are correct, false otherwise.
+ */
+static bool ice_tspll_check_params(struct ice_hw *hw,
+ enum ice_tspll_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid TSPLL frequency %u\n",
+ clk_freq);
+ return false;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
+ clk_src);
+ return false;
+ }
+
+ if ((hw->mac_type == ICE_MAC_GENERIC_3K_E825 ||
+ clk_src == ICE_CLK_SRC_TCXO) &&
+ clk_freq != ice_tspll_default_freq(hw->mac_type)) {
+ dev_warn(ice_hw_to_dev(hw), "Unsupported frequency for this clock source\n");
+ return false;
+ }
+
+ return true;
+}
+
/**
* ice_tspll_clk_src_str - Convert time_ref_src to string
* @clk_src: Clock source
@@ -129,24 +181,6 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
{
u32 val, r9, r24;
- if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
- dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
- clk_freq);
- return -EINVAL;
- }
-
- if (clk_src >= NUM_ICE_CLK_SRC) {
- dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
- clk_src);
- return -EINVAL;
- }
-
- if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_25_000) {
- dev_warn(ice_hw_to_dev(hw),
- "TCXO only supports 25 MHz frequency\n");
- return -EINVAL;
- }
-
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &r24);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val);
@@ -258,23 +292,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
{
u32 val, r9, r23;
- if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
- dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
- clk_freq);
- return -EINVAL;
- }
-
- if (clk_src >= NUM_ICE_CLK_SRC) {
- dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
- clk_src);
- return -EINVAL;
- }
-
- if (clk_freq != ICE_TSPLL_FREQ_156_250) {
- dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
- return -EINVAL;
- }
-
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &r9);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R23, &r23);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val);
@@ -400,6 +417,52 @@ int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
return ice_write_cgu_reg(hw, ICE_CGU_R9, val);
}
+/**
+ * ice_tspll_cfg - Configure the Clock Generation Unit TSPLL
+ * @hw: Pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCXO)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the TSPLL which drives the PTP hardware clock.
+ *
+ * Return: 0 on success, -ERANGE on unsupported MAC type, other negative error
+ * codes when failed to configure CGU.
+ */
+static int ice_tspll_cfg(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ switch (hw->mac_type) {
+ case ICE_MAC_GENERIC:
+ return ice_tspll_cfg_e82x(hw, clk_freq, clk_src);
+ case ICE_MAC_GENERIC_3K_E825:
+ return ice_tspll_cfg_e825c(hw, clk_freq, clk_src);
+ default:
+ return -ERANGE;
+ }
+}
+
+/**
+ * ice_tspll_dis_sticky_bits - disable TSPLL sticky bits
+ * @hw: Pointer to the HW struct
+ *
+ * Configure the Clock Generation Unit TSPLL sticky bits so they don't latch on
+ * losing TSPLL lock, but always show current state.
+ *
+ * Return: 0 on success, -ERANGE on unsupported MAC type.
+ */
+static int ice_tspll_dis_sticky_bits(struct ice_hw *hw)
+{
+ switch (hw->mac_type) {
+ case ICE_MAC_GENERIC:
+ return ice_tspll_dis_sticky_bits_e82x(hw);
+ case ICE_MAC_GENERIC_3K_E825:
+ return ice_tspll_dis_sticky_bits_e825c(hw);
+ default:
+ return -ERANGE;
+ }
+}
+
/**
* ice_tspll_init - Initialize TSPLL with settings from firmware
* @hw: Pointer to the HW structure
@@ -411,25 +474,22 @@ int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
int ice_tspll_init(struct ice_hw *hw)
{
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
+ enum ice_tspll_freq tspll_freq;
+ enum ice_clk_src clk_src;
int err;
- /* Disable sticky lock detection so lock err reported is accurate. */
- if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_tspll_dis_sticky_bits_e825c(hw);
- else
- err = ice_tspll_dis_sticky_bits_e82x(hw);
+ tspll_freq = (enum ice_tspll_freq)ts_info->time_ref;
+ clk_src = (enum ice_clk_src)ts_info->clk_src;
+ if (!ice_tspll_check_params(hw, tspll_freq, clk_src))
+ return -EINVAL;
+
+ /* Disable sticky lock detection so lock status reported is accurate */
+ err = ice_tspll_dis_sticky_bits(hw);
if (err)
return err;
/* Configure the TSPLL using the parameters from the function
* capabilities.
*/
- if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
- err = ice_tspll_cfg_e825c(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
- else
- err = ice_tspll_cfg_e82x(hw, ts_info->time_ref,
- (enum ice_clk_src)ts_info->clk_src);
-
- return err;
+ return ice_tspll_cfg(hw, tspll_freq, clk_src);
}
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers Jacob Keller
@ 2025-05-22 14:32 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:32 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Add helpers for checking TSPLL params, disabling sticky bits, configuring TSPLL and getting default clock frequency to simplify the code flows.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 156 ++++++++++++++++++++---------
> 1 file changed, 108 insertions(+), 48 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (10 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 11/15] ice: add multiple TSPLL helpers Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:34 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail Jacob Keller
` (2 subsequent siblings)
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
To ensure proper operation, wait for 10 to 20 microseconds before
enabling TSPLL.
Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms.
Those values are empirical and tested on multiple HW configurations.
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 66ad5ee63f3084d1d54c2445f56d7f61d6be344b..a392b39920aeb7c23008a03baf3df9cd14dcbb7e 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -229,12 +229,15 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
r24 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
+ /* Wait to ensure everything is stable */
+ usleep_range(10, 20);
+
/* Finally, enable the PLL */
r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
+ /* Wait at least 1 ms to verify if the PLL locks */
+ usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val);
if (!(val & ICE_CGU_RO_BWM_LF_TRUE_LOCK)) {
@@ -357,12 +360,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
/* Clear the R24 register. */
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0);
+ /* Wait to ensure everything is stable */
+ usleep_range(10, 20);
+
/* Finally, enable the PLL */
r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23);
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
+ /* Wait at least 1 ms to verify if the PLL locks */
+ usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val);
if (!(val & ICE_CGU_RO_LOCK_TRUE_LOCK)) {
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL Jacob Keller
@ 2025-05-22 14:34 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:34 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> To ensure proper operation, wait for 10 to 20 microseconds before enabling TSPLL.
>
> Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms.
>
> Those values are empirical and tested on multiple HW configurations.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (11 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 12/15] ice: wait before enabling TSPLL Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:36 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c Jacob Keller
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C Jacob Keller
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
TSPLL can fail when trying to lock to TIME_REF as a clock source, e.g.
when the external clock source is not stable or connected to the board.
To continue operation after failure, try to lock again to internal TCXO
and inform user about this.
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index a392b39920aeb7c23008a03baf3df9cd14dcbb7e..7b61e1afe8b43a24c77edf0a0590562fbfa0ce3e 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -497,5 +497,17 @@ int ice_tspll_init(struct ice_hw *hw)
/* Configure the TSPLL using the parameters from the function
* capabilities.
*/
- return ice_tspll_cfg(hw, tspll_freq, clk_src);
+ err = ice_tspll_cfg(hw, tspll_freq, clk_src);
+ if (err) {
+ dev_warn(ice_hw_to_dev(hw), "Failed to lock TSPLL to predefined frequency. Retrying with fallback frequency.\n");
+
+ /* Try to lock to internal TCXO as a fallback. */
+ tspll_freq = ice_tspll_default_freq(hw->mac_type);
+ clk_src = ICE_CLK_SRC_TCXO;
+ err = ice_tspll_cfg(hw, tspll_freq, clk_src);
+ if (err)
+ dev_warn(ice_hw_to_dev(hw), "Failed to lock TSPLL to fallback frequency.\n");
+ }
+
+ return err;
}
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail Jacob Keller
@ 2025-05-22 14:36 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:36 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> TSPLL can fail when trying to lock to TIME_REF as a clock source, e.g.
when the external clock source is not stable or connected to the board.
> To continue operation after failure, try to lock again to internal TCXO and inform user about this.
>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_tspll.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (12 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:38 ` Rinitha, SX
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C Jacob Keller
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
From: Karol Kolacinski <karol.kolacinski@intel.com>
Initialize TSPLL after initializing PHC in ice_ptp.c instead of calling
for each product in PHC init in ice_ptp_hw.c.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_ptp.c | 11 +++++++++++
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 22 +---------------------
drivers/net/ethernet/intel/ice/ice_tspll.c | 5 +++++
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 083f50f827441792d3b7a838c3359e05d2bbdf7c..3278b96d8f01cdf783db495db167e44c13e8c8da 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -2891,6 +2891,10 @@ static int ice_ptp_rebuild_owner(struct ice_pf *pf)
if (err)
return err;
+ err = ice_tspll_init(hw);
+ if (err)
+ return err;
+
/* Acquire the global hardware lock */
if (!ice_ptp_lock(hw)) {
err = -EBUSY;
@@ -3058,6 +3062,13 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
return err;
}
+ err = ice_tspll_init(hw);
+ if (err) {
+ dev_err(ice_pf_to_dev(pf), "Failed to initialize CGU, status %d\n",
+ err);
+ return err;
+ }
+
/* Acquire the global hardware lock */
if (!ice_ptp_lock(hw)) {
err = -EBUSY;
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 6da82025934cb709d06f12cc26f9b494c6f4d772..523f95271f353e72b72ac5ea0123869f2d387e98 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2115,20 +2115,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
return 0;
}
-/**
- * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
- * @hw: pointer to HW struct
- *
- * Perform E825-specific PTP hardware clock initialization steps.
- *
- * Return: 0 on success, negative error code otherwise.
- */
-static int ice_ptp_init_phc_e825(struct ice_hw *hw)
-{
- /* Initialize the Clock Generation Unit */
- return ice_tspll_init(hw);
-}
-
/**
* ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
* @hw: pointer to the HW struct
@@ -2788,7 +2774,6 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
*/
static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
{
- int err;
u32 val;
/* Enable reading switch and PHY registers over the sideband queue */
@@ -2798,11 +2783,6 @@ static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
wr32(hw, PF_SB_REM_DEV_CTL, val);
- /* Initialize the Clock Generation Unit */
- err = ice_tspll_init(hw);
- if (err)
- return err;
-
/* Set window length for all the ports */
return ice_ptp_set_vernier_wl(hw);
}
@@ -5584,7 +5564,7 @@ int ice_ptp_init_phc(struct ice_hw *hw)
case ICE_MAC_GENERIC:
return ice_ptp_init_phc_e82x(hw);
case ICE_MAC_GENERIC_3K_E825:
- return ice_ptp_init_phc_e825(hw);
+ return 0;
default:
return -EOPNOTSUPP;
}
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 7b61e1afe8b43a24c77edf0a0590562fbfa0ce3e..8f125ea5a80f5d145a412eee55a148b3ae3f830d 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -484,6 +484,11 @@ int ice_tspll_init(struct ice_hw *hw)
enum ice_clk_src clk_src;
int err;
+ /* Only E822, E823 and E825 products support TSPLL */
+ if (hw->mac_type != ICE_MAC_GENERIC &&
+ hw->mac_type != ICE_MAC_GENERIC_3K_E825)
+ return 0;
+
tspll_freq = (enum ice_tspll_freq)ts_info->time_ref;
clk_src = (enum ice_clk_src)ts_info->clk_src;
if (!ice_tspll_check_params(hw, tspll_freq, clk_src))
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c Jacob Keller
@ 2025-05-22 14:38 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:38 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c
>
> From: Karol Kolacinski <karol.kolacinski@intel.com>
>
> Initialize TSPLL after initializing PHC in ice_ptp.c instead of calling for each product in PHC init in ice_ptp_hw.c.
>
> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
> Reviewed-by: Milena Olech <milena.olech@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp.c | 11 +++++++++++
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 22 +--------------------- drivers/net/ethernet/intel/ice/ice_tspll.c | 5 +++++
> 3 files changed, 17 insertions(+), 21 deletions(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C
2025-05-01 22:54 [Intel-wired-lan] [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
` (13 preceding siblings ...)
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c Jacob Keller
@ 2025-05-01 22:54 ` Jacob Keller
2025-05-22 14:40 ` Rinitha, SX
14 siblings, 1 reply; 31+ messages in thread
From: Jacob Keller @ 2025-05-01 22:54 UTC (permalink / raw)
To: Intel Wired LAN, Anthony Nguyen, netdev
Cc: Jacob Keller, Michal Kubiak, Aleksandr Loktionov,
Karol Kolacinski, Przemek Kitszel, Milena Olech, Paul Menzel
The driver currently defaults to the internal oscillator as the clock
source for E825-C hardware. While this clock source is labeled TCXO,
indicating a temperature compensated oscillator, this is only true for some
board designs. Many board designs have a less capable oscillator. The
E825-C hardware may also have its clock source set to the TIME_REF pin.
This pin is connected to the DPLL and is often a more stable clock source.
The choice of the internal oscillator is not suitable for all systems,
especially those which want to enable SyncE support.
There is currently no interface available for users to configure the clock
source. Other variants of the E82x board have the clock source configured
in the NVM, but E825-C lacks this capability, so different board designs
cannot select a different default clock via firmware.
In most setups, the TIME_REF is a suitable default clock source.
Additionally, we now fall back to the internal oscillator automatically if
the TIME_REF clock source cannot be locked.
Change the default clock source for E825-C to TIME_REF. Note that the
driver logs a dev_dbg message upon configuring the TSPLL which includes the
clock source and frequency. This can be enabled to confirm which clock
source is in use.
Longterm a proper interface to dynamically introspect and change the clock
source will be designed (perhaps some extension of the DPLL subsystem?)
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
---
drivers/net/ethernet/intel/ice/ice_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 7d731d1be862311358943c6922354504ba4721ba..742ffbfba73ca3279cec311ae359ebc6a4e6a584 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2344,7 +2344,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
} else {
info->clk_freq = ICE_TSPLL_FREQ_156_250;
- info->clk_src = ICE_CLK_SRC_TCXO;
+ info->clk_src = ICE_CLK_SRC_TIME_REF;
}
if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {
--
2.48.1.397.gec9d649cc640
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C
2025-05-01 22:54 ` [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C Jacob Keller
@ 2025-05-22 14:40 ` Rinitha, SX
0 siblings, 0 replies; 31+ messages in thread
From: Rinitha, SX @ 2025-05-22 14:40 UTC (permalink / raw)
To: Keller, Jacob E, Intel Wired LAN, Nguyen, Anthony L, netdev
Cc: Keller, Jacob E, Kubiak, Michal, Loktionov, Aleksandr,
Kolacinski, Karol, Kitszel, Przemyslaw, Olech, Milena,
Paul Menzel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller
> Sent: 02 May 2025 04:24
> To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; netdev <netdev@vger.kernel.org>
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Kubiak, Michal <michal.kubiak@intel.com>; Loktionov, Aleksandr <aleksandr.loktionov@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; Olech, Milena <milena.olech@intel.com>; Paul Menzel <pmenzel@molgen.mpg.de>
> Subject: [Intel-wired-lan] [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C
>
> The driver currently defaults to the internal oscillator as the clock source for E825-C hardware. While this clock source is labeled TCXO, indicating a temperature compensated oscillator, this is only true for some board designs. Many board designs have a less capable oscillator. The E825-C hardware may also have its clock source set to the TIME_REF pin.
> This pin is connected to the DPLL and is often a more stable clock source.
> The choice of the internal oscillator is not suitable for all systems, especially those which want to enable SyncE support.
>
> There is currently no interface available for users to configure the clock source. Other variants of the E82x board have the clock source configured in the NVM, but E825-C lacks this capability, so different board designs cannot select a different default clock via firmware.
>
> In most setups, the TIME_REF is a suitable default clock source.
> Additionally, we now fall back to the internal oscillator automatically if the TIME_REF clock source cannot be locked.
>
> Change the default clock source for E825-C to TIME_REF. Note that the driver logs a dev_dbg message upon configuring the TSPLL which includes the clock source and frequency. This can be enabled to confirm which clock source is in use.
>
> Longterm a proper interface to dynamically introspect and change the clock source will be designed (perhaps some extension of the DPLL subsystem?)
>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
^ permalink raw reply [flat|nested] 31+ messages in thread