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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Aleksandr Loktionov , Chwee-Lin Choong Date: Wed, 14 May 2025 00:29:40 -0400 Message-Id: <20250514042945.2685273-4-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514042945.2685273-1-faizal.abdul.rahim@linux.intel.com> References: <20250514042945.2685273-1-faizal.abdul.rahim@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747197074; x=1778733074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k89ugzuHOnkB/aDBW+4LJjImUgTAiWJPrYGGiSD3Gng=; b=mNT9+I0L1OtfSw2di6X8L23mCBIIrw9ga0jukYpvY6xx83nyBm8Eq27X R4qe9PTuxTJ9JhU+gp8XQ9GmFq/4frZuY4AausZfvWYr16B64ZI149bS2 178iKPd0h/Jc9IXOpV3KV+OIZnnsiNhmfIZO0m8fyYEGfkaQpeULUBGf6 ZdVEbDhwnccnInXeifA3Xwgfyam4HUguJzIrceS2l8yP5fXK6fNRnDA6E fbj9egnTr1RDOS8oZFTSQ5A7x/DTQDhrCYH5PCWc//6mfy+uqhQtLk+kY BjL5md2HVPGTGb8TQzt7Ks29j5lRykY7GZwJ2o8RvG0CW5TFT1glODa0S w==; X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dmarc=none (p=none dis=none) header.from=linux.intel.com X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=mNT9+I0L Subject: [Intel-wired-lan] [PATCH iwl-next v2 3/8] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros. This prepares the code for adding a new TXDCTL priority field in an upcoming patch. Verified that the macro values remain unchanged before and after refactoring. Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 15 ++++++++++----- drivers/net/ethernet/intel/igc/igc_main.c | 6 ++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index db1e2db1619e..daab06fc3f80 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) /* Receive Software Flush */ #define IGC_RXDCTL_SWFLUSH 0x04000000 -#define IGC_TXDCTL_PTHRESH 8 -#define IGC_TXDCTL_HTHRESH 1 -#define IGC_TXDCTL_WTHRESH 16 +#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) +#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) +#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) +#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) +#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) +#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) +#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) +#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) /* Ena specific Tx Queue */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1) /* Transmit Software Flush */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 +#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 4f1a8bc006c6..f3a312c9413b 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); - txdctl |= IGC_TXDCTL_PTHRESH; - txdctl |= IGC_TXDCTL_HTHRESH << 8; - txdctl |= IGC_TXDCTL_WTHRESH << 16; + txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | + IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE; - txdctl |= IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); } -- 2.34.1