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charset=us-ascii Content-Disposition: inline In-Reply-To: <2de556f0-d7db-47f1-a59e-197f92f93d46@lunn.ch> X-Mailman-Approved-At: Wed, 17 Dec 2025 16:26:46 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765932589; bh=DNExHzFtlzkFnn3/GNMoj9gWvQBHtxOQZpew5LKKPUU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SMwTSgadUHirIxyUBx2QnuZKJJ5FL5lg7rrvoDS6JUpWfwRhO5E94tsjMZPV79W6l QIRhp1Cfw20qrRxdORrEJQmh9MKnyAAeoliIFDzJ+Tik/OguMSdckpu9mtS13TUsoS kPtAS4XghFPE+c9YZGkq9TLuDeLCyibKkCdYIngpeAIztsxiEVORzspMqQK+xV66e5 KBfLrP1pB+0hVYtfgoT9oJUHy2pKUkgLNwAevg8lzAUbb4eeqKirhvM8SU8kcYcBU6 ig+05Kia3Evtel6azROtQiaPP9njbQOoZVOG6tTX6kQbSiGW5VVzQlie4CLxhr6Qg2 kUWJOBj9DuwBw== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=kernel.org X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=SMwTSgad Subject: Re: [Intel-wired-lan] [PATCH RFC net-next 01/13] dt-bindings: net: ethernet-controller: Add DPLL pin properties X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dumazet , Tony Nguyen , Ivan Vecera , Leon Romanovsky , Alexander Lobakin , linux-rdma@vger.kernel.org, Przemek Kitszel , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, Jakub Kicinski , Paolo Abeni , devicetree@vger.kernel.org, Conor Dooley , Jiri Pirko , Richard Cochran , Prathosh Satish , Willem de Bruijn , Vadim Fedorenko , netdev@vger.kernel.org, Mark Bloch , linux-kernel@vger.kernel.org, Tariq Toukan , Andrew Lunn , Stefan Wahren , Simon Horman , Jonathan Lemon , Krzysztof Kozlowski , Saeed Mahameed , "David S. Miller" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On Thu, Dec 11, 2025 at 08:56:52PM +0100, Andrew Lunn wrote: > On Thu, Dec 11, 2025 at 08:47:44PM +0100, Ivan Vecera wrote: > > Ethernet controllers may be connected to DPLL (Digital Phase Locked Loop) > > pins for frequency synchronization purposes, such as in Synchronous > > Ethernet (SyncE) configurations. > > > > Add 'dpll-pins' and 'dpll-pin-names' properties to the generic > > ethernet-controller schema. This allows describing the physical > > connections between the Ethernet controller and the DPLL subsystem pins > > in the Device Tree, enabling drivers to request and manage these > > resources. > > Please include a .dts patch in the series which actually makes use of > these new properties. Actually, first you need a device (i.e. a specific ethernet controller bindings) using this and defining the number of dpll-pins entries and the names. Rob