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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1768589197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1Vq0sGyRYXFQB0FSoR5ne1F5tGDgvK5fncUfpA16P7M=; b=L6Fx/InRpk/Tpj6b4CIZDxlKTi3B/4KDIpD6JADZge/iBMdsF/DX4dfOKRRZGuhbBZLu2a uGjlL2qy7e9gMkhT79UhkCmWlf2c4Cic+7ZTFNJfSmel8cp8e9NdW0Sj3v/+yJ2/kA1I8e C76tHFbfILgaG2w/7MyUQ0fcW+HZCAU= X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=L6Fx/InR Subject: [Intel-wired-lan] [PATCH net-next v2 01/12] dt-bindings: dpll: support acting as pin provider X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dumazet , Tony Nguyen , Rob Herring , Leon Romanovsky , Alexander Lobakin , linux-rdma@vger.kernel.org, Przemek Kitszel , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, Jakub Kicinski , Paolo Abeni , devicetree@vger.kernel.org, Conor Dooley , Jiri Pirko , Richard Cochran , Saravana Kannan , Prathosh Satish , Vadim Fedorenko , Mark Bloch , linux-kernel@vger.kernel.org, Tariq Toukan , Andrew Lunn , Jonathan Lemon , Krzysztof Kozlowski , Saeed Mahameed , "David S. Miller" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Enable DPLL devices to act as pin providers for consumers (such as Ethernet controllers or PHYs). Add the '#dpll-pin-cells' property to the generic dpll-device.yaml schema and mark it as required. This allows DPLL nodes to define pin specifiers for their connected consumers. Introduce a new header '' to define pin direction macros (`DPLL_PIN_INPUT` and `DPLL_PIN_OUTPUT`). These macros are intended to be used in the DT pin specifiers (inside 'dpll-pins' properties of consumers) to describe the direction of the signal. Update the 'microchip,zl30731.yaml' examples to include the new '#dpll-pin-cells' property. The core schema definitions for these properties are being added to dt-schema in PR #183. Link: https://github.com/devicetree-org/dt-schema/pull/183 Signed-off-by: Ivan Vecera --- v2: * removed dpll-pin-consumer.yaml schema per request * added '#dpll-pin-cells' property into dpll-device.yaml and microchip,zl30731.yaml --- .../devicetree/bindings/dpll/dpll-device.yaml | 10 ++++++++++ .../devicetree/bindings/dpll/microchip,zl30731.yaml | 4 ++++ MAINTAINERS | 1 + include/dt-bindings/dpll/dpll.h | 13 +++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/dpll/dpll.h diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Documentation/devicetree/bindings/dpll/dpll-device.yaml index fb8d7a9a3693f..5022cbd77f308 100644 --- a/Documentation/devicetree/bindings/dpll/dpll-device.yaml +++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml @@ -27,6 +27,13 @@ properties: "#size-cells": const: 0 + "#dpll-pin-cells": + const: 2 + description: | + - Specified pin index + - Specified pin direction. The macros are defined in + dt-bindings/dpll/dpll.h + dpll-types: description: List of DPLL channel types, one per DPLL instance. $ref: /schemas/types.yaml#/definitions/non-unique-string-array @@ -73,4 +80,7 @@ properties: - "#address-cells" - "#size-cells" +required: + - "#dpll-pin-cells" + additionalProperties: true diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml index 17747f754b845..6693151af6ccb 100644 --- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml +++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml @@ -44,6 +44,8 @@ examples: #size-cells = <0>; dpll@70 { + #dpll-pin-cells = <2>; + compatible = "microchip,zl30732"; reg = <0x70>; dpll-types = "pps", "eec"; @@ -80,6 +82,8 @@ examples: #size-cells = <0>; dpll@70 { + #dpll-pin-cells = <2>; + compatible = "microchip,zl30731"; reg = <0x70>; spi-max-frequency = <12500000>; diff --git a/MAINTAINERS b/MAINTAINERS index afc71089ba09f..d359d42f64223 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7655,6 +7655,7 @@ F: Documentation/devicetree/bindings/dpll/dpll-device.yaml F: Documentation/devicetree/bindings/dpll/dpll-pin.yaml F: Documentation/driver-api/dpll.rst F: drivers/dpll/ +F: include/dt-bindings/dpll/dpll.h F: include/linux/dpll.h F: include/uapi/linux/dpll.h diff --git a/include/dt-bindings/dpll/dpll.h b/include/dt-bindings/dpll/dpll.h new file mode 100644 index 0000000000000..5fc9815800fc0 --- /dev/null +++ b/include/dt-bindings/dpll/dpll.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * This header provides constants for DPLL bindings. + */ + +#ifndef _DT_BINDINGS_DPLL_DPLL_H +#define _DT_BINDINGS_DPLL_DPLL_H + +/* DPLL pin direction */ +#define DPLL_PIN_INPUT 0 +#define DPLL_PIN_OUTPUT 1 + +#endif -- 2.52.0