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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768954737; bh=0HGVVeTAHwzSzLFOpdIyNRyTdHYdyUOMXgvp4PSevFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JOs9JzpEXQU9eIhdVdrnpwlJd0Lx0KFCd8ly+f79aar8QjwM2HCTDp7T2RDQX6+ob Ef9GBFn5ZqaGH2OJ6HKk2NRVk0s19bpGE0qROw8XqoLaHrl2MbUSfdXv34sVf+DUBb iymuRI1xM9TuNJtGFlFnZ19X2vWr4c9tNa4QGmfzht+9hEMLeD0ymHhGU6jsqT13Mh 5vSV+8CWuQp5z++nE3yV/gFB8Xkafkx+HVPMcvclMjBddewvQqcLVsOIlQFdW1EKkz xb2OLPuFdNV0gCfKRAW6XMmlONmiLocH+s3wChGXAFZTlkeKRDBO4kN2xoU7xIF4hH Au9H717kdzrig== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=kernel.org X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=JOs9JzpE Subject: Re: [Intel-wired-lan] [net-next, v2, 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edumazet@google.com, anthony.l.nguyen@intel.com, robh@kernel.org, leon@kernel.org, andrew+netdev@lunn.ch, linux-rdma@vger.kernel.org, przemyslaw.kitszel@intel.com, arkadiusz.kubalewski@intel.com, aleksandr.loktionov@intel.com, intel-wired-lan@lists.osuosl.org, Jakub Kicinski , pabeni@redhat.com, devicetree@vger.kernel.org, conor+dt@kernel.org, jiri@resnulli.us, richardcochran@gmail.com, saravanak@kernel.org, Prathosh.Satish@microchip.com, vadim.fedorenko@linux.dev, netdev@vger.kernel.org, mbloch@nvidia.com, linux-kernel@vger.kernel.org, tariqt@nvidia.com, aleksander.lobakin@intel.com, jonathan.lemon@gmail.com, krzk+dt@kernel.org, saeedm@nvidia.com, davem@davemloft.net Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" This is an AI-generated review of your patch. The human sending this email has considered the AI review valid, or at least plausible. For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html --- ice: dpll: Support E825-C SyncE and dynamic pin discovery This patch adds DPLL support for the Intel E825-C Ethernet controller. It implements dynamic pin discovery via firmware nodes, asynchronous registration using a DPLL notifier chain, and hardware configuration for CGU registers. > diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c > index 4eca62688d83..9d82748810a3 100644 [ ... ] > +static void ice_dpll_pin_notify_work(struct work_struct *work) > +{ > + struct ice_dpll_pin_work *w = container_of(work, > + struct ice_dpll_pin_work, > + work); > + struct ice_dpll_pin *pin, *parent = w->pin; > + struct ice_pf *pf = parent->pf; > + int ret; > + > + switch (w->action) { > + case DPLL_PIN_CREATED: > + if (!IS_ERR_OR_NULL(parent->pin)) { > + /* We have already our pin registered */ > + goto out; > + } > + > + /* Grab reference on fwnode pin */ > + parent->pin = fwnode_dpll_pin_find(parent->fwnode, > + &parent->tracker); > + if (IS_ERR_OR_NULL(parent->pin)) { > + dev_err(ice_pf_to_dev(pf), > + "Cannot get fwnode pin reference\n"); > + goto out; > + } > + > + /* Register rclk pin */ > + pin = &pf->dplls.rclk; > + ret = dpll_pin_on_pin_register(parent->pin, pin->pin, > + &ice_dpll_rclk_ops, pin); Can pin->pin (pf->dplls.rclk.pin) be NULL here? Looking at the init order in ice_dpll_init_pins_e825(): ret = ice_dpll_init_fwnode_pins(pf, pf->dplls.inputs, 0); ... ret = ice_dpll_init_rclk_pin(pf, DPLL_PIN_IDX_UNSPEC, ...); The fwnode pins are initialized first, which registers notifiers. If a DPLL_PIN_CREATED notification fires before ice_dpll_init_rclk_pin() completes, this work handler will run while pf->dplls.rclk.pin is still NULL (the structure is zeroed by kcalloc). Passing NULL to dpll_pin_on_pin_register() causes a NULL dereference in dpll_xa_ref_pin_add() when it accesses pin->parent_refs. > + if (ret) { > + dev_err(ice_pf_to_dev(pf), > + "Failed to register pin: %pe\n", ERR_PTR(ret)); > + dpll_pin_put(parent->pin, &parent->tracker); > + parent->pin = NULL; > + goto out; > + } > + break; [ ... ] > diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c > index 4c8d20f2d2c0..0eb8a9e29a52 100644 > --- a/drivers/net/ethernet/intel/ice/ice_ptp.c > +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c > @@ -1341,6 +1341,35 @@ void ice_ptp_link_change(struct ice_pf *pf, bool linkup) > if (pf->hw.reset_ongoing) > return; > > + if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) { > + int pin, err; > + > + mutex_lock(&pf->dplls.lock); Should this check ICE_FLAG_DPLL before using pf->dplls.lock? Looking at ice_dpll_init_e825(), if initialization fails the mutex is destroyed: err = ice_dpll_init_info_e825c(pf); if (err) goto err_exit; ... err_exit: mutex_destroy(&d->lock); But ICE_FLAG_DPLL is only set on success. If DPLL init fails and a link change event occurs, this code will use a destroyed mutex. > + for (pin = 0; pin < ICE_SYNCE_CLK_NUM; pin++) { > + enum ice_synce_clk clk_pin; > + bool active; > + u8 port_num; > + > + port_num = ptp_port->port_num; > + clk_pin = (enum ice_synce_clk)pin; > + err = ice_tspll_bypass_mux_active_e825c(hw, > + port_num, > + &active, > + clk_pin); > + if (WARN_ON_ONCE(err)) { > + mutex_unlock(&pf->dplls.lock); > + return; > + } > + > + err = ice_tspll_cfg_synce_ethdiv_e825c(hw, clk_pin); > + if (active && WARN_ON_ONCE(err)) { > + mutex_unlock(&pf->dplls.lock); > + return; > + } > + } > + mutex_unlock(&pf->dplls.lock); > + }