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[2001:999:48c:ff1:3920:79f7:a7df:45d9]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2b13b13bbsm3111080e87.0.2026.04.01.00.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 00:26:00 -0700 (PDT) Date: Wed, 1 Apr 2026 10:25:56 +0300 From: Timo Teras To: "Ruinskiy, Dima" Cc: "Lifshits, Vitaly" , "Brandt, Todd E" , David Box , Len Brown , "intel-wired-lan@lists.osuosl.org" , "marmarek@invisiblethingslab.com" , "jeremie.wenger@edu.ge.ch" Message-ID: <20260401102556.64d226c8@onyx.my.domain> In-Reply-To: References: <20260202103257.1972097-1-vitaly.lifshits@intel.com> <20260210131158.1055ad48@onyx.my.domain> <745b1cd3-3e02-4d50-b1cb-0463ae6a9dd3@intel.com> <20260212111506.16bc402a@onyx.my.domain> <29b8a4b4-66d4-47e5-a316-b88a03b3882c@intel.com> <20260226143616.608ba411@onyx.my.domain> <35bc35d8-ff5d-4596-9f9f-6ab563c890b0@intel.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-alpine-linux-musl) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=none (p=none dis=none) header.from=iki.fi Subject: Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: reconfigure PLL clock gate value and re-enable K1 on Meteor Lake X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Hi On Wed, 1 Apr 2026 10:07:45 +0300 "Ruinskiy, Dima" wrote: > On 25/03/2026 17:49, Ruinskiy, Dima wrote: > > On 26/02/2026 14:36, Timo Teras wrote: =20 > >> Yes, generally maintaining a large quirk set is infeasible. > >> > >> But this is my point: if the affected set of machines with this issue > >> is so large that maintaining a quirk set becomes infeasible, then > >> the proposed change will make life very difficult for large enough > >> set of people that a better solution should be devised. > >> =20 > > At this point, with the current PLL change, it looks like the number of= =20 > > affected systems would be smaller than would be with the previous PLL=20 > > value. > >=20 > > So far we have not received additional reports of regressions caused by= =20 > > this patch, other than yours. So, perhaps, the it can be manageable wit= h=20 > > a DMI quirk approach. I went ahead and implemented the infrastructure,= =20 > > it's actually quite a small change, and does what I want (automatically= =20 > > alters the default value of the K1 disable flag). I would not make quick judgement on not receiving any reports that there is not other hardware where this causes issues. I do hope this is the situation. But as it happened in the past the reports start typically with a delay after the commit makes it into an upstream release. We had the patched kernel with the PLL change running for a bit longer time, and we observed that it also caused packet loss / very slow network issues in the Dell laptop. Especially with the later suggested value 0x226. > > Could you share the DMI IDs of your system, where the issue is observed= ?=20 > > Most likely the sys_vendor, product_family and product_name, located=20 > > under /sys/class/dmi/id would be the most useful. I can add them as an= =20 > > initial DMI table entry for v3 of this patch (or a follow-up patch). sys_vendor: Dell Inc. product_family: Dell Pro Laptops product_name: Dell Pro 16 Plus PB16250 See also the original report for a full dmesg at: https://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20250623/048= 860.html =46rom dmesg: DMI: Dell Inc. Dell Pro 16 Plus PB16250/0W8RP8, BIOS 2.3.1 05/16/2025 e1000e 0000:00:1f.6 eth0: MAC: 16, PHY: 12, PBA No: FFFFFF-0FF I would not be surprised if other Dell models with same chipset are affected. But this is the only one I have available to test with. Maybe its worth to check based on sys_vendor and/or product_family together with the MAC and/or PHY version? That is to exclude product_name? Thanks! Timo