From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10C3BF45A0D for ; Fri, 10 Apr 2026 20:38:21 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id AC06661118; Fri, 10 Apr 2026 20:38:21 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id GW9eVh3TNsc3; Fri, 10 Apr 2026 20:38:20 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver= DKIM-Filter: OpenDKIM Filter v2.11.0 smtp3.osuosl.org 37BCC6110E DKIM-Signature: v=1; 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Fri, 10 Apr 2026 20:38:18 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id LIpc4wsKXrHU for ; Fri, 10 Apr 2026 20:38:18 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2600:3c0a:e001:78e:0:1991:8:25; helo=sea.source.kernel.org; envelope-from=kuba@kernel.org; receiver= DMARC-Filter: OpenDMARC Filter v1.4.2 smtp3.osuosl.org 49F3B61101 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp3.osuosl.org 49F3B61101 Received: from sea.source.kernel.org (sea.source.kernel.org [IPv6:2600:3c0a:e001:78e:0:1991:8:25]) by smtp3.osuosl.org (Postfix) with ESMTPS id 49F3B61101 for ; Fri, 10 Apr 2026 20:38:18 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 8F20C43344; Fri, 10 Apr 2026 20:38:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62914C19421; Fri, 10 Apr 2026 20:38:14 +0000 (UTC) Date: Fri, 10 Apr 2026 13:38:12 -0700 From: Jakub Kicinski To: "Nitka, Grzegorz" Message-ID: <20260410133812.4cf9b090@kernel.org> In-Reply-To: References: <20260402230626.3826719-1-grzegorz.nitka@intel.com> <20260406192312.0f7a2760@kernel.org> <20260409181041.395a0c37@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775853497; bh=B6+j5N5qAy6nbb1b9iueruT9QbUx2CuqHxkBpEuTEmM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JmBU1qDNA8QqEGMGjmAJtjkRxxIl4Pt50tPXswPzd/pORv/6YRvby1WKbSvnlulgv FVy1CaNm+G124JwlGB5e1etPOAG3+cwzCUZOvf9vNnHLp5NlZOPQGO/ygUxUOSCPAY bjcfCTBT4vi9Iab8Rp8PAkXCAWhfnia6mZ+2+rk/NasCH7zL5ERjxWZIe+W8x/oVpK VtPrL+I9S4YkpkhbbJ+WsY8NNx/h95KZSWpmUdKnJr9mQvz7Vu3uU96z7TthrBlDm+ fbb51lN3B9gFHcV7ufIyzM3175tO+dPy9Bzff5p8FiYYWNdnfpq4adqUaJ3r3ong8i jXWkNvc1XftxA== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=kernel.org X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=JmBU1qDN Subject: Re: [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Vecera, Ivan" , "vadim.fedorenko@linux.dev" , "jiri@resnulli.us" , "edumazet@google.com" , "netdev@vger.kernel.org" , "richardcochran@gmail.com" , "donald.hunter@gmail.com" , "linux-kernel@vger.kernel.org" , "Kubalewski, Arkadiusz" , "Prathosh.Satish@microchip.com" , "andrew+netdev@lunn.ch" , "intel-wired-lan@lists.osuosl.org" , "horms@kernel.org" , "Kitszel, Przemyslaw" , "Nguyen, Anthony L" , "pabeni@redhat.com" , "davem@davemloft.net" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On Fri, 10 Apr 2026 14:23:58 +0000 Nitka, Grzegorz wrote: > Here is the high-level connection diagram for E825 device. I hope you find it helpful: > [..] It does thanks a lot. > Before this series, we tried different approaches. > One of them was to create MUX pin associated with netdev interface. > EXT_REF and SYNCE pins were registered with this MUX pin. > However I recall there were at least two issues with this solution: > - when using DPLL subsystem not all the connections/relations were visible > from DPLL pin-get perspective. RT netlink was required > - due to mixing pins from different modules (like fwnode based pin from zl driver > and the pins from ice), we were not able to safely clean the references between > pins and dpll (basicaly .. we observed crashes) > > Proposed solution just seems to be clean and fully reflects current > connection topology. Do you have the link to the old proposal that was adding stuff to rtnetlink? I remember some discussion long-ish ago, maybe I was wrong. > What's actually your biggest concern? > The fact we introduce a new DPLL type? Or multiply DPLL instances? Or both? > Do you prefer to see "one big" DPLL with 16 pins in our case (8 ports x 2 tx-clk pins)? > Each pin with the name like, for example, PF0-SyncE/PF0-eRef etc.? My concern is that I think this is a pretty run of the mill SyncE design. If we need to pretend we have two DPLLs here if we really only have one and a mux - then our APIs are mis-designed :(