From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64916F34C6B for ; Mon, 13 Apr 2026 17:41:01 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 0DF9F60EAE; Mon, 13 Apr 2026 17:41:01 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id iPcjgZQnAkZz; Mon, 13 Apr 2026 17:41:00 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver= DKIM-Filter: OpenDKIM Filter v2.11.0 smtp3.osuosl.org 09B2360E49 DKIM-Signature: v=1; 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charset=US-ASCII Content-Transfer-Encoding: 7bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776102055; bh=0N4BCYvO1+Hekbec44W1YKBqMvRW8D/6DQUbra7OWXM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=X5kp8GuU2+Zb0pS0yNLjVoEp8rBKG3Q21yTnrDjIY7ZM2U+9a+hi4HgHm/lMr8UNI vpjDIGFcNffSiLj01LAL6dAQrdQuu9D/ho7gPuGDN9CypsV7Mnp38ZILUsegyf3hzZ D0ItKRXD8uJieku1w25W3QWiuPcur5ly+IqpAgOszAt2q8rubZHwDu+YgOXE63XbRQ Nbx0wDj6GIzmz+69rPLCt3/uXfDKW8v0wtyl8fW81+KEKRGvOQQvwJU0RfJK7qnac9 Qfio15bMQbzyGgSERwSEB1LloUuayrwOIagCS3S7sQBrc373RREfluQCgEFDlpimNh 0rMQ3+hCW8EMQ== X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=kernel.org X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=X5kp8GuU Subject: Re: [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Vecera, Ivan" , "vadim.fedorenko@linux.dev" , "edumazet@google.com" , "netdev@vger.kernel.org" , "richardcochran@gmail.com" , "donald.hunter@gmail.com" , "linux-kernel@vger.kernel.org" , "davem@davemloft.net" , "Prathosh.Satish@microchip.com" , "andrew+netdev@lunn.ch" , "intel-wired-lan@lists.osuosl.org" , "horms@kernel.org" , "Kitszel, Przemyslaw" , "Nguyen, Anthony L" , "pabeni@redhat.com" , "jiri@resnulli.us" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On Mon, 13 Apr 2026 08:19:30 +0000 Kubalewski, Arkadiusz wrote: > >My concern is that I think this is a pretty run of the mill SyncE > >design. If we need to pretend we have two DPLLs here if we really > >only have one and a mux - then our APIs are mis-designed :( > > Well, the true is that we did not anticipated per-port control of the > TX clock source, as a single DPLL device could drive multiple of such. > > This is not true, that we pretend there is a second PLL - there is a > PLL on each TX clock, maybe not a full DPLL, but still the loop with > a control over it's sources is there and it has the same 2 external > sources + default XO. Let me dig around and see if I can find any docs for PLL IPs that get integrated into ASICs. The DPLL subsystem has implicitly focused on standalone, timing related PLLs. Every ASIC out there has a bunch of PLLs to generate the clock signals. It's not clear to me that DPLL subsystem is the right fit for this. Ping me if I don't get back to this by the end of the week please. I'll need to wrap up net-next and send the PR first.. > A mentioned try of adding per port MUX-type pin, just to give some control > to the user, is where we wanted to simplify things, but in the end the API > would have to be modified in significant way, various paths related to pin > registration and keeping correct references, just to make working case > for the pin_on_pin_register and it's internals. We decided that the burden > and impact for existing design was to high. > > And that is why the TXC approach emerged, the change of DPLL is minimal, > The model is still correct from user perspective, SyncE SW controller shall > anticipate possibility that per-port TXC dpll is there > > This particular device and driver doesn't implement any EEC-type DPLL > device, the one could think that we can just change the type here and use > EEC type instead of new one TXC - since we share pins from external dpll > driver, which is EEC type, and our DPLL device would have different clock_id > and module. But, further designs, where a single NIC is having control over > both a EEC DPLL and ability to control each source per-port this would be > problematic. At least one NIC Port driver would have to have 2 EEC-type DPLLs > leaving user with extra confusion.