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04 May 2026 04:01:03 -0700 X-CSE-ConnectionGUID: 1Jr09M9ZRjCWXsJ9erLfmQ== X-CSE-MsgGUID: X24t4QpYRCS3srp9wepcXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,215,1770624000"; d="scan'208";a="239792124" Received: from gnrd8.igk.intel.com (HELO GNRD8) ([10.123.232.137]) by orviesa004.jf.intel.com with ESMTP; 04 May 2026 04:01:01 -0700 From: Sergey Temerkhanov To: intel-wired-lan@lists.osuosl.org Date: Mon, 4 May 2026 11:00:58 +0000 Message-ID: <20260504110058.2373236-4-sergey.temerkhanov@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260504110058.2373236-1-sergey.temerkhanov@intel.com> References: <20260504110058.2373236-1-sergey.temerkhanov@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777892463; x=1809428463; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=NYS+R40mOjYf6fmrJkydT5fr4ckbVWfdyHgaoqz5wAk=; b=hvco6sQHC/4mnw+3P6+DjZqbtH660IjkDVnB6cUHV1joM/gVzGELnAf0 sKUqKuWm45MtnvIdfxGhaMGRMzQ8YKt6dMnQYK4FGCkZCMAUMK4mJ+dv/ fX/3nxUqE25n0o3u9H2z4eyK0pZTKP5n7Q4R8h3S9iPqM1If4uRrJyfJ7 VQD0TDwEs9ksOjYJjN8BSMf+/h3rkOkg0talv4uDC+AM/ZdeUMoDo/C6H +BnNYAkPBYkmESV8kkTqBUhw6Sc6+nZlIjiFXmn8ivHoLhs9FTZMQoXs1 ++X1Mai9j4qR4sUA2nLyso+LA0J5I4X8geom4WXkgIubuCtxG+rX69jw8 w==; X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=hvco6sQH Subject: [Intel-wired-lan] [PATCH iwl-net v1 3/3] ice: Cache struct ice_hw pointer for split register reads X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Cache the primary ice_hw pointer to ensure consistency between calls (both parts of a value will be read from the same NAC). ice_get_primary_hw() will never return NULL, but during the ctrl_pf cleanup there may be a case when one call will return the pointer to the ctrl_pf->hw and the subsequent one - to the pf->hw which generally are not the same. Struct ice_hw is embedded in the struct ice_pf so it is protected by the same critical section - no additional synchronization is needed. Fixes: e2193f9f9ec9 ("ice: enable timesync operation on 2xNAC E825 devices") Signed-off-by: Sergey Temerkhanov Reviewed-by: Aleksandr Loktionov Reviewed-by: Arkadiusz Kubalewski --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 892bcc50e82f..95238224b59a 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -4,6 +4,7 @@ #include #include #include +#include "ice.h" #include "ice_common.h" #include "ice_ptp_hw.h" #include "ice_ptp_consts.h" @@ -1988,10 +1989,14 @@ static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); } else { + struct ice_hw *pri_hw; + guard(rcu)(); - zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx)); - lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx)); + pri_hw = ice_get_primary_hw(pf); + + zo = rd32(pri_hw, GLTSYN_SHTIME_0(tmr_idx)); + lo = rd32(pri_hw, GLTSYN_SHTIME_L(tmr_idx)); } *phc_time = (u64)lo << 32 | zo; @@ -2159,10 +2164,14 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); } else { + struct ice_hw *pri_hw; + guard(rcu)(); - lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx)); - hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx)); + pri_hw = ice_get_primary_hw(pf); + + lo = rd32(pri_hw, GLTSYN_INCVAL_L(tmr_idx)); + hi = rd32(pri_hw, GLTSYN_INCVAL_H(tmr_idx)); } incval = (u64)hi << 32 | lo; -- 2.53.0