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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id B9F193F7041; Thu, 7 May 2026 20:49:40 -0700 (PDT) From: Ratheesh Kannoth To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Ratheesh Kannoth Date: Fri, 8 May 2026 09:19:05 +0530 Message-ID: <20260508034912.4082520-3-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260508034912.4082520-1-rkannoth@marvell.com> References: <20260508034912.4082520-1-rkannoth@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: mIZUNbQgqFhIKvwAl1gsnIIP3dR0l610 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDAzMyBTYWx0ZWRfXytgNrDRTptqJ nsux18mdiNswztiaGb87eN2rVJ4yMhSOyXZwu5m3YGwLJnCZsuVY1TuNnmXj+r2dc/VectyfntT Z6Zxon+0B7BAyihibK+74825huMoSVu+BHOonXL8O/kHj6a4Po5qfXRyColfGYqMW0NhAoBjpqw bXXTV/kPmvIdprpjFvpHGsoZljQLqARVCq4PJS2cRxeOUf/4bifLQgrfZQNXwqN57HD91QyIRAu seHOJ/VjNL0+ra1iFoH+SUPLcR5eZy/RgpBATC0ECJnKE8s9MELlDOxyiayYEnB6jAQlrOCIlg5 LpNHINbDXGVlF/WrzvdtvKrBiJRoVaFDVVNqeVoNguwb6bpXQdZxUAgJvMykNvfwQ+iNKEar+8i 8CVOfnAUDd61U2u0knmUfGk2j9JU89Ed8jJ5mYfpaGwqkmJPxO75KKVdi30GG0KadNxPhzPGmGH pg0Ow8e5PRozoLc7mlQ== X-Proofpoint-GUID: mIZUNbQgqFhIKvwAl1gsnIIP3dR0l610 X-Authority-Analysis: v=2.4 cv=WMBPmHsR c=1 sm=1 tr=0 ts=69fd5d60 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=YjTTaRMW2Sk_qnKZcsQA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Mailman-Approved-At: Fri, 08 May 2026 22:09:04 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=w NoyjCcOt9iCXEZtiOjB9y5jkpJj2m5Kh9tPG4kCON8=; b=gAy6wfkcAoXTC/bZs ied3LxcaJxjNTXdOMSJ5hachPCyZpZBUZF1jR2gU7Mp8cWmtEGlTeepZCdwUq98u b3/noflsIz0d/ihXC0BM/Jk88PjPV2gueqEFQSRUpyvvSGbB+dmVfRmuQVEMVFnY NRUYWTQGoEc4eZlfUVWkIbkZ6jCaG8wWIt3TFGZQq9vdxeKucohvvvVmNQuIrBht BM4E3ROFgNUKxtvNFVKYxLeckqxSa+op9l+Cr+TkPKAePJPDyr4oZev5f3dW7sr6 n8Ghu3Fo4+1BHNP2fv86ABPp3cS0kDcSMGn72SetMQ5RQ7K1yy9dy5p0f7ocKqBB m0YEQ== X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dmarc=pass (p=none dis=none) header.from=marvell.com X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0220 header.b=gAy6wfkc Subject: [Intel-wired-lan] [PATCH v12 net-next 2/9] net/mlx5e: trim stack use in PCIe congestion threshold helper X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" union devlink_param_value grew when U64 array parameters were added. Keeping a four-element array of that union in mlx5e_pcie_cong_get_thresh_config() inflated the stack frame past the -Wframe-larger-than limit. Read each driverinit value into a single reused union, then store the four u16 thresholds in struct mlx5e_pcie_cong_thresh field order via a temporary u16 pointer to config. Signed-off-by: Ratheesh Kannoth --- .../mellanox/mlx5/core/en/pcie_cong_event.c | 34 +++++++++++-------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index 2eb666a46f39..88e76be3a73d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -252,28 +252,32 @@ static int mlx5e_pcie_cong_get_thresh_config(struct mlx5_core_dev *dev, struct mlx5e_pcie_cong_thresh *config) { + enum { + INBOUND_HIGH, + INBOUND_LOW, + OUTBOUND_HIGH, + OUTBOUND_LOW, + }; + u32 ids[4] = { - MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW, - MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH, - MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW, - MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH, + [INBOUND_LOW] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW, + [INBOUND_HIGH] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH, + [OUTBOUND_LOW] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW, + [OUTBOUND_HIGH] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH, }; - struct devlink *devlink = priv_to_devlink(dev); - union devlink_param_value val[4]; - for (int i = 0; i < 4; i++) { - u32 id = ids[i]; - int err; + struct devlink *devlink = priv_to_devlink(dev); + union devlink_param_value val; + u16 *dst = (u16 *)config; + int err; - err = devl_param_driverinit_value_get(devlink, id, &val[i]); + for (int i = 0; i < ARRAY_SIZE(ids); i++) { + err = devl_param_driverinit_value_get(devlink, ids[i], &val); if (err) return err; - } - config->inbound_low = val[0].vu16; - config->inbound_high = val[1].vu16; - config->outbound_low = val[2].vu16; - config->outbound_high = val[3].vu16; + dst[i] = val.vu16; + } return 0; } -- 2.43.0