From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A84FCDB466 for ; Sat, 20 Jun 2026 08:53:49 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id D72718617F; Sat, 20 Jun 2026 08:53:48 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id QjqZ27boCXtW; Sat, 20 Jun 2026 08:53:48 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.142; helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver= DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.osuosl.org 12A8B86180 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org; s=default; t=1781945628; bh=u8+egrML541MWpVVt07sjq5yP5ImkoHuZ/0MZ8y1gg4=; h=From:To:Cc:Date:In-Reply-To:References:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=xREVyvS7Mi2iTAImqR1eg5x8nIlemp6UnkVR5Va5rm6DFaXWAAWduhQcWHmtXd/Y0 ILkpTkh5RaOrSmeAXfQ8QHvCn5S45Sv9DT1dyrtB0XdT2XMwKcK1yjxFeioLemzLO9 NVsUYJ5aJhYbVpokTxy25EBfRUIlhpbSl+3+jG0jaOWJEojA1g8VOv5DTvb2cQ4qgf kIcB7UvoBF+ogWe6Jz2KII0p+KfqfTtWoFKsjgiknEjOoAY72LXseEeSsByBIjXit6 B9K0Z29WQTb5gFznQanrMDkduiltfh2kpPzlfnyD79dw/llFQVKCYyWp+RD6QczrKE mh8pheIeWVFyw== Received: from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142]) by smtp1.osuosl.org (Postfix) with ESMTP id 12A8B86180; Sat, 20 Jun 2026 08:53:48 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [IPv6:2605:bc80:3010::136]) by lists1.osuosl.org (Postfix) with ESMTP id 38CCF367 for ; Sat, 20 Jun 2026 08:53:47 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 1EFE06FAAA for ; Sat, 20 Jun 2026 08:53:47 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id g-ddOZczePUs for ; Sat, 20 Jun 2026 08:53:46 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2600:3c0a:e001:78e:0:1991:8:25; helo=sea.source.kernel.org; envelope-from=horms@kernel.org; receiver= DMARC-Filter: OpenDMARC Filter v1.4.2 smtp3.osuosl.org 3564D6FA9E DKIM-Filter: OpenDKIM Filter v2.11.0 smtp3.osuosl.org 3564D6FA9E Received: from sea.source.kernel.org (sea.source.kernel.org [IPv6:2600:3c0a:e001:78e:0:1991:8:25]) by smtp3.osuosl.org (Postfix) with ESMTPS id 3564D6FA9E for ; Sat, 20 Jun 2026 08:53:45 +0000 (UTC) Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 5931343A5D; Sat, 20 Jun 2026 08:53:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 239751F000E9; Sat, 20 Jun 2026 08:53:43 +0000 (UTC) From: Simon Horman To: sergey.temerkhanov@intel.com Cc: Simon Horman , intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, pmenzel@molgen.mpg.de Date: Sat, 20 Jun 2026 09:53:27 +0100 Message-ID: <20260620085327.965597-1-horms@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260618142212.310475-1-sergey.temerkhanov@intel.com> References: <20260618142212.310475-1-sergey.temerkhanov@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781945625; bh=u8+egrML541MWpVVt07sjq5yP5ImkoHuZ/0MZ8y1gg4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ZbMwWP+OaUZQPJMq0cU94POElOt381gzO7lVWcWpjfoKStmc75w+NTkz8MJ76jMIa L8EASZqerFldTUtqDkUQLke/ZaHg3KAHPDys2XuUB02AVf48l6jsNxTvgPNfwaCgJ6 KpqzSkYG6Y9mbhRh7NLifqUVKT9dvDROm2AbUU9oIi5booQnBl/4TP6pYYjhu0cFMU mzoGcI+6SUPiDrevr/xZxtO4eyz69EK37qwX5ZaQPgwwkcmKmQZ4ThFrcdzLf4WICv 3HT61xPbZUlzU3Ilx513/2CyRMyHbFUFPfb0YOHklKzObZ397WjaQPfzlL46JiLalV 09x4CsWyEpANg== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=kernel.org X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=ZbMwWP+O Subject: Re: [Intel-wired-lan] [PATCH iwl-next v2] ixgbe: Implement PCI reset handler X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" This is an AI-generated review of your patch. The human sending this email has considered the AI review valid, or at least plausible. Full review at: https://sashiko.dev --- ixgbe: Implement PCI reset handler Implement PCI device reset handler to allow the network device to get re-initialized and function after a PCI-level reset. > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c [ ... ] > @@ -12338,6 +12338,86 @@ static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) > +static void ixgbe_reset_prep(struct pci_dev *pdev) > +{ > + struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); > + > + if (!adapter) > + return; > + > + if (poll_timeout_us(test_and_set_bit(__IXGBE_RESETTING, &adapter->state), > + test_bit(__IXGBE_RESETTING, &adapter->state), [Severity: Medium] Does this introduce a new instance of an ad-hoc bit lock? According to the networking drivers guidelines, using bit operations like test_and_set_bit() to guard critical sections instead of proper synchronization primitives like a mutex or spinlock can hide issues from lockdep and lacks deadlock detection. [Severity: Critical] Does this misuse the poll_timeout_us() macro? The macro executes the operation before evaluating the condition. Since test_and_set_bit() unconditionally sets the bit to 1, test_bit() will always evaluate to true on the very first loop iteration, regardless of whether the lock was already held. Doesn't this completely break mutual exclusion? > + IXGBE_RESET_PREP_POLL_INTERVAL_US, > + IXGBE_RESET_PREP_TIMEOUT_US, false)) { > + /* ixgbe_reset_done() will exit early if this happens. > + * A retry will be needed > + */ > + e_err(drv, "Timed out waiting for __IXGBE_RESETTING to be released. Reset is needed\n"); > + return; [Severity: High] If this times out and returns early, won't it abandon the software reinitialization process while the PCI subsystem proceeds with the physical reset? The .reset_prepare callback returns void, so the reset continues. By returning early without setting __IXGBE_PCIE_RESET_IN_PROGRESS, critical teardowns are skipped, and ixgbe_reset_done() will also bail out early: ixgbe_reset_done() { if (!test_and_clear_bit(__IXGBE_PCIE_RESET_IN_PROGRESS, &adapter->state)) { e_err(drv, "Reset done called without PCIe reset in progress\n"); return; } } Could this permanently break the network interface until the module is reloaded? > + } > + > + /* Sync __IXGBE_RESETTING */ > + smp_mb__after_atomic(); > + > + if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) { > + /* Prevent the service task from being requeued in the timer callback */ > + timer_delete_sync(&adapter->service_timer); > + /* Cancel any possibly queued service task */ > + cancel_work_sync(&adapter->service_task); [Severity: Critical] Can this sequence cause a deadlock with the service task? Here in ixgbe_reset_prep(), __IXGBE_RESETTING has just been acquired, and then cancel_work_sync(&adapter->service_task) blocks waiting for the service task to complete. However, if the active service task reaches ixgbe_reinit_locked(): ixgbe_reinit_locked() { while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) usleep_range(1000, 2000); ... } The service task will spin infinitely waiting for __IXGBE_RESETTING to be cleared. Since ixgbe_reset_prep() holds the bit lock and is blocked waiting for the service task, neither thread can make progress. > + } > + > + pci_clear_master(pdev); > + > + set_bit(__IXGBE_PCIE_RESET_IN_PROGRESS, &adapter->state); > +} [ ... ] > +static void ixgbe_reset_done(struct pci_dev *pdev) > +{ > + struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); [ ... ] > + /* Allow the service task to run */ > + if (!test_bit(__IXGBE_REMOVING, &adapter->state)) { > + clear_bit(__IXGBE_RESETTING, &adapter->state); > + /* Sync __IXGBE_RESETTING */ > + smp_mb__after_atomic(); [Severity: Medium] Does this provide the correct release semantics for the ad-hoc lock? The clear_bit() operation does not imply a memory barrier, and smp_mb__after_atomic() only orders memory operations that occur after the atomic operation. Could memory accesses from within the critical section (like the pci_set_master() call earlier) bleed past the lock release, allowing other threads to acquire the lock too early? Is it possible to use clear_bit_unlock() or place an smp_mb__before_atomic() prior to the clear_bit() instead? > + } [ ... ]