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Thu, 17 Sep 2026 19:03:04 +0000 (UTC) Received: from ShadowPeak.redhat.com (unknown [10.44.49.1]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0E6F719AC048; Thu, 17 Sep 2026 19:03:00 +0000 (UTC) From: Petr Oros To: netdev@vger.kernel.org Cc: Petr Oros , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-net 0/2] ice: DPLL init fixes for E810 timing boards Date: Thu, 17 Sep 2026 21:02:56 +0200 Message-ID: <20260917190258.3239282-1-poros@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mimecast-MFC-PROC-ID: nkJFWIv2J9dnn4GIW4fWwv7169dXYdh9Lhdkcier_f4_1789671784 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Two fixes for E810-C timing boards the driver's static pin tables were not written for, seen on a board whose netlist has no PCA9575 clock mux and whose CGU reports more pins than the tables describe. The first layout is a reference design of its own, Intel ships it as the E810_C827_SyncE_SFP_SEC NVM configuration. Patch 1 keeps the DPLL registration alive when the PCA9575 clock mux is missing. Today the lookup fails and the driver gives up on the whole DPLL, so userspace loses both devices and every pin. Patch 2 stops the SMA and U.FL wrapper setup from indexing the input and output arrays at fixed positions when the driver has already fallen back to generic pins, where those positions can lie past the end of the arrays. Both are tested on an E810-T with the mux present, with the mux hidden from the driver, and with the generic pin path forced, and on the board above, where both DPLLs now lock. A follow-up for iwl-next derives the generic pin names from the pin classification the firmware reports, so such boards get addressable pins instead of ambiguous numbers. Petr Oros (2): ice: fix DPLL registration on boards without the SMA clock mux ice: skip the SW pin description on boards with generic DPLL pins drivers/net/ethernet/intel/ice/ice_dpll.c | 33 +++++++++++++++++------ 1 file changed, 25 insertions(+), 8 deletions(-) -- 2.55.0