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X-CSE-ConnectionGUID: kjXVVx7CT7W8fJDGjL1sQQ== X-CSE-MsgGUID: I4DtdyaASp+PBjLqBgpJ9g== X-IronPort-AV: E=McAfee;i="6800,10657,11913"; a="108232048" X-IronPort-AV: E=Sophos;i="6.27,116,1787036400"; d="scan'208";a="108232048" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 11:04:24 -0700 X-CSE-ConnectionGUID: C7mE2pZmRJKQ/eyWUD3DVw== X-CSE-MsgGUID: Ucuzgu9nStCy6AYIXoT2Dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,116,1787036400"; d="scan'208";a="281315334" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2026 11:04:24 -0700 From: Jacob Keller Date: Tue, 22 Sep 2026 11:02:43 -0700 Subject: [PATCH iwl-net v2 10/15] ice: E825: perform a soft reset when starting the PHY timer MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260922-jk-e825c-timestamp-processing-logic-fixes-srcu-v2-10-e55b692d0e6b@intel.com> References: <20260922-jk-e825c-timestamp-processing-logic-fixes-srcu-v2-0-e55b692d0e6b@intel.com> In-Reply-To: <20260922-jk-e825c-timestamp-processing-logic-fixes-srcu-v2-0-e55b692d0e6b@intel.com> To: Jacob Keller , Grzegorz Nitka , Arkadiusz Kubalewski , Intel Wired LAN , Maciej Machnikowski , Przemyslaw Korba , netdev@vger.kernel.org, Anthony Nguyen Cc: Jacob Keller , Maciek Machnikowski X-Mailer: b4 0.17-dev-8b7ea X-Developer-Signature: v=1; a=openpgp-sha256; l=2054; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=uYQTnh0Hg1Gx19CjcekG5cvjGDYmClExgwMLJ2AUOzw=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhqxNh2XWa6lnbeJ34ktfvm39wg6/8we/cDhP7njgLHXXZ od21aTHHaUsDGJcDLJiiiwKDiErrxtPCNN64ywHM4eVCWQIAxenAEzktx/DP4UmPs0EvZmq207E L1if/n9L+RGDvi43kec7gw/a1YTGsTAyLFz98XditEIio8FH9aWm/pc2JGfvj8rwOs/2cbKIo4Q ZOwA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org To ensure that the E825 PHY timer begins in a clean state, initiate a PHY soft reset prior to programming the PHY. This ensures that we clear any outstanding Tx timestamp memory, and ensures that the PHY internal state including its timestamp counter has been reset. Note that despite the name, this PHY soft reset only impacts the timer block of the PHY, and not its regular Tx/Rx functionality. Additionally, many configuration registers such as the PHY_REG_TS_INT_CONFIG and PHY_REG_TX_OFFSET_READY are not reset. Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") Reviewed-by: Maciek Machnikowski Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index e1a5ff5793d1..f8f985a5d039 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2128,9 +2128,11 @@ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port) * @hw: pointer to the HW struct * @port: the PHY port to start * - * Start the clock of a PHY port. This must be done as part of the flow to - * re-calibrate Tx and Rx timestamping offsets whenever the clock time is - * initialized or when link speed changes. + * Perform a PHY soft reset and then start the clock for the PHY port. + * + * This must be done as part of the flow to re-calibrate Tx and Rx + * timestamping offsets whenever the clock time is initialized or when link + * speed changes. * * Return: * * %0 - success @@ -2150,6 +2152,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) if (err) return err; + err = ice_ptp_phy_soft_reset_eth56g(hw, port); + if (err) + return err; + ice_ptp_src_cmd(hw, ICE_PTP_NOP); err = ice_phy_cfg_parpcs_eth56g(hw, port); -- 2.56.0.rc0.395.gd1f3524e15dc