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25 Sep 2026 16:58:04 -0700 X-CSE-ConnectionGUID: 0P5v0ebMQqSTIPtZ7ZThdw== X-CSE-MsgGUID: oP88gOiCRXG+FM4aq3rp1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,123,1787036400"; d="scan'208";a="300731145" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2026 16:58:03 -0700 From: Jacob Keller Date: Fri, 25 Sep 2026 16:56:47 -0700 Subject: [PATCH iwl-net v3 15/15] ice: Recalibrate PHY after settime64 on E825-C MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260925-jk-e825c-timestamp-processing-logic-fixes-srcu-v3-15-6532598e8da8@intel.com> References: <20260925-jk-e825c-timestamp-processing-logic-fixes-srcu-v3-0-6532598e8da8@intel.com> In-Reply-To: <20260925-jk-e825c-timestamp-processing-logic-fixes-srcu-v3-0-6532598e8da8@intel.com> To: Intel Wired LAN , Maciej Machnikowski , Jacob Keller , Przemyslaw Korba , Anthony Nguyen , Grzegorz Nitka , Arkadiusz Kubalewski Cc: Jacob Keller , Maciek Machnikowski , Paul Menzel , Aleksandr Loktionov X-Mailer: b4 0.17-dev-8b7ea X-Developer-Signature: v=1; a=openpgp-sha256; l=3924; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=XJYnGOIzMrOMQ/LcUzFdKbpZXkVUbFwdfMxUeBc7hyU=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhqztXDUq3rPFixlbAmsuHH+tH7p3xd0NP74E3rzfbqXXL dLmm3+ro5SFQYyLQVZMkUXBIWTldeMJYVpvnOVg5rAygQxh4OIUgInY72Fk6H12fNvKJ9c3HDO1 nfxZXjrFUuCnqv9NNjFZI485n6KaQxn+x3WJhrKE+TB/fFyySUn4x0Y2hzM8ZyqY1yyaMnPJ9v3 anAA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org From: Maciek Machnikowski The PHY on E825-C requires recalibration after large jumps of the system time. This step is required and is done for E822 devices previously, but was accidentally skipped due to oversight when E825-C support was added. Lack of recalibration will fail to converge quickly as the effective adjustment requested is not applied properly to the PHY timestamps, so the readings from the timestamp are incorrect. Without the fix: > ptp4l[12591.505]: port 1 (eno8303np0): SLAVE to UNCALIBRATED on SYNCHRONIZATION_FAULT > ptp4l[12591.951]: port 1 (eno8303np0): UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED > ptp4l[12592.027]: rms 752851973 max 1102277559 freq -84408798 +/- 53560133 delay 6009 +/- 92308 > ptp4l[12593.038]: rms 91302045 max 136894784 freq +100000000 +/- 0 delay 93700 +/- 24153 > ptp4l[12594.050]: rms 16036314 max 35711594 freq +47433070 +/- 46746070 delay 44899 +/- 45255 > ptp4l[12595.061]: rms 5558880 max 12292103 freq -13092285 +/- 6627317 delay -13499 +/- 6560 > ptp4l[12596.073]: rms 759533 max 1081638 freq +837063 +/- 802691 delay 711 +/- 979 > ptp4l[12597.085]: rms 60485 max 106800 freq +146706 +/- 263535 delay 145 +/- 263 > ptp4l[12598.096]: rms 16428 max 41896 freq -46707 +/- 34325 delay -40 +/- 34 > ptp4l[12599.108]: rms 3049 max 5356 freq +5337 +/- 1730 delay 7 +/- 2 > ptp4l[12600.120]: rms 284 max 381 freq +104 +/- 759 delay 2 +/- 1 > ptp4l[12601.131]: rms 42 max 119 freq -124 +/- 143 delay 2 +/- 0 > ptp4l[12602.144]: rms 11 max 25 freq +39 +/- 12 delay 3 +/- 0 > ptp4l[12603.156]: rms 2 max 4 freq +14 +/- 5 delay 3 +/- 0 > ptp4l[12604.167]: rms 1 max 3 freq +15 +/- 5 delay 2 +/- 0 > ptp4l[12605.179]: rms 1 max 4 freq +16 +/- 5 delay 2 +/- 1 > ptp4l[12606.191]: rms 1 max 3 freq +15 +/- 5 delay 3 +/- 0 With the fix: > ptp4l[12834.266]: rms 27178238388098 max 30079328952737 freq +479164 +/- 1040869 delay 5 +/- 1 > ptp4l[12834.522]: port 1 (eno8703np0): minimum delay request interval 2^-8 > ptp4l[12835.315]: rms 86919 max 139746 freq +111289 +/- 539214 delay -35 +/- 28 > ptp4l[12836.376]: rms 5415 max 8884 freq +579 +/- 22798 delay 4 +/- 5 > ptp4l[12837.429]: rms 335 max 559 freq -305 +/- 842 delay 4 +/- 1 > ptp4l[12838.471]: rms 20 max 45 freq +79 +/- 33 delay 4 +/- 0 > ptp4l[12839.512]: rms 2 max 5 freq +44 +/- 8 delay 4 +/- 0 > ptp4l[12840.545]: rms 1 max 4 freq +46 +/- 8 delay 4 +/- 0 > ptp4l[12841.586]: rms 1 max 3 freq +46 +/- 7 delay 4 +/- 0 > ptp4l[12842.637]: rms 1 max 3 freq +46 +/- 7 delay 4 +/- 0 Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") Signed-off-by: Maciek Machnikowski Reviewed-by: Paul Menzel Reviewed-by: Aleksandr Loktionov Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_ptp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 8d302b500a39..a5fe05d70461 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2086,8 +2086,9 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) /* Reenable periodic outputs */ ice_ptp_enable_all_perout(pf); - /* Recalibrate and re-enable timestamp blocks for E822/E823 */ - if (hw->mac_type == ICE_MAC_GENERIC) + /* Recalibrate and re-enable timestamp blocks for E822/E823/E825-C */ + if (hw->mac_type == ICE_MAC_GENERIC || + hw->mac_type == ICE_MAC_GENERIC_3K_E825) ice_ptp_restart_all_phy(pf); exit: if (err) { -- 2.56.0.rc0.395.gd1f3524e15dc