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Fri, 02 Oct 2026 02:35:33 -0700 (PDT) Received: from sashaneftin-pc-GB-BSi5-1135G7.home ([185.175.35.55]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48b380fada5sm4134284f8f.24.2026.10.02.02.35.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2026 02:35:32 -0700 (PDT) From: Sasha Neftin To: intel-wired-lan@osuosl.org Subject: [iwl-next, v1] igb: Fix typo in IGB_NO_QUEUE macro definition Date: Fri, 2 Oct 2026 12:35:30 +0300 Message-ID: <20261002093530.150023-1-sashaneftin@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Correct the macro name from IGB_N0_QUEUE (using digit '0') to IGB_NO_QUEUE (using letter 'O') in igb_main.c and update its usage in igb_main.c. The typo in the igc driver was likely copied from this original typo in the igb driver, which has now been fixed previously in igc. Signed-off-by: Sasha Neftin --- drivers/net/ethernet/intel/igb/igb_main.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index d4a897a8c82c..73a08ab27221 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -754,13 +754,13 @@ static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, array_wr32(E1000_IVAR0, index, ivar); } -#define IGB_N0_QUEUE -1 +#define IGB_NO_QUEUE -1 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) { struct igb_adapter *adapter = q_vector->adapter; struct e1000_hw *hw = &adapter->hw; - int rx_queue = IGB_N0_QUEUE; - int tx_queue = IGB_N0_QUEUE; + int rx_queue = IGB_NO_QUEUE; + int tx_queue = IGB_NO_QUEUE; u32 msixbm = 0; if (q_vector->rx.ring) @@ -775,9 +775,9 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) * or more queues to a vector, we write the appropriate bits * into the MSIXBM register for that vector. */ - if (rx_queue > IGB_N0_QUEUE) + if (rx_queue > IGB_NO_QUEUE) msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; - if (tx_queue > IGB_N0_QUEUE) + if (tx_queue > IGB_NO_QUEUE) msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) msixbm |= E1000_EIMS_OTHER; @@ -790,11 +790,11 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) * lower 3 bits as the row index, and the 4th bit as the * column offset. */ - if (rx_queue > IGB_N0_QUEUE) + if (rx_queue > IGB_NO_QUEUE) igb_write_ivar(hw, msix_vector, rx_queue & 0x7, (rx_queue & 0x8) << 1); - if (tx_queue > IGB_N0_QUEUE) + if (tx_queue > IGB_NO_QUEUE) igb_write_ivar(hw, msix_vector, tx_queue & 0x7, ((tx_queue & 0x8) << 1) + 8); @@ -811,11 +811,11 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) * bit 0 as the column offset, and the remaining bits as the * row index. */ - if (rx_queue > IGB_N0_QUEUE) + if (rx_queue > IGB_NO_QUEUE) igb_write_ivar(hw, msix_vector, rx_queue >> 1, (rx_queue & 0x1) << 4); - if (tx_queue > IGB_N0_QUEUE) + if (tx_queue > IGB_NO_QUEUE) igb_write_ivar(hw, msix_vector, tx_queue >> 1, ((tx_queue & 0x1) << 4) + 8); -- 2.43.0