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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from CY8PR11MB7364.namprd11.prod.outlook.com (2603:10b6:930:87::14) by CYYPR11MB8432.namprd11.prod.outlook.com (2603:10b6:930:be::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.17; Wed, 23 Sep 2026 20:28:37 +0000 Received: from CY8PR11MB7364.namprd11.prod.outlook.com ([fe80::1b92:4856:eb86:f7e3]) by CY8PR11MB7364.namprd11.prod.outlook.com ([fe80::1b92:4856:eb86:f7e3%5]) with mapi id 15.21.0451.014; Wed, 23 Sep 2026 20:28:37 +0000 Message-ID: <54f684b4-b47f-4908-a330-64d47ddbd0e4@intel.com> Date: Wed, 23 Sep 2026 13:28:36 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH iwl-net v2 09/15] ice: E825: clear PHY_REG_TX_MEMORY_STATUS prior to soft reset To: "Loktionov, Aleksandr" , "Nitka, Grzegorz" , "Kubalewski, Arkadiusz" , Intel Wired LAN , "Machnikowski, Maciej" , "Korba, Przemyslaw" , "netdev@vger.kernel.org" , "Nguyen, Anthony L" References: <20260922-jk-e825c-timestamp-processing-logic-fixes-srcu-v2-0-e55b692d0e6b@intel.com> <20260922-jk-e825c-timestamp-processing-logic-fixes-srcu-v2-9-e55b692d0e6b@intel.com> Content-Language: en-US From: Jacob Keller In-Reply-To: Content-Type: text/plain; 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Nitka, Grzegorz >> ; Kubalewski, Arkadiusz >> ; Intel Wired LAN > lan@lists.osuosl.org>; Machnikowski, Maciej >> ; Korba, Przemyslaw >> ; netdev@vger.kernel.org; Nguyen, >> Anthony L >> Cc: Keller, Jacob E ; Machnikowski, Maciej >> >> Subject: [PATCH iwl-net v2 09/15] ice: E825: clear >> PHY_REG_TX_MEMORY_STATUS prior to soft reset >> >> The current implementation of ice_ptp_reset_ts_memory_eth56g() is >> flawed. >> It tries to clear the timestamp memory by writing to the >> PHY_REG_TX_MEMORY_STATUS region. This does not work properly, as it >> does not trigger appropriate PHY actions. >> >> To clear outstanding timestamp memory, the driver must read the >> timestamps. >> However, naively doing this as part of ice_ptp_reset_ts_memory() is >> problematic. When reading the timestamp index, hardware kicks off a >> chain of actions including clearing the ready bitmap index, and >> decrementing an internal counter if the timestamp index was marked >> as valid. >> >> This can potentially leave the internal hardware counter out of sync >> with the actual number of timestamps. This occurs because the >> PHY_REG_TX_MEMORY_STATUS region is not zero-initialized when the >> device boots up. Instead, it is filled with garbage. On a cold power >> on, attempts to read the stale data result in the hardware >> triggering a counter decrement for a timestamp that never happened. >> This underflows the counter, and prevents new timestamp interrupts >> from being triggered for real timestamp requests. >> >> We must read the PHY_REG_TX_MEMORY_STATUS in order to clear stale >> timestamps. But doing so may cause a desync with the counter. To >> prevent issues, perform this clearing always and only right before >> initiating a PHY soft reset. >> >> The soft reset will clear and reset the internal counter and the >> ready bitmap. The reads to PHY_REG_TX_MEMORY_STATUS will reset the >> region valid bits ensuring that no stale data is left behind. This >> combination ensures that we always have a clean slate with no stale >> data and with the counter properly reset to zero. >> >> If a read fails (i.e. due to a transient sideband queue failure) it >> is not treated as a fatal error. There is already a dynamic debug >> message for each read failure. Keep track of the total number of >> timestamp registers that fail for a given port and log a warning >> message indicating the total number of failures. Continuing is >> acceptable as clearing the memory is a precaution against faulty >> software. Correct software access won't read the index twice and >> won't read it at all except when it has already confirmed that the >> index is valid by reading ice_get_phy_tx_tstamp_ready(). >> >> Fixes: 3ec46e157c7f ("ice: perform PHY soft reset for E825C ports at >> initialization") >> Reviewed-by: Maciek Machnikowski >> Signed-off-by: Jacob Keller >> --- >> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 100 +++++++++++++++-- >> ----------- >> 1 file changed, 52 insertions(+), 48 deletions(-) >> >> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c >> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c >> index c8a67a307832..e1a5ff5793d1 100644 >> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c >> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c >> @@ -737,24 +737,6 @@ static int ice_read_port_mem_eth56g(struct >> ice_hw *hw, u8 port, u16 offset, >> return ice_read_port_eth56g(hw, port, offset, val, >> ETH56G_PHY_MEM_PTP); } >> > > ... > >> return err; >> } >> >> @@ -1177,19 +1147,43 @@ static int >> ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) } >> >> /** >> - * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the >> port block >> + * ice_ptp_clear_tx_memory_status_eth56g - Reset one port's Tx >> + timestamp memory >> * @hw: pointer to the HW struct >> + * @port: port number to clear >> + * >> + * Fully reset a single PHY port's Tx timestamp memory. Per the PHY >> + spec, the >> + * only way to clear a timestamp valid bit (and its read-only >> + ts_memory_status >> + * bit) is to read the timestamp memory location, so read every >> entry >> + for the >> + * port (two 32-bit reads each). This discards all timestamp data >> on >> + the port, >> + * so it must only be used for a full reset; callers that must >> preserve >> + * in-flight timestamps clear individual indices via >> ice_clear_phy_tstamp(). >> + * >> + * Due to interactions with an internal HW counter for the number >> of >> + * outstanding Tx timestamps, this *must* only be called as part of >> the >> + * ice_ptp_phy_soft_reset_eth56g() procedure. Otherwise, the >> internal >> + counter >> + * may become out of sync and prevent new timestamp interrupts. >> + * >> + * Failure to read a given index (i.e. due to a transient sideband >> + queue >> + * failure) is not considered fatal as the PHY port is about to be >> soft reset. >> + * While the soft reset does not clear the timestamp memory, >> software >> + * shouldn't be reading the timestamp memory without already >> knowing it >> + is >> + * valid via ice_get_phy_tx_tstamp_ready(), and this sweep is just >> + * a precaution to ensure the memory is in a known state. >> */ >> -static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) >> +static void ice_ptp_clear_tx_memory_status_eth56g(struct ice_hw >> *hw, u8 >> +port) >> { >> - unsigned int port; >> + int err, failed = 0; >> + u8 idx; >> >> - for (port = 0; port < hw->ptp.num_lports; port++) { >> - ice_write_ptp_reg_eth56g(hw, port, >> PHY_REG_TX_MEMORY_STATUS_L, >> - 0); >> - ice_write_ptp_reg_eth56g(hw, port, >> PHY_REG_TX_MEMORY_STATUS_U, >> - 0); >> + for (idx = 0; idx < INDEX_PER_PORT; idx++) { >> + err = ice_clear_ptp_tstamp_eth56g(hw, port, idx); >> + if (err) >> + failed++; >> } >> + >> + if (failed) >> + dev_warn(ice_hw_to_dev(hw), "Failed to clear %d PHY >> timestamp registers for port %u\n", >> + port, failed); > Failed, port arguments looks like swaped. > Yep. Will fix. > > Reviewed-by: Aleksandr Loktionov