From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jonathan Toppins Date: Thu, 07 May 2015 12:57:46 -0400 Subject: [Intel-wired-lan] [PATCH v1 net-next 1/2] igb: add PHY support for Broadcom 5461S In-Reply-To: References: <1429302240-654-1-git-send-email-jtoppins@cumulusnetworks.com> Message-ID: <554B998A.9010001@cumulusnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: intel-wired-lan@osuosl.org List-ID: On 5/7/15 12:18 PM, Tim Harvey wrote: > On Fri, Apr 17, 2015 at 1:23 PM, Jonathan Toppins > wrote: >> From: Alan Liebthal >> >> The Quanta LY8 Ethernet management port uses a Broadcom 5461S chip for >> the PHY layer. This adds support for this PHY to the Intel igb driver. >> >> Signed-off-by: Alan Liebthal >> Signed-off-by: Jonathan Toppins >> --- > >> --- a/drivers/net/ethernet/intel/igb/e1000_phy.c >> +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c >> @@ -148,6 +148,13 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) >> * Control register. The MAC will take care of interfacing with the >> * PHY to retrieve the desired data. >> */ >> + if (phy->type == e1000_phy_bcm5461s) { >> + mdic = rd32(E1000_MDICNFG); >> + mdic &= ~E1000_MDICNFG_PHY_MASK; >> + mdic |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); >> + wr32(E1000_MDICNFG, mdic); >> + } >> + >> mdic = ((offset << E1000_MDIC_REG_SHIFT) | >> (phy->addr << E1000_MDIC_PHY_SHIFT) | >> (E1000_MDIC_OP_READ)); >> @@ -204,6 +211,13 @@ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) >> * Control register. The MAC will take care of interfacing with the >> * PHY to retrieve the desired data. >> */ >> + if (phy->type == e1000_phy_bcm5461s) { >> + mdic = rd32(E1000_MDICNFG); >> + mdic &= ~E1000_MDICNFG_PHY_MASK; >> + mdic |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); >> + wr32(E1000_MDICNFG, mdic); >> + } >> + >> mdic = (((u32)data) | >> (offset << E1000_MDIC_REG_SHIFT) | >> (phy->addr << E1000_MDIC_PHY_SHIFT) | >> @@ -2509,3 +2523,68 @@ static s32 igb_set_master_slave_mode(struct e1000_hw *hw) >> >> return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); >> } > > Jonathan, > > Is this bcm5461s attached to an i210/i211? These changes look a lot > like some changes I'm trying to upstream to add support for i210/i211 > which require the phy address in the MDICNFG register. If this is the > case, then I think the right approach is to check for hw->mac.type = > e1000_i210/e1000_i211 and I can submit my patch for review. > > Regards, > > Tim > Hi Tim, The MAC in question are the ones integrated with Intel's Atom processor, I don't recall the series off hand, output of lspci and /proc/cpuinfo below. If you think your change may apply to this controller as well I would be more than happy to apply your change and test. Thanks, -Jon Supplementary Information. Processor info (8 processors total): root at qct-ly8-01:~# uname -a Linux qct-ly8-01 3.2.60-1+deb7u1+cl2.5+1 #3.2.60-1+deb7u1+cl2.5+1 SMP Mon Apr 13 23:18:31 PDT 2015 x86_64 GNU/Linux root at qct-ly8-01:~# cat /proc/cpuinfo | grep "processor" | wc -l 8 root at qct-ly8-01:~# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 77 model name : Intel(R) Atom(TM) CPU C2758 @ 2.40GHz stepping : 8 microcode : 0x11d cpu MHz : 2400.191 cache size : 1024 KB physical id : 0 siblings : 8 core id : 0 cpu cores : 8 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 11 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch arat epb dtherm tpr_shadow vnmi flexpriority ept vpid smep erms bogomips : 4800.38 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: ...trimmed... The PCI info for the controller: root at qct-ly8-01:~# lspci -vvx -s 00:14.0 00:14.0 Ethernet controller: Intel Corporation Device 1f41 (rev 03) Subsystem: Intel Corporation Device 1f41 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-