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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767630245; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=46dE8wQn1HVL0x3WTf36oZBc8LAD4VTY8ItMtpTUnY8=; b=Mfrlad7tbe4J0qLdqN7oubqgss9UKy/WMdvFp+zdFF6AuzVsi7MDwKfMY94MnD5IaZ/Jke aFdRDw1+AQnk/lzCS3pbPrCCZO4AZAZFMiS8yMFWm/rfIDsMAoME6ddSnnFtbogUjAGH2W si6W14DBfbQoE+tyrNO1Bb4E0kfiCiM= X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (1024-bit key, unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=Mfrlad7t Subject: Re: [Intel-wired-lan] [PATCH RFC net-next 01/13] dt-bindings: net: ethernet-controller: Add DPLL pin properties X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dumazet , Tony Nguyen , Horatiu Vultur , Leon Romanovsky , Alexander Lobakin , linux-rdma@vger.kernel.org, Przemek Kitszel , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, Jakub Kicinski , Paolo Abeni , devicetree@vger.kernel.org, Conor Dooley , Jiri Pirko , Richard Cochran , Prathosh Satish , Willem de Bruijn , Vadim Fedorenko , netdev@vger.kernel.org, Mark Bloch , linux-kernel@vger.kernel.org, Tariq Toukan , Andrew Lunn , Stefan Wahren , Simon Horman , Jonathan Lemon , Krzysztof Kozlowski , Saeed Mahameed , "David S. Miller" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On 12/17/25 1:49 AM, Rob Herring wrote: > On Thu, Dec 11, 2025 at 08:56:52PM +0100, Andrew Lunn wrote: >> On Thu, Dec 11, 2025 at 08:47:44PM +0100, Ivan Vecera wrote: >>> Ethernet controllers may be connected to DPLL (Digital Phase Locked Loop) >>> pins for frequency synchronization purposes, such as in Synchronous >>> Ethernet (SyncE) configurations. >>> >>> Add 'dpll-pins' and 'dpll-pin-names' properties to the generic >>> ethernet-controller schema. This allows describing the physical >>> connections between the Ethernet controller and the DPLL subsystem pins >>> in the Device Tree, enabling drivers to request and manage these >>> resources. >> >> Please include a .dts patch in the series which actually makes use of >> these new properties. > > Actually, first you need a device (i.e. a specific ethernet > controller bindings) using this and defining the number of dpll-pins > entries and the names. The goal of this patch is to define properties that allow referencing dpll pins from other devices. I included it in this series to allow implementing helpers that use the property names defined in the schema. This series implements the dpll pin consumer in the ice driver. This is usually present on ACPI platforms, so the properties are stored in _DSD ACPI nodes. Although I don't have a DT user right now, isn't it better to define the schema now? Thinking about this further, consumers could be either an Ethernet controller (where the PHY is not exposed and is driven directly by the NIC driver) or an Ethernet PHY. For the latter case (Ethernet PHY), I have been preparing a similar implementation for the Micrel phy driver (lan8814) on the Microchip EDS2 board (pcb8385). Unfortunately, the DTS is not upstreamed yet [1], so I cannot include the necessary bindings here. Since there can be multiple consumer types (Ethernet controller or PHY), would it be better to define a dpll-pin-consumer.yaml schema instead (similar to mux-consumer)? Thanks for the advice, Ivan [1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=1031294&state=*