From: "Neftin, Sasha" <sasha.neftin@intel.com>
To: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>,
<intel-wired-lan@osuosl.org>, <vinicius.gomes@intel.com>
Cc: christopher.s.hall@intel.com, anthony.l.nguyen@intel.com
Subject: Re: [Intel-wired-lan] [PATCH net v1] igc: Fix PPS delta between two synchronized end-points
Date: Wed, 14 Dec 2022 11:15:53 +0200 [thread overview]
Message-ID: <75444c43-11ae-6994-8205-07f8f0d21068@intel.com> (raw)
In-Reply-To: <20221214081038.1720-1-muhammad.husaini.zulkifli@intel.com>
On 12/14/2022 10:10, Muhammad Husaini Zulkifli wrote:
> From: Christopher S Hall <christopher.s.hall@intel.com>
>
> This patch fix the pulse per second output delta between
> two synchronized end-points.
>
> Based on Intel Discrete I225 Software User Manual Section
> 4.2.15 TimeSync Auxiliary Control Register, ST0[Bit 4] and
> ST1[Bit 7] must be set to ensure that clock output will be
> toggles based on frequency value defined. This is to ensure
> that output of the PPS is aligned with the clock.
>
> How to test:
>
> 1) Running time synchronization on both end points.
> Ex: ptp4l --step_threshold=1 -m -f gPTP.cfg -i <interface name>
>
> 2) Configure PPS output using below command for both end-points
> Ex: SDP0 on I225 REV4 SKU variant
>
> ./testptp -d /dev/ptp0 -L 0,2
> ./testptp -d /dev/ptp0 -p 1000000000
>
> 3) Measure the output using analyzer for both end-points
>
> Fixes: 87938851b6ef ("igc: enable auxiliary PHC functions for the i225")
> Signed-off-by: Christopher S Hall <christopher.s.hall@intel.com>
> Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
> ---
> drivers/net/ethernet/intel/igc/igc_defines.h | 2 ++
> drivers/net/ethernet/intel/igc/igc_ptp.c | 10 ++++++----
> 2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
> index a7b22639cfcd..e9747ec5ac0b 100644
> --- a/drivers/net/ethernet/intel/igc/igc_defines.h
> +++ b/drivers/net/ethernet/intel/igc/igc_defines.h
> @@ -475,7 +475,9 @@
> #define IGC_TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
> #define IGC_TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
> #define IGC_TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
> +#define IGC_TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
> #define IGC_TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
> +#define IGC_TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
> #define IGC_TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
> #define IGC_TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
> #define IGC_TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
> diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c
> index 8dbb9f903ca7..c34734d432e0 100644
> --- a/drivers/net/ethernet/intel/igc/igc_ptp.c
> +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c
> @@ -322,7 +322,7 @@ static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
> ts = ns_to_timespec64(ns);
> if (rq->perout.index == 1) {
> if (use_freq) {
> - tsauxc_mask = IGC_TSAUXC_EN_CLK1;
> + tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
> tsim_mask = 0;
> } else {
> tsauxc_mask = IGC_TSAUXC_EN_TT1;
> @@ -333,7 +333,7 @@ static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
> freqout = IGC_FREQOUT1;
> } else {
> if (use_freq) {
> - tsauxc_mask = IGC_TSAUXC_EN_CLK0;
> + tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
> tsim_mask = 0;
> } else {
> tsauxc_mask = IGC_TSAUXC_EN_TT0;
> @@ -347,10 +347,12 @@ static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
> tsauxc = rd32(IGC_TSAUXC);
> tsim = rd32(IGC_TSIM);
> if (rq->perout.index == 1) {
> - tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
> + tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
> + IGC_TSAUXC_ST1);
> tsim &= ~IGC_TSICR_TT1;
> } else {
> - tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
> + tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
> + IGC_TSAUXC_ST0);
> tsim &= ~IGC_TSICR_TT0;
> }
> if (on) {
Acked-by: Sasha Neftin <sasha.neftin@intel.com>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
next prev parent reply other threads:[~2022-12-14 9:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-14 8:10 [Intel-wired-lan] [PATCH net v1] igc: Fix PPS delta between two synchronized end-points Muhammad Husaini Zulkifli
2022-12-14 9:15 ` Neftin, Sasha [this message]
2023-01-01 11:29 ` naamax.meir
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=75444c43-11ae-6994-8205-07f8f0d21068@intel.com \
--to=sasha.neftin@intel.com \
--cc=anthony.l.nguyen@intel.com \
--cc=christopher.s.hall@intel.com \
--cc=intel-wired-lan@osuosl.org \
--cc=muhammad.husaini.zulkifli@intel.com \
--cc=vinicius.gomes@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox