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02 Apr 2026 16:48:36 -0700 X-CSE-ConnectionGUID: tjSrim2+TJqzeTDkrUgoWA== X-CSE-MsgGUID: TiOtLPiUTV+8RW4wpIPixQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,156,1770624000"; d="scan'208";a="227361270" Received: from vcostago-desk1.jf.intel.com (HELO vcostago-desk1) ([10.88.27.144]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 16:48:36 -0700 From: Vinicius Costa Gomes To: Bob Van Valzah , Vadim Fedorenko Cc: intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com, netdev@vger.kernel.org, julianstj@fb.com, jeff@jeffgeerling.com, Lasse Johnsen , Ian Gough In-Reply-To: References: <65977d5b-16eb-418c-995e-6a918f67707a@linux.dev> Date: Thu, 02 Apr 2026 16:48:35 -0700 Message-ID: <874ilsyld8.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775173717; x=1806709717; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version:content-transfer-encoding; bh=y95f5QlYUMwAz4Mebn4afYMRuQzmkG7xApZVnf6syFs=; b=GSq0ahLNpfMbvubdL55KmhPPGhc405RU53Vrqn8nQmu9t6kSCVn7xROx GoSNcBuBs+dJaoA3G4AyHKEeteHJnDVJ248WJweLZUQKMPZzUsOW7HnZF WPII6Qkaoaux5DIRPmiu8RunmgjfoDf5U2rhYBJGPuDBNVxFRA2rTwYre 5RyOujX1u5cQmk6Sc/oNWiU4UCglIt7ClfRN984lURQ3Jc7xURuIw5dPT Neg5XrIh83tDRV0ZzMNqkv5YIg0+7n8O947sFqmhcmoNUYdxTaaHBvOL+ mz3q4ATrig2+lOnZQRqkXggaq0JejI+cj8Ijx5HLZOIN04MtYb3LpfQjM Q==; X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=GSq0ahLN Subject: Re: [Intel-wired-lan] [PATCH] igc: fix Tx timestamp timeout caused by unlocked TIMINCA write in adj fine] X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Hi, Bob Van Valzah writes: > Vadim, > > Thanks for the feedback on our first patch. We've spent more time in > the lab studying the igc TX timestamp behavior under stress. We > understand the failure modes much better now. > > You were right that ptp_tx_lock was the wrong lock =E2=80=94 it guards th= e TX > queue, not the timing registers. You suggested tmreg_lock instead. We > tested tmreg_lock alone (v2) and found it doesn't fix the bug: it appears > that the race is between the software TIMINCA write and the hardware=E2= =80=99s > asynchronous TX timestamp capture pipeline, not between two software thre= ads. > tmreg_lock serializes software register accesses but can't prevent the ha= rdware > from reading TIMINCA at the instant software writes it. > > Our v3 patch (attached) takes tmreg_lock as you suggested, and > additionally disables TX timestamping in hardware via TSYNCTXCTL around > the TIMINCA write. This prevents the hardware from starting new > timestamp captures during the rate change: > > spin_lock_irqsave(&igc->tmreg_lock, flags); > txctl =3D rd32(IGC_TSYNCTXCTL); > wr32(IGC_TSYNCTXCTL, txctl & ~IGC_TSYNCTXCTL_ENABLED); > wr32(IGC_TIMINCA, inca); > wr32(IGC_TSYNCTXCTL, txctl); > spin_unlock_irqrestore(&igc->tmreg_lock, flags); > I sent, a couple of days ago, the link to your report to our hardware folks, waiting for them to take a look. I think that this workaround, even if incomplete, will be interesting to them as well. Again, thanks for the detailed report. Cheers, --=20 Vinicius