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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1765744939; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7dtrcaVLTNzNgFmQjfOcQvmiNkCId0/CKPWI6nsR8CY=; b=TKu7tQ/wGInnG+D0xTmQcvREJEdy9x55z1zpZ/wvuQE9Bi+i0ze9Cglsotps3vDFj5cN+g YnMdTQvMBanRi/Wn3/7L5VmTSzekiXLK29WVQHlxl0hN+Jl3OBJnhP5BX9K62I3VeWCkay FITi+GAMZxt6hk/rjAazQuF63pDsXYI= X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (1024-bit key, unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=TKu7tQ/w Subject: Re: [Intel-wired-lan] [PATCH RFC net-next 01/13] dt-bindings: net: ethernet-controller: Add DPLL pin properties X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dumazet , Tony Nguyen , Rob Herring , Leon Romanovsky , Alexander Lobakin , linux-rdma@vger.kernel.org, Przemek Kitszel , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, Jakub Kicinski , Paolo Abeni , devicetree@vger.kernel.org, Conor Dooley , Jiri Pirko , Richard Cochran , Prathosh Satish , Willem de Bruijn , Vadim Fedorenko , netdev@vger.kernel.org, Mark Bloch , linux-kernel@vger.kernel.org, Tariq Toukan , Andrew Lunn , Stefan Wahren , Simon Horman , Jonathan Lemon , Krzysztof Kozlowski , Saeed Mahameed , "David S. Miller" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On 12/11/25 8:56 PM, Andrew Lunn wrote: > On Thu, Dec 11, 2025 at 08:47:44PM +0100, Ivan Vecera wrote: >> Ethernet controllers may be connected to DPLL (Digital Phase Locked Loop) >> pins for frequency synchronization purposes, such as in Synchronous >> Ethernet (SyncE) configurations. >> >> Add 'dpll-pins' and 'dpll-pin-names' properties to the generic >> ethernet-controller schema. This allows describing the physical >> connections between the Ethernet controller and the DPLL subsystem pins >> in the Device Tree, enabling drivers to request and manage these >> resources. > > Please include a .dts patch in the series which actually makes use of > these new properties. > > Andrew Hi Andy, I would include this but the development of this series was done on Microchip EVB-LAN9668 EDS2 development board [1] and its DTS is not present in upstream tree. The base DTS for this board is at vendor's github repo [2]. The second development environment was/is ACPI based Intel GNR-D platform and the goal is to use unified fwnode API so ACPI is providing _DSD nodes to specify dpll-pin-names and dpll-names properties. Ivan [1] https://www.microchip.com/en-us/development-tool/ev83e85a [2] https://github.com/microchip-ung/linux/blob/bsp-6.12-2025/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts