Re: [Intel-wired-lan] [PATCH net-next v6 4/4] ice: Add txbalancing devlink param

[Tony Nguyen <anthony.l.nguyen@intel.com>]

On 7/20/2022 7:40 AM, Michal Wilczynski wrote:
> From: Lukasz Czapnik <lukasz.czapnik@intel.com>
> 
> It was observed that Tx performance was inconsistent across all queues
> and/or VSIs and that it was directly connected to existing 9-layer
> topology of the Tx scheduler.
> 
> Introduce new private devlink param - txbalance. This paramerer gives user

s/paramerer/parameter

> flexibility to choose the 5-layer transmit scheduler topology which helps
> to smooth out the transmit performance.
> 
> Allowed parameter values are true for enabled and false for disabled.

Please document these in Documentation/networking/devlink/ice.rst

> Example usage:
> 
> Show:
> devlink dev param show pci/0000:4b:00.0 name txbalancing
> pci/0000:4b:00.0:
>    name txbalancing type driver-specific
>      values:
>        cmode permanent value true
> 
> Set:
> devlink dev param set pci/0000:4b:00.0 name txbalancing value true cmode
> permanent
> 
> Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
> Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>

<snip>

> +/**
> + * ice_devlink_txbalance_get - Get txbalance parameter
> + * @devlink: pointer to the devlink instance
> + * @id: the parameter ID to set
> + * @ctx: context to store the parameter value
> + *
> + * Returns zero on success and negative value on failure.
> + */
> +static int ice_devlink_txbalance_get(struct devlink *devlink, u32 id,
> +				     struct devlink_param_gset_ctx *ctx)

nit: Can you use GNU style on these

static int
ice_devlink_txbalance_get(...)


> +{
> +	struct ice_pf *pf = devlink_priv(devlink);
> +	struct device *dev = ice_pf_to_dev(pf);
> +	int status;
> +
> +	status = ice_get_tx_topo_user_sel(pf, &ctx->val.vbool);
> +	if (status) {
> +		dev_warn(dev, "Failed to read Tx Scheduler Tree - User Selection data from flash\n");
> +		return -EIO;
> +	}
> +
> +	return 0;
> +}
> +

As well as the lkp reported issues[1]

[1] 
https://lore.kernel.org/intel-wired-lan/202207210108.7ZpVcgDQ-lkp@intel.com/
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