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[213.179.129.39]) by smtp.gmail.com with ESMTPSA id b7-20020a5d45c7000000b003141a3c4353sm460558wrs.30.2023.06.28.23.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 23:14:26 -0700 (PDT) Date: Thu, 29 Jun 2023 08:14:25 +0200 From: Jiri Pirko To: "Kubalewski, Arkadiusz" Message-ID: References: <20230609121853.3607724-1-arkadiusz.kubalewski@intel.com> <20230609121853.3607724-9-arkadiusz.kubalewski@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=resnulli-us.20221208.gappssmtp.com; s=20221208; t=1688019267; x=1690611267; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=BxPmChzKXR1dj/ko+9tzcHvICaNxDCij9PscVU1CwGY=; b=g4spu/YTypGbdobXCPpsNMEE7fZgSTh6dwO8ck/RlyJzKG32ec8qbcH4voInoYNI6o nG6/zJ1n82WItH1lu3qQCRFI8uw3L8ph8dhnODO74Jobt9mAAC6aVPmcAOEeHa3CijaY GQ0EQQTgLWtAzMyQV8sZkz9pP1Q5sB+jGzX0IRtVzmIH7vRZDqd7kAqk/QYf3QTa8aEJ QSuo/h0rl0fcrDEeomgjT4HhlbHIS1Bzm651nwZXtQyAM08WdVMOLO0uppwo8McOoT1j 8CGh366oXSh0q2wYy6HTFoOLtXKgeVtSm3qpnqhqbheagjwO+/UJVS4tnevaSr7XLabv Rrig== X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=resnulli-us.20221208.gappssmtp.com header.i=@resnulli-us.20221208.gappssmtp.com header.a=rsa-sha256 header.s=20221208 header.b=g4spu/YT Subject: Re: [Intel-wired-lan] [RFC PATCH v8 08/10] ice: implement dpll interface to control cgu X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "geert+renesas@glider.be" , "mst@redhat.com" , "razor@blackwall.org" , "phil@nwl.cc" , "javierm@redhat.com" , "edumazet@google.com" , "benjamin.tissoires@redhat.com" , "Nguyen, Anthony L" , "netdev@vger.kernel.org" , "linux-clk@vger.kernel.org" , "lucien.xin@gmail.com" , "leon@kernel.org" , "corbet@lwn.net" , "linux-rdma@vger.kernel.org" , "masahiroy@kernel.org" , "linux-doc@vger.kernel.org" , "Brandeburg, Jesse" , "vadfed@meta.com" , "intel-wired-lan@lists.osuosl.org" , "airlied@redhat.com" , "vadfed@fb.com" , "pabeni@redhat.com" , "ricardo.canuelo@collabora.com" , "arnd@arndb.de" , "idosch@nvidia.com" , "richardcochran@gmail.com" , "claudiajkang@gmail.com" , "kuniyu@amazon.com" , "jacek.lawrynowicz@linux.intel.com" , "liuhangbin@gmail.com" , "kuba@kernel.org" , "nicolas.dichtel@6wind.com" , "linux-arm-kernel@lists.infradead.org" , "axboe@kernel.dk" , "sj@kernel.org" , "vadim.fedorenko@linux.dev" , "linux@zary.sk" , "gregkh@linuxfoundation.org" , "ogabbay@kernel.org" , "nipun.gupta@amd.com" , "linux-kernel@vger.kernel.org" , "andy.ren@getcruise.com" , "tzimmermann@suse.de" , "jonathan.lemon@gmail.com" , "M, Saeed" , "davem@davemloft.net" , "Olech, Milena" , "hkallweit1@gmail.com" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Wed, Jun 21, 2023 at 02:29:59PM CEST, jiri@resnulli.us wrote: >Mon, Jun 19, 2023 at 10:34:12PM CEST, arkadiusz.kubalewski@intel.com wrote: >>>From: Jiri Pirko >>>Sent: Saturday, June 10, 2023 6:37 PM >>> >>>Fri, Jun 09, 2023 at 02:18:51PM CEST, arkadiusz.kubalewski@intel.com wrote: >>> >>>[...] >>> >>> >>>>+static int ice_dpll_mode_get(const struct dpll_device *dpll, void *priv, >>>>+ enum dpll_mode *mode, >>>>+ struct netlink_ext_ack *extack) >>>>+{ >>>>+ *mode = DPLL_MODE_AUTOMATIC; >>> >>>I don't understand how the automatic mode could work with SyncE. The >>>There is one pin exposed for one netdev. The SyncE daemon should select >>>exacly one pin. How do you achieve that? >>>Is is by setting DPLL_PIN_STATE_SELECTABLE on the pin-netdev you want to >>>select and DPLL_PIN_STATE_DISCONNECTED on the rest? >>> >>> >>>[...] >> >>AUTOMATIC mode autoselects highest priority valid signal. >>As you have pointed out, for SyncE selection, the user must be able to manually >>select a pin state to enable recovery of signal from particular port. >> >>In "ice" case there are 2 pins for network PHY clock signal recovery, and both >>are parent pins (MUX-type). There are also 4 pins assigned to netdevs (one per >>port). Thus passing a signal from PHY to the pin is done through the MUX-pin, >>by selecting proper state on pin-parent pair (where parent pins is highest prio >>pin on dpll). > >Could you show me some examples please? Arkadiusz, could you please reply to this? Thanks! > > >> >>Thank you! >>Arkadiusz _______________________________________________ Intel-wired-lan mailing list Intel-wired-lan@osuosl.org https://lists.osuosl.org/mailman/listinfo/intel-wired-lan