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[213.179.129.39]) by smtp.gmail.com with ESMTPSA id lz1-20020a170906fb0100b0099b5a71b0bfsm17185248ejb.94.2023.10.02.08.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 08:04:20 -0700 (PDT) Date: Mon, 2 Oct 2023 17:04:19 +0200 From: Jiri Pirko To: "Kubalewski, Arkadiusz" Message-ID: References: <20230927092435.1565336-1-arkadiusz.kubalewski@intel.com> <20230927092435.1565336-4-arkadiusz.kubalewski@intel.com> <4018c0b0-b288-ff60-09be-7ded382f4a82@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=resnulli-us.20230601.gappssmtp.com; s=20230601; t=1696259061; x=1696863861; darn=lists.osuosl.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=QvJNZIXntn7YAjmySz9d+Qe4GmC8D4FRYo7VLjmUagg=; b=JmoP/NctLC1z0c3PJ5tdmzReKb1Z4OJWehgvng4kyheqrultAr2US6rbVp9wcZGZ/L ZisgA1YRAcgHTio69MXlwxzJxncPJ2t6ltfAVFcCGSSFe2nV4Z5I10K4wWC5/3opKzfQ TEci34eA/wgNAYKTt/9FSxHTGaK/QcIYrB+9EyZvSKoh0sk17zxq+H2XjjQtr/Rf/Hqb Y1UN3efDilgjSye60XqH45fsOaGlXnWUCuE/qkezEXJyb5yCki44EvMYvpjcy9MzJfgR 2bXQUv8mRw1t5pnSfUSSpDISsJsqoefWUcvesH3OtVBuu+V9odH1dEiZ1fXtWHtpfTaw NWzA== X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (2048-bit key) header.d=resnulli-us.20230601.gappssmtp.com header.i=@resnulli-us.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=JmoP/Nct Subject: Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vadim Fedorenko , "corbet@lwn.net" , "netdev@vger.kernel.org" , "linux-doc@vger.kernel.org" , "Brandeburg, Jesse" , "Nguyen, Anthony L" , "intel-wired-lan@lists.osuosl.org" , "kuba@kernel.org" , "pabeni@redhat.com" , "davem@davemloft.net" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com wrote: >>From: Vadim Fedorenko >>Sent: Wednesday, September 27, 2023 8:09 PM >> >>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote: >>> Add callback op (get) for pin-dpll phase-offset measurment. >>> Add callback ops (get/set) for pin signal phase adjustment. >>> Add min and max phase adjustment values to pin proprties. >>> Invoke get callbacks when filling up the pin details to provide user >>> with phase related attribute values. >>> Invoke phase-adjust set callback when phase-adjust value is provided for >>> pin-set request. >>> >>> Signed-off-by: Arkadiusz Kubalewski >> >>[...] >> >>> +static int >>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr >>> *phase_adj_attr, >>> + struct netlink_ext_ack *extack) >>> +{ >>> + struct dpll_pin_ref *ref; >>> + unsigned long i; >>> + s32 phase_adj; >>> + int ret; >>> + >>> + phase_adj = nla_get_s32(phase_adj_attr); >>> + if (phase_adj > pin->prop->phase_range.max || >>> + phase_adj < pin->prop->phase_range.min) { >>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported"); >>> + return -EINVAL; >>> + } >>> + xa_for_each(&pin->dpll_refs, i, ref) { >>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref); >>> + struct dpll_device *dpll = ref->dpll; >>> + >>> + if (!ops->phase_adjust_set) >>> + return -EOPNOTSUPP; >> >>I'm thinking about this part. We can potentially have dpll devices with >>different expectations on phase adjustments, right? And if one of them >>won't be able to adjust phase (or will fail in the next line), then >>netlink will return EOPNOTSUPP while _some_ of the devices will be >>adjusted. Doesn't look great. Can we think about different way to apply >>the change? >> > >Well makes sense to me. > >Does following makes sense as a fix? >We would call op for all devices which has been provided with the op. >If device has no op -> add extack error, continue Is it real to expect some of the device support this and others don't? Is it true for ice? If not, I would got for all-or-nothing here. >If device fails to set -> add extack error, continue >Function always returns 0. > >Thank you! >Arkadiusz > >> >>> + ret = ops->phase_adjust_set(pin, >>> + dpll_pin_on_dpll_priv(dpll, pin), >>> + dpll, dpll_priv(dpll), phase_adj, >>> + extack); >>> + if (ret) >>> + return ret; >>> + } >>> + __dpll_pin_change_ntf(pin); >>> + >>> + return 0; >>> +} >>> + _______________________________________________ Intel-wired-lan mailing list Intel-wired-lan@osuosl.org https://lists.osuosl.org/mailman/listinfo/intel-wired-lan