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[194.45.78.10]) by smtp.gmail.com with ESMTPSA id p9-20020a170906838900b009497509fda3sm2503755ejx.40.2023.04.14.07.18.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Apr 2023 07:18:41 -0700 (PDT) From: Jesper Dangaard Brouer X-Google-Original-From: Jesper Dangaard Brouer Message-ID: Date: Fri, 14 Apr 2023 16:18:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 To: David Laight , "'Song, Yoong Siang'" , Jesper Dangaard Brouer , "Brandeburg, Jesse" , "Nguyen, Anthony L" , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , "Fijalkowski, Maciej" , Vedang Patel , "Joseph, Jithu" , Andre Guedes , Stanislav Fomichev , "Keller, Jacob E" References: <20230414020915.1869456-1-yoong.siang.song@intel.com> <8214fb10-8caa-4418-8435-85b6ac27b69e@redhat.com> <4dc9ea6c77ff49138a49d7f73f7301fd@AcuMS.aculab.com> In-Reply-To: <4dc9ea6c77ff49138a49d7f73f7301fd@AcuMS.aculab.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1681481925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sX4uJHc1E4iUI/WZObcqqEuHDDY4tzWA7F305PZUU8s=; b=WjtV6vZ5IsECtSF9Rad7AejqERNrFJHaWDg4MxPjslCkLwysRL1fZehBSkw1eZx/FZygJ/ 5fQwzA0U/eplBOt6z3chkwL3JxR1lx6J5OFiPPWmMKFgcguyBbsjQ/29M7+4VTvUCZZrup PqlVxeIdtQJWVxoN6JqgF6y9iIyG33E= X-Mailman-Original-Authentication-Results: smtp2.osuosl.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=WjtV6vZ5 Subject: Re: [Intel-wired-lan] [PATCH net v2 1/1] igc: read before write to SRRCTL register X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "xdp-hints@xdp-project.net" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "intel-wired-lan@lists.osuosl.org" , brouer@redhat.com, "bpf@vger.kernel.org" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On 14/04/2023 14.32, David Laight wrote: > From: Song, Yoong Siang >> Sent: 14 April 2023 12:16 > ... >>> I have checked Foxville manual for SRRCTL (Split and Replication Receive >>> Control) register and below GENMASKs looks correct. >>> >>>> -#define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ >>>> -#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ >>>> +#define IGC_SRRCTL_BSIZEPKT_MASK GENMASK(6, 0) >>>> +#define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ >>> >>> Shift due to 1 KB resolution of BSIZEPKT (manual field BSIZEPACKET) >> >> Ya, 1K = BIT(10), so need to shift right 10 bits. > > I bet the code would be easier to read if it did 'value / 1024u'. > The object code will be (much) the same. I agree. Code becomes more readable for humans and machine code will be the same. >>>> +#define IGC_SRRCTL_BSIZEHDRSIZE_MASK GENMASK(13, 8) >>>> +#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ >>> >>> This shift is suspicious, but as you inherited it I guess it works. >>> I did the math, and it happens to work, knowing (from manual) value is in 64 bytes >>> resolution. >> >> It is in 64 = BIT(6) resolution, so need to shift right 6 bits. >> But it start on 8th bit, so need to shift left 8 bits. >> Thus, total = shift left 2 bits. >> >> I didnt put the explanation into the header file because it is too lengthy >> and user can know from databook. Well, users usually don't have access to the databook (Programming Interface) PDF. Personally I have it, but I had to go though a lot of red-tape to get it (under Red Hat NDA). >> >> How do you feel on the necessary of explaining the shifting logic? > > Not everyone trying to grok the code will have the manual. > Even writing (8 - 6) will help. > Or (I think) if the value is in bits 13-8 in units of 64 then just: > ((value >> 8) & 0x1f) * 64 > gcc will do a single shift right and a mask 9at some point). > You might want some defines, but if they aren't used much > just comments that refer to the names in the manual/datasheet > can be enough. > After Alexander Lobakin opened my eyes for GENMASK, FIELD_PREP and FIELD_GET, I find that easier to read and work-with these kind of register value manipulations, see[1] include/linux/bitfield.h. It will also detect if the assigned value exceeds the mask (like David code handled via mask). (thx Alex) [1] https://elixir.bootlin.com/linux/v6.3-rc6/source/include/linux/bitfield.h#L14 So, instead of: srrctl |= IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT; I would write /* BSIZEHDR value in 64 bytes resolution */ srrctl |= FIELD_PREP(IGC_SRRCTL_BSIZEHDRSIZE_MASK, (IGC_RX_HDR_LEN / 64)); --Jesper _______________________________________________ Intel-wired-lan mailing list Intel-wired-lan@osuosl.org https://lists.osuosl.org/mailman/listinfo/intel-wired-lan