Re: [Intel-wired-lan] [PATCH iwl-net v3] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency

["Dahan, AvigailX" <avigailx.dahan@intel.com>]

On 18/03/2026 11:34, Dima Ruinskiy wrote:
> From: Vitaly Lifshits <vitaly.lifshits@intel.com>
> 
> On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware
> XTAL clock is incorrectly interpreted as 24 MHz instead of the actual
> 38.4 MHz. This causes the PHC to run significantly faster than system
> time, breaking PTP synchronization.
> 
> To mitigate this at runtime, measure PHC vs system time over ~1 ms using
> cross-timestamps. If the PHC increment differs from system time beyond
> the expected tolerance (currently >100 uSecs), reprogram TIMINCA for the
> 38.4 MHz profile and reinitialize the timecounter.
> 
> Tested on an affected system using phc_ctl:
> Without fix:
> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get
> clock time: 16.000541250 (expected ~10s)
> 
> With fix:
> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get
> clock time: 9.984407212 (expected ~10s)
> 
> Fixes: fb776f5d57ee ("e1000e: Add support for Tiger Lake")
> Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
> Co-developed-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
> Signed-off-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
> ---
> v3: fix cc.shift and wrap TIMINCA write in systim_lock
> v2: avoid resetting the systim and rephrase commit message
> v1: initial version
> ---
>   drivers/net/ethernet/intel/e1000e/netdev.c | 78 ++++++++++++++++++++++
>   1 file changed, 78 insertions(+)
> 

Tested-by: Avigail Dahan <avigailx.dahan@intel.com>