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Wed, 08 Apr 2026 05:44:59 -0400 X-MC-Unique: QqfLZcIANHqLSnK_0ttR4A-1 X-Mimecast-MFC-AGG-ID: QqfLZcIANHqLSnK_0ttR4A_1775641496 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id DD409195608D; Wed, 8 Apr 2026 09:44:55 +0000 (UTC) Received: from [10.44.48.188] (unknown [10.44.48.188]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A85A3300019F; Wed, 8 Apr 2026 09:44:49 +0000 (UTC) Message-ID: Date: Wed, 8 Apr 2026 11:44:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: Grzegorz Nitka , netdev@vger.kernel.org References: <20260402230626.3826719-1-grzegorz.nitka@intel.com> <20260402230626.3826719-5-grzegorz.nitka@intel.com> From: Ivan Vecera In-Reply-To: <20260402230626.3826719-5-grzegorz.nitka@intel.com> X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 X-Mimecast-MFC-PROC-ID: qy48aukMVew2cl4ikAb7gUNsbg3Yr8fSLDsxq8N93RY_1775641496 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775641503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fVByUgcVRV9cDGwBxu0qdLtCN/YmZ0vWbRv6xHT9zUI=; b=NB5wq1qaRbRqY8HA4Y+CJtQwDrA5CClK7RaKavM3IbaBN3RcBRuwA2NE5H9UI+cnKqQE3j B/MHblWSO+VGaULR5X4WxqBqEfypCnVCCFM07Y7CXuYw4MH0Qhxr37sFqa2mD+a0YC/ExC L3H1ODKU+oO8He9ZiHs3nW/J8vNdMcg= X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (1024-bit key, unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=NB5wq1qa Subject: Re: [Intel-wired-lan] [PATCH v5 net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vadim.fedorenko@linux.dev, kuba@kernel.org, jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com, richardcochran@gmail.com, donald.hunter@gmail.com, linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com, Aleksandr Loktionov , andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org, Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com, davem@davemloft.net Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" On 4/3/26 1:06 AM, Grzegorz Nitka wrote: > The SyncE_Ref pin may operate as either an active or inactive reference > depending on board design and system configuration. Some platforms need > to disable the SyncE reference dynamically (e.g., when selecting a > different recovered clock input). The hardware supports toggling this > pin, therefore advertise the STATE_CAN_CHANGE capability. > > Reviewed-by: Arkadiusz Kubalewski > Reviewed-by: Aleksandr Loktionov > Signed-off-by: Grzegorz Nitka > --- > drivers/dpll/zl3073x/prop.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c > index ac9d41d0f978..acd7061a741a 100644 > --- a/drivers/dpll/zl3073x/prop.c > +++ b/drivers/dpll/zl3073x/prop.c > @@ -215,6 +215,15 @@ struct zl3073x_pin_props *zl3073x_pin_props_get(struct zl3073x_dev *zldev, > > props->dpll_props.type = DPLL_PIN_TYPE_GNSS; > > + /* > + * The SyncE_Ref pin supports enabling/disabling dynamically. > + * Some platforms may choose to expose this through firmware > + * configuration later. For now, advertise this capability > + * universally since the hardware allows state toggling. > + */ > + props->dpll_props.capabilities |= > + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; > + > /* The output pin phase adjustment granularity equals half of > * the synth frequency count. > */ Reviewed-by: Ivan Vecera