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charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 30 Oct 2026 04:54:06 +0000 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 X-Archived-By: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [High] The primary default rule allocation still hardcodes X2 keys and un= masked reference indices, completely ignoring the X4 hardware profile for P= Fs and successful VF attempts. - [Medium] Caching device-specific hardware profile information in a global= static variable causes a data race across concurrent device instances. -- commit 0a14e92cf2754f6d4cb9d8447914740b55c1a43e Author: Ratheesh Kannoth octeontx2: cn20k: Respect NPC MCAM X2/X4 profile in flows and DFT alloc This commit updates the default CN20K NPC rule allocation and flow-install= =20 path to respect the active MCAM keyword width, dynamically selecting X2 or = X4=20 and masking reference indices accordingly. It caches the profile informatio= n=20 on the PF. > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driv= ers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > index 67dfbe5ca903f..15b3f29d60ee9 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > @@ -4467,11 +4467,18 @@ int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u1= 6 pcifunc) > * as NPC_DFT_RULE_PRIO - 1 (higher hw priority) > */ > req.contig =3D false; > - req.kw_type =3D NPC_MCAM_KEY_X2; > req.count =3D cnt; > req.hdr.pcifunc =3D pcifunc; > req.ref_prio =3D NPC_MCAM_LOWER_PRIO; > - req.ref_entry =3D eidx + 1; > + > + if (npc_priv.kw =3D=3D NPC_MCAM_KEY_X4) { > + req.kw_type =3D NPC_MCAM_KEY_X4; > + req.ref_entry =3D eidx & (npc_priv.bank_depth - 1); > + } else { > + req.kw_type =3D NPC_MCAM_KEY_X2; > + req.ref_entry =3D eidx; > + } > + Does the initial allocation attempt unconditionally hardcode X2 keys? Looking at the code just above this fallback path in npc_cn20k_dft_rules_alloc(), the primary allocation hardcodes the key type: req.contig =3D false; req.ref_prio =3D NPC_MCAM_HIGHER_PRIO; req.ref_entry =3D eidx; req.kw_type =3D NPC_MCAM_KEY_X2; ... ret =3D rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &req, &rsp); If this first attempt succeeds, VFs might incorrectly get assigned X2 rules on X4 silicon. Since PFs bypass the fallback path entirely if this fails, will PF default rule allocation fail completely on X4 profiles? [ ... ] > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > index 38cc539d724d8..5dd0591fed999 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > @@ -37,14 +37,13 @@ static void otx2_clear_ntuple_flow_info(struct otx2_n= ic *pfvf, struct otx2_flow_ > flow_cfg->max_flows =3D 0; > } > =20 > -static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, > - u16 *x4_slots) > +static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, u16 *x4_slots, = u8 *kw_type) > { > struct npc_get_pfl_info_rsp *rsp; > struct msg_req *req; > static struct { > bool is_set; > - bool is_x2; > + u8 kw_type; > u16 x4_slots; > } pfl_info; Does caching this profile information in a static structure cause a data race across concurrent device instances? The accesses to this shared cache are protected by mutex_lock(&pfvf->mbox.l= ock). Since this is a per-device instance lock, multiple network devices could concurrently acquire their own independent locks and read or write the shar= ed pfl_info structure. Could this lack of synchronization lead to torn reads, such as reading x4_s= lots as 0 if the compiler reorders the write to is_set before x4_slots? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260508034912.4082= 520-1-rkannoth@marvell.com?part=3D8