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Fri, 6 Nov 2026 20:53:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793998432; bh=wQATwTVtMocXdW6kCyhDIN9aoxU6AoFUXZw6XVltzVI=; h=From:Subject:Reply-To:To:In-Reply-To:References:Date; b=HxOkhfiZkSDbborlEnp3veiYpqr+Y/oqWg9XYL4gVczz2sVitdhXoFow+HG/rzlTk KLlxRNb37d1TIIaCyfzf6ADclnMt88eewr62JFU4lumIIHkGp6xkCt5Zyf1zjNTAIY Z8YKoWcA/BaCM4pk0RofJH2/fm7mQMI1asiJksQJ8cyMXdPLPtaHV8vORpRMwfaKYM HuAN9BAmX36TrjgkWW+tCzF4cepEMCfVaq54Q0RmsGX6jMB9dWWrzyG0GTs+4iEX6T LxNN4LX3Pzg6DoCeYyqbsEA00S23dREsILi71q7/WHakkjfYWWLclitDqfrLIX3OK8 iaS8D/hrUovrw== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH iwl-net] igb: Retry the D0 write of the i210 PLL workaround To: "Anthony Pighin" , intel-wired-lan@lists.osuosl.org In-Reply-To: <20261105205325.2624892-1-anthony.pighin@nokia.com> References: <20261105205325.2624892-1-anthony.pighin@nokia.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 06 Nov 2026 20:53:51 +0000 X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 X-Archived-By: Thank you for your contribution! Sashiko AI review found 2 potential issues to consider: - [Medium] igb: MMIO access while in D3hot after igb_set_d0_i210() fails - [Low] igb: __bitwise pci_power_t type mismatch in igb_set_d0_i210() -- commit f07d2c21ba2a41d9be32c940436c29816e2eedd2 Author: Anthony Pighin igb: Retry the D0 write of the i210 PLL workaround This commit adds igb_set_d0_i210() to retry transitioning the device from D3hot back to D0 during the i210 PLL errata workaround if the config write = is rejected while the root port reports link training. > diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/et= hernet/intel/igb/e1000_i210.c > index 784f9a7bcbed0..fad7cdfea197f 100644 > --- a/drivers/net/ethernet/intel/igb/e1000_i210.c > +++ b/drivers/net/ethernet/intel/igb/e1000_i210.c [ ... ] > @@ -812,6 +814,33 @@ s32 igb_init_nvm_params_i210(struct e1000_hw *hw) > return 0; > } > =20 > +static bool igb_set_d0_i210(struct e1000_hw *hw, u16 pci_word) > +{ > + struct igb_adapter *adapter =3D hw->back; > + u16 pmcsr; > + int i; > + > + pci_word &=3D ~PCI_PM_CTRL_STATE_MASK; > + pci_word |=3D PCI_D0; > + > + /* Some host controller drivers refuse config accesses while the root > + * port reports link training. The root port can report link training > + * while the device is in D3hot, so the write that requests D0 can be > + * refused. > + */ > + for (i =3D 0; i < 1000; i++) { > + igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); > + igb_read_pci_cfg(hw, E1000_PCI_PMCSR, &pmcsr); > + if (!PCI_POSSIBLE_ERROR(pmcsr) && > + (pmcsr & PCI_PM_CTRL_STATE_MASK) =3D=3D PCI_D0) > + return true; [Severity: Low] Does mixing PCI_D0 with u16 pci_word and (pmcsr & PCI_PM_CTRL_STATE_MASK) trigger Sparse warnings? PCI_D0 is a restricted __bitwise pci_power_t token rather than a raw PMCSR register value, so both the bitwise OR and the comparison degrade pci_power_t to an integer under Sparse. [ ... ] > @@ -866,8 +895,8 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw) > pci_word |=3D E1000_PCI_PMCSR_D3; > igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); > usleep_range(1000, 2000); > - pci_word &=3D ~E1000_PCI_PMCSR_D3; > - igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); > + if (!igb_set_d0_i210(hw, pci_word)) > + break; [Severity: Medium] If igb_set_d0_i210() fails, does breaking out of the loop still perform MMIO accesses while the device is stuck in D3hot? After the loop, igb_pll_workaround_i210() runs: drivers/net/ethernet/intel/igb/e1000_i210.c:igb_pll_workaround_i210() { ... igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0); /* restore MDICNFG setting */ wr32(E1000_MDICNFG, mdicnfg); return ret_val; } igb_write_phy_reg_82580() acquires the PHY semaphore and reads E1000_SWSM v= ia igb_rd32(), and igb_reset() also continues issuing MMIO accesses after init_hw() fails. Because the device is still in D3hot, readl() returns 0xffffffff, causing igb_rd32() to clear hw->hw_addr, report "PCIe link lost= ", and trigger a WARN(). --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261105205325.2624= 892-1-anthony.pighin@nokia.com?part=3D1