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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from IA0PR11MB7307.namprd11.prod.outlook.com (2603:10b6:208:437::10) by SA3PR11MB9487.namprd11.prod.outlook.com (2603:10b6:806:47e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Thu, 23 Oct 2025 09:34:00 +0000 Received: from IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843]) by IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843%6]) with mapi id 15.20.9253.011; Thu, 23 Oct 2025 09:34:00 +0000 Message-ID: <025360f0-1630-41a5-a38a-1f243e2ab1e8@intel.com> Date: Thu, 23 Oct 2025 15:03:53 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables To: Suraj Kandpal , , CC: , , , References: <20251015040817.3431297-1-suraj.kandpal@intel.com> <20251015040817.3431297-18-suraj.kandpal@intel.com> Content-Language: en-US From: "Murthy, Arun R" In-Reply-To: <20251015040817.3431297-18-suraj.kandpal@intel.com> Content-Type: text/plain; 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So we share > * them for both DP and FDI transports, allowing those ports to > @@ -1115,6 +1116,69 @@ static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = { > .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), > }; > > +/* DP1.4 */ > +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = { > + { .lt = { 1, 0, 0, 21, 0 } }, > + { .lt = { 1, 1, 0, 24, 3 } }, > + { .lt = { 1, 2, 0, 28, 7 } }, > + { .lt = { 0, 3, 0, 35, 13 } }, > + { .lt = { 1, 1, 0, 27, 0 } }, > + { .lt = { 1, 2, 0, 31, 4 } }, > + { .lt = { 0, 3, 0, 39, 9 } }, > + { .lt = { 1, 2, 0, 35, 0 } }, > + { .lt = { 0, 3, 0, 41, 7 } }, > + { .lt = { 0, 3, 0, 48, 0 } }, > +}; > + > +/* DP2.1 */ > +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = { > + { .lt = { 0, 0, 0, 48, 0 } }, > + { .lt = { 0, 0, 0, 43, 5 } }, > + { .lt = { 0, 0, 0, 40, 8 } }, > + { .lt = { 0, 0, 0, 37, 11 } }, > + { .lt = { 0, 0, 0, 33, 15 } }, > + { .lt = { 0, 0, 2, 46, 0 } }, > + { .lt = { 0, 0, 2, 42, 4 } }, > + { .lt = { 0, 0, 2, 38, 8 } }, > + { .lt = { 0, 0, 2, 35, 11 } }, > + { .lt = { 0, 0, 2, 33, 13 } }, > + { .lt = { 0, 0, 4, 44, 0 } }, > + { .lt = { 0, 0, 4, 40, 4 } }, > + { .lt = { 0, 0, 4, 37, 7 } }, > + { .lt = { 0, 0, 4, 33, 11 } }, > + { .lt = { 0, 0, 8, 40, 0 } }, > + { .lt = { 1, 0, 2, 26, 2 } }, > +}; > + > +/* eDp */ > +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = { > + { .lt = { 1, 0, 0, 12, 0 } }, > + { .lt = { 1, 1, 0, 13, 1 } }, > + { .lt = { 1, 2, 0, 15, 3 } }, > + { .lt = { 1, 3, 0, 19, 7 } }, > + { .lt = { 1, 1, 0, 14, 0 } }, > + { .lt = { 1, 2, 0, 16, 2 } }, > + { .lt = { 1, 3, 0, 21, 5 } }, > + { .lt = { 1, 2, 0, 18, 0 } }, > + { .lt = { 1, 3, 0, 22, 4 } }, > + { .lt = { 1, 3, 0, 26, 0 } }, > +}; > + > +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = { > + .entries = _xe3plpd_lt_trans_dp14, > + .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14), > +}; > + > +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = { > + .entries = _xe3plpd_lt_trans_uhbr, > + .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr), > +}; > + > +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = { > + .entries = _xe3plpd_lt_trans_edp, > + .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp), > +}; > + > bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) > { > return table == &tgl_combo_phy_trans_edp_hbr2_hobl; > @@ -1707,11 +1771,26 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder, > return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state)) > + return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries); > + else > + return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries); > +} > + > void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > { > struct intel_display *display = to_intel_display(encoder); > > - if (DISPLAY_VER(display) >= 14) { > + if (HAS_LT_PHY(display)) { > + encoder->get_buf_trans = xe3plpd_get_lt_buf_trans; > + } else if (DISPLAY_VER(display) >= 14) { > if (intel_encoder_is_c10phy(encoder)) > encoder->get_buf_trans = mtl_get_c10_buf_trans; > else > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > index 29a190390192..cec332090a20 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > @@ -50,6 +50,14 @@ struct dg2_snps_phy_buf_trans { > u8 post_cursor; > }; > > +struct xe3plpd_lt_phy_buf_trans { > + u8 txswing; > + u8 txswing_level; > + u8 pre_cursor; > + u8 main_cursor; > + u8 post_cursor; > +}; > + > union intel_ddi_buf_trans_entry { > struct hsw_ddi_buf_trans hsw; > struct bxt_ddi_buf_trans bxt; > @@ -57,6 +65,7 @@ union intel_ddi_buf_trans_entry { > struct icl_mg_phy_ddi_buf_trans mg; > struct tgl_dkl_phy_ddi_buf_trans dkl; > struct dg2_snps_phy_buf_trans snps; > + struct xe3plpd_lt_phy_buf_trans lt; > }; > > struct intel_ddi_buf_trans {