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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by PH7PR11MB7720.namprd11.prod.outlook.com (2603:10b6:510:2b3::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.14; Mon, 29 Dec 2025 05:30:12 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9456.013; Mon, 29 Dec 2025 05:30:12 +0000 Message-ID: <028319cb-b276-469f-8fad-4c5002b2ebc8@intel.com> Date: Mon, 29 Dec 2025 11:00:05 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] drm/i915/vdsc: Account for DSC slice overhead in intel_vdsc_min_cdclk() To: CC: , References: <20251223150826.2591182-1-ankit.k.nautiyal@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: Content-Type: text/plain; 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(Imre) >> >> Bspec:68912 >> Signed-off-by: Ankit Nautiyal >> --- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 35 ++++++++++++++++++++--- >> 1 file changed, 31 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index ad5fe841e4b3..5493082f30a7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -1050,15 +1050,40 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, >> drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); >> } >> >> +static >> +int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, >> + int pixel_rate, int htotal, >> + int dsc_horizontal_slices) >> +{ >> + int dsc_slice_bubbles; >> + u64 num; >> + >> + if (drm_WARN_ON(display->drm, !htotal)) >> + return pixel_rate; >> + >> + dsc_slice_bubbles = 14 * dsc_horizontal_slices; >> + num = mul_u32_u32(pixel_rate, (htotal + dsc_slice_bubbles)); >> + >> + return DIV_ROUND_UP_ULL(num, htotal); >> +} >> + >> int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) >> { >> struct intel_display *display = to_intel_display(crtc_state); >> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); >> + int htotal = crtc_state->hw.adjusted_mode.crtc_htotal; >> + int dsc_slices = crtc_state->dsc.slice_count; >> + int pixel_rate; >> int min_cdclk; >> >> if (!crtc_state->dsc.compression_enable) >> return 0; >> >> + pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display, >> + crtc_state->pixel_rate, >> + htotal, >> + dsc_slices); >> + >> /* >> * When we decide to use only one VDSC engine, since >> * each VDSC operates with 1 ppc throughput, pixel clock >> @@ -1066,7 +1091,7 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) >> * If there 2 VDSC engines, then pixel clock can't be higher than >> * VDSC clock(cdclk) * 2 and so on. >> */ >> - min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances); >> + min_cdclk = DIV_ROUND_UP(pixel_rate, num_vdsc_instances); >> >> if (crtc_state->joiner_pipes) { >> int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); >> @@ -1084,9 +1109,11 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) >> * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits >> */ >> int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; >> - int min_cdclk_bj = >> - (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * >> - pixel_clock) / (2 * bigjoiner_interface_bits); >> + int adjusted_pixel_rate = >> + intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock, >> + htotal, dsc_slices); >> + int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * >> + adjusted_pixel_rate) / (2 * bigjoiner_interface_bits); > The patch looks ok: > Reviewed-by: Imre Deak > > Fwiw: I suppose when calculating min_cdclk_bj instead of > fxp_q4_to_int_roundup() the x16 adjustment could be in the divider for > more precision and the division should round up not down. However neither > of these are related to your changes, they can be revised later. Agreed. I guess when this change started, we were not having the granularity of 1/16. I will add the suggested change with my other DSC cdclk series. Thanks for the review! Regards, Ankit > >> >> min_cdclk = max(min_cdclk, min_cdclk_bj); >> } >> -- >> 2.45.2 >>