[Intel-xe] LLC configurating, mmap and bo cache management questions

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

Hi,

We are working on adding xe support to ChromeOS minigbm and have a 
couple questions.

If I follow things correctly with xe mmap caching mode is fixed to 
object caching modes set at bo create. For framebuffers it will be WC 
and for the rest userspace can choose WB or WC via 
drm_xe_gem_create->cpu_caching. (Unless discrete, when WB cannot be used 
at all.)

AFAICT minigbm basically cares about two transition points. Lets call 
them CPU access begin and end.

1)
When a bo is mmapped it wants to invalidate the cache, which looks to be 
about making sure all GPU writes have landed to the backing store. In 
the i915 world that translates to the set_domain ioctl.

What is the uapi for this with xe, or it is somehow guaranteed to not be 
needed?

2)
When a bo is unmapped, or CPU access finished, it wants to flush the CPU 
caches. That is /almost/ completely a CPU operation, where it just needs 
to either clflush or invalidate the WC buffer respectively, if not the 
fact that clflush can be skipped on platforms with LLC.

I did not see an equivalent of an I915_PARAM_HAS_LLC in xe? Did I miss 
it or what it is the plan for querying this detail?

Regards,

Tvrtko