Re: [PATCH v3 05/11] drm/xe/bmg: Program an additional discrete-specific PAT setting

["Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>]

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On 08-04-2024 22:35, Balasubramani Vivekanandan wrote:
> From: Matt Roper<matthew.d.roper@intel.com>
>
> Discrete Xe2 platforms require programming of one additional row of PAT
> settings which controls the access characteristics for PPGTT and LMTT
> page tables.  Integrated GPUs do not need this programming and will
> leave the register at its hardware default value.
>
> Bspec:  71582
> Signed-off-by: Matt Roper<matthew.d.roper@intel.com>
> Signed-off-by: Balasubramani Vivekanandan<balasubramani.vivekanandan@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pat.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 66d8e3dd8237..13812042177d 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -142,6 +142,7 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
>   
>   /* Special PAT values programmed outside the main table */
>   static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
> +static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );

LGTM.

Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>

>   
>   u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>   {
> @@ -302,6 +303,9 @@ static void xe2lpg_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
>   {
>   	program_pat_mcr(gt, table, n_entries);
>   	xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe2_pat_ats.value);
> +
> +	if (IS_DGFX(gt_to_xe(gt)))
> +		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe2_pat_pta.value);
>   }
>   
>   static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],
> @@ -309,6 +313,9 @@ static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
>   {
>   	program_pat(gt, table, n_entries);
>   	xe_mmio_write32(gt, XE_REG(_PAT_ATS), xe2_pat_ats.value);
> +
> +	if (IS_DGFX(gt_to_xe(gt)))
> +		xe_mmio_write32(gt, XE_REG(_PAT_PTA), xe2_pat_pta.value);
>   }
>   
>   static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)

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