Re: [PATCH 7/8] drm/xe/xe_ras: Add support for Uncorrectable Core-Compute errors

[Riana Tauro <riana.tauro@intel.com>]

On 1/27/2026 5:14 PM, Mallesh, Koujalagi wrote:
> Hi Riana,
> 
> On 22-01-2026 03:36 pm, Riana Tauro wrote:
>> Uncorrectable Core-Compute errors are classified into Global and Local
>> errors.
>>
>> Global error is an error that affects the entire device requiring a
>> reset. This type of error is not isolated. When an AER is reported and
>> error_detected is invoked return PCI_ERS_RESULT_NEED_RESET.
>>
>> A Local error is confined to a specific component or context like a
>> engine. These errors can be contained and recovered by resetting
>> only the affected part without distrupting the rest of the device.
>>
>> Upon detection of an Uncorrectable Local Core-Compute error, an AER is
>> generated and GuC is notified of the error. The KMD then sets
>> the context as non-runnable and initiates an engine reset.
>> (TODO: GuC <->KMD communication for the error).
>> Since the error is contained and recovered, PCI error handling
>> callback returns PCI_ERS_RESULT_RECOVERED.
>>
>> Signed-off-by: Riana Tauro<riana.tauro@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_ras.c | 109 +++++++++++++++++++++++++++++++++++-
>>   drivers/gpu/drm/xe/xe_ras.h |   3 +
>>   2 files changed, 110 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index ace08d8d8d46..2a98cb116dc7 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -2,11 +2,16 @@
>>   /*
>>    * Copyright © 2026 Intel Corporation
>>    */
>> -#include <linux/pci.h>
>> -
>>   #include "xe_assert.h"
>>   #include "xe_device_types.h"
>> +#include "xe_printk.h"
>>   #include "xe_ras.h"
>> +#include "xe_ras_types.h"
>> +#include "xe_sysctrl_mailbox.h"
>> +#include "xe_sysctrl_mailbox_types.h"
>> +
>> +#define COMPUTE_ERROR_SEVERITY_MASK        GENMASK(26, 25)
>> +#define GLOBAL_UNCORR_ERROR            2
>>   /* Severity classification of detected errors */
>>   enum xe_ras_severity {
>> @@ -60,6 +65,106 @@ static inline const char *comp_to_str(struct 
>> xe_device *xe, u32 comp)
>>       return xe_ras_components[comp];
>>   }
>> +static void log_ras_error(struct xe_device *xe, struct 
>> xe_ras_error_class *error_class)
>> +{
>> +    struct xe_ras_error_common common_info = error_class->common;
>> +    struct xe_ras_error_product product_info = error_class->product;
>> +    u8 tile = product_info.unit.tile;
>> +    u32 instance = product_info.unit.instance;
>> +    u32 cause = product_info.error_cause.cause;
>> +
>> +    xe_err(xe, "[RAS]: Tile%u, Instance %u, %s %s Error detected 
>> Cause: 0x%x",
>> +           tile, instance, severity_to_str(xe, common_info.severity),
>> +           comp_to_str(xe, common_info.component), cause);
>> +}
>> +
>> +static pci_ers_result_t handle_compute_errors(struct xe_device *xe, 
>> struct xe_ras_error_array *arr)
>> +{
>> +    struct xe_ras_compute_error *error_info = (struct 
>> xe_ras_compute_error *)arr->error_details;
>> +    u8 uncorr_type;
>> +
>> +    uncorr_type = FIELD_GET(COMPUTE_ERROR_SEVERITY_MASK, error_info- 
>> >error_log_header);
>> +    log_ras_error(xe, &arr->error_class);
>> +
>> +    xe_err(xe, "[RAS]: Core Compute Error: timestamp %llu Uncorrected 
>> error type %u\n",
>> +           arr->timestamp, uncorr_type);
>> +
>> +    /* Request a RESET if error is global */
>> +    if (uncorr_type == GLOBAL_UNCORR_ERROR)
>> +        return PCI_ERS_RESULT_NEED_RESET;
>> +
>> +    /* Local errors are recovered using a engine reset */
>> +    return PCI_ERS_RESULT_RECOVERED;
>> +}
>> +
>> +/**
>> + * xe_ras_process_errors - Process and contain hardware errors
>> + * @xe: xe device instance
>> + *
>> + * Get error details from system controller and return recovery
>> + * method. Called only from PCI error handling.
>> + *
>> + * Returns: PCI_ERS_RESULT_RECOVERED if recovered or if no recovery 
>> needed,
>> + * PCI_ERS_RESULT_NEED_RESET otherwise.
>> + */
>> +pci_ers_result_t xe_ras_process_errors(struct xe_device *xe)
>> +{
>> +    struct xe_sysctrl_mailbox_command command = {0};
>> +    struct xe_sysctrl_mailbox_app_msg_hdr msg_hdr = {0};
>> +    struct xe_ras_get_error_response response;
>> +    u32 req_hdr;
>> +    size_t rlen;
>> +    int ret;
>> +
>> +    if (!xe->info.has_sysctrl)
>> +        return PCI_ERS_RESULT_NEED_RESET;
>> +
>> +    req_hdr = FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
>> +          FIELD_PREP(APP_HDR_COMMAND_MASK, 
>> XE_SYSCTRL_CMD_GET_SOC_ERROR);
>> +
>> +    msg_hdr.data = req_hdr;
>> +    command.header = msg_hdr;
>> +    command.data_out = &response;
>> +    command.data_out_len = sizeof(response);
>> +
>> +    do {
>> +        memset(&response, 0, sizeof(response));
>> +        rlen = 0;
>> +
>> +        ret = xe_sysctrl_send_command(xe, &command, &rlen);
>> +        if (ret || !rlen) {
>> +            xe_err(xe, "[RAS]: Sysctrl error ret %d\n", ret);
>> +            goto err;
>> +        }
>> +
>> +        if (rlen != sizeof(response)) {
>> +            xe_err(xe, "[RAS]: Sysctrl response does not match len!! 
>> \n");
>> +            goto err;
>> +        }
>> +
> 
>   Array bound check is required for response.num_errors. if num_errors 
> are more than 3 then potentials security issue (accessing uninitialized 
> or arbitrary memory).

yeah agree. Will fix this in next revision

Thanks
Riana

> 
> Thanks,
> 
> -/Mallesh
> 
>> +        for (int i = 0; i < response.num_errors; i++) {
>> +            struct xe_ras_error_array arr = response.error_arr[i];
>> +            struct xe_ras_error_class error_class;
>> +            u8 component;
>> +
>> +            error_class = arr.error_class;
>> +            component = error_class.common.component;
>> +
>> +            if (component == XE_RAS_COMPONENT_CORE_COMPUTE) {
>> +                ret = handle_compute_errors(xe, &arr);
>> +                if (ret == PCI_ERS_RESULT_NEED_RESET)
>> +                    goto err;
>> +            }
>> +        }
>> +
>> +    } while (response.additional_errors);
>> +
>> +    return PCI_ERS_RESULT_RECOVERED;
>> +
>> +err:
>> +    return PCI_ERS_RESULT_NEED_RESET;
>> +}
>> +
>>   #ifdef CONFIG_PCIEAER
>>   static void unmask_and_downgrade_internal_error(struct xe_device *xe)
>>   {
>> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
>> index 14cb973603e7..28400613c9a9 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.h
>> +++ b/drivers/gpu/drm/xe/xe_ras.h
>> @@ -6,8 +6,11 @@
>>   #ifndef _XE_RAS_H_
>>   #define _XE_RAS_H_
>> +#include <linux/pci.h>
>> +
>>   struct xe_device;
>>   void xe_ras_init(struct xe_device *xe);
>> +pci_ers_result_t xe_ras_process_errors(struct xe_device *xe);
>>   #endif