* [PATCH 1/8] drm/xe: Move explicit CT lock in TLB invalidation sequence
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-30 20:45 ` [PATCH 2/8] drm/xe: s/tlb_invalidation/tlb_inval stuartsummers
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, stuartsummers
We already have a lock tracking the fences/sequence numbers
here (pending_lock). And the GuC CT code already has an
implicit version of this lock in the ct_send routine.
Prepare the way for future optimizations in TLB invalidation
flow by moving the mutex lock down into the GuC CT send
routine rather than in the upper TLB invalidation layer.
Signed-off-by: stuartsummers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index 02f0bb92d6e0..230f30161395 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -158,7 +158,6 @@ void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
* appear.
*/
- mutex_lock(>->uc.guc.ct.lock);
spin_lock_irq(>->tlb_invalidation.pending_lock);
cancel_delayed_work(>->tlb_invalidation.fence_tdr);
/*
@@ -178,7 +177,6 @@ void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
>->tlb_invalidation.pending_fences, link)
invalidation_fence_signal(gt_to_xe(gt), fence);
spin_unlock_irq(>->tlb_invalidation.pending_lock);
- mutex_unlock(>->uc.guc.ct.lock);
}
static bool tlb_invalidation_seqno_past(struct xe_gt *gt, int seqno)
@@ -211,13 +209,12 @@ static int send_tlb_invalidation(struct xe_guc *guc,
* need to be updated.
*/
- mutex_lock(&guc->ct.lock);
seqno = gt->tlb_invalidation.seqno;
fence->seqno = seqno;
trace_xe_gt_tlb_invalidation_fence_send(xe, fence);
action[1] = seqno;
- ret = xe_guc_ct_send_locked(&guc->ct, action, len,
- G2H_LEN_DW_TLB_INVALIDATE, 1);
+ ret = xe_guc_ct_send(&guc->ct, action, len,
+ G2H_LEN_DW_TLB_INVALIDATE, 1);
if (!ret) {
spin_lock_irq(>->tlb_invalidation.pending_lock);
/*
@@ -248,7 +245,6 @@ static int send_tlb_invalidation(struct xe_guc *guc,
if (!gt->tlb_invalidation.seqno)
gt->tlb_invalidation.seqno = 1;
}
- mutex_unlock(&guc->ct.lock);
xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/8] drm/xe: s/tlb_invalidation/tlb_inval
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
2025-07-30 20:45 ` [PATCH 1/8] drm/xe: Move explicit CT lock in TLB invalidation sequence stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-30 20:45 ` [PATCH 3/8] drm/xe: Add xe_tlb_inval structure stuartsummers
` (9 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
tlb_invalidation is a bit verbose leading to ugly wraps in the code,
shorten to tlb_inval.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/xe_device_types.h | 4 +-
drivers/gpu/drm/xe/xe_exec_queue.c | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 4 +-
drivers/gpu/drm/xe/xe_gt.c | 8 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 1 -
...t_tlb_invalidation.c => xe_gt_tlb_inval.c} | 246 +++++++++---------
drivers/gpu/drm/xe/xe_gt_tlb_inval.h | 40 +++
drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c | 18 +-
...dation_types.h => xe_gt_tlb_inval_types.h} | 14 +-
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h | 40 ---
drivers/gpu/drm/xe/xe_gt_types.h | 18 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 8 +-
drivers/gpu/drm/xe/xe_lmtt.c | 12 +-
drivers/gpu/drm/xe/xe_pci.c | 6 +-
drivers/gpu/drm/xe/xe_pci_types.h | 2 +-
drivers/gpu/drm/xe/xe_svm.c | 4 +-
drivers/gpu/drm/xe/xe_trace.h | 24 +-
drivers/gpu/drm/xe/xe_vm.c | 64 +++--
drivers/gpu/drm/xe/xe_vm.h | 4 +-
20 files changed, 255 insertions(+), 266 deletions(-)
rename drivers/gpu/drm/xe/{xe_gt_tlb_invalidation.c => xe_gt_tlb_inval.c} (62%)
create mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval.h
rename drivers/gpu/drm/xe/{xe_gt_tlb_invalidation_types.h => xe_gt_tlb_inval_types.h} (55%)
delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 8e0c3412a757..0a36b2463434 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -61,7 +61,7 @@ xe-y += xe_bb.o \
xe_gt_pagefault.o \
xe_gt_sysfs.o \
xe_gt_throttle.o \
- xe_gt_tlb_invalidation.o \
+ xe_gt_tlb_inval.o \
xe_gt_tlb_inval_job.o \
xe_gt_topology.o \
xe_guc.o \
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 38c8329b4d2c..159653303038 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -287,8 +287,8 @@ struct xe_device {
u8 has_mbx_power_limits:1;
/** @info.has_pxp: Device has PXP support */
u8 has_pxp:1;
- /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */
- u8 has_range_tlb_invalidation:1;
+ /** @info.has_range_tlb_inval: Has range based TLB invalidations */
+ u8 has_range_tlb_inval:1;
/** @info.has_sriov: Supports SR-IOV */
u8 has_sriov:1;
/** @info.has_usm: Device has unified shared memory support */
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d5958518ef00..cf21f0f6bae6 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -75,7 +75,7 @@ static int alloc_dep_schedulers(struct xe_device *xe, struct xe_exec_queue *q)
if (!gt)
continue;
- wq = gt->tlb_invalidation.job_wq;
+ wq = gt->tlb_inval.job_wq;
#define MAX_TLB_INVAL_JOBS 16 /* Picking a reasonable value */
dep_scheduler = xe_dep_scheduler_create(xe, wq, q->name,
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 249713139f69..78d426778151 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -23,7 +23,7 @@
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_printk.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_pm.h"
@@ -438,7 +438,7 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
if (!gt)
return;
- err = xe_gt_tlb_invalidation_ggtt(gt);
+ err = xe_gt_tlb_inval_ggtt(gt);
xe_gt_WARN(gt, err, "Failed to invalidate GGTT (%pe)", ERR_PTR(err));
}
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 5a79c6e3208b..95ed95d38494 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -37,7 +37,7 @@
#include "xe_gt_sriov_pf.h"
#include "xe_gt_sriov_vf.h"
#include "xe_gt_sysfs.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_gt_topology.h"
#include "xe_guc_exec_queue_types.h"
#include "xe_guc_pc.h"
@@ -412,7 +412,7 @@ int xe_gt_init_early(struct xe_gt *gt)
xe_force_wake_init_gt(gt, gt_to_fw(gt));
spin_lock_init(>->global_invl_lock);
- err = xe_gt_tlb_invalidation_init_early(gt);
+ err = xe_gt_tlb_inval_init_early(gt);
if (err)
return err;
@@ -840,7 +840,7 @@ static int gt_reset(struct xe_gt *gt)
xe_uc_stop(>->uc);
- xe_gt_tlb_invalidation_reset(gt);
+ xe_gt_tlb_inval_reset(gt);
err = do_gt_reset(gt);
if (err)
@@ -1054,5 +1054,5 @@ void xe_gt_declare_wedged(struct xe_gt *gt)
xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode);
xe_uc_declare_wedged(>->uc);
- xe_gt_tlb_invalidation_reset(gt);
+ xe_gt_tlb_inval_reset(gt);
}
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index ab43dec52776..1da6a981ca4e 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -16,7 +16,6 @@
#include "xe_gt.h"
#include "xe_gt_printk.h"
#include "xe_gt_stats.h"
-#include "xe_gt_tlb_invalidation.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_migrate.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
similarity index 62%
rename from drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
rename to drivers/gpu/drm/xe/xe_gt_tlb_inval.c
index 230f30161395..188e09124887 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
@@ -5,8 +5,6 @@
#include <drm/drm_managed.h>
-#include "xe_gt_tlb_invalidation.h"
-
#include "abi/guc_actions_abi.h"
#include "xe_device.h"
#include "xe_force_wake.h"
@@ -15,6 +13,7 @@
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_gt_stats.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_mmio.h"
#include "xe_pm.h"
#include "xe_sriov.h"
@@ -39,7 +38,7 @@ static long tlb_timeout_jiffies(struct xe_gt *gt)
return hw_tlb_timeout + 2 * delay;
}
-static void xe_gt_tlb_invalidation_fence_fini(struct xe_gt_tlb_invalidation_fence *fence)
+static void xe_gt_tlb_inval_fence_fini(struct xe_gt_tlb_inval_fence *fence)
{
if (WARN_ON_ONCE(!fence->gt))
return;
@@ -49,66 +48,66 @@ static void xe_gt_tlb_invalidation_fence_fini(struct xe_gt_tlb_invalidation_fenc
}
static void
-__invalidation_fence_signal(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence)
+__inval_fence_signal(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence)
{
bool stack = test_bit(FENCE_STACK_BIT, &fence->base.flags);
- trace_xe_gt_tlb_invalidation_fence_signal(xe, fence);
- xe_gt_tlb_invalidation_fence_fini(fence);
+ trace_xe_gt_tlb_inval_fence_signal(xe, fence);
+ xe_gt_tlb_inval_fence_fini(fence);
dma_fence_signal(&fence->base);
if (!stack)
dma_fence_put(&fence->base);
}
static void
-invalidation_fence_signal(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence)
+inval_fence_signal(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence)
{
list_del(&fence->link);
- __invalidation_fence_signal(xe, fence);
+ __inval_fence_signal(xe, fence);
}
-void xe_gt_tlb_invalidation_fence_signal(struct xe_gt_tlb_invalidation_fence *fence)
+void xe_gt_tlb_inval_fence_signal(struct xe_gt_tlb_inval_fence *fence)
{
if (WARN_ON_ONCE(!fence->gt))
return;
- __invalidation_fence_signal(gt_to_xe(fence->gt), fence);
+ __inval_fence_signal(gt_to_xe(fence->gt), fence);
}
static void xe_gt_tlb_fence_timeout(struct work_struct *work)
{
struct xe_gt *gt = container_of(work, struct xe_gt,
- tlb_invalidation.fence_tdr.work);
+ tlb_inval.fence_tdr.work);
struct xe_device *xe = gt_to_xe(gt);
- struct xe_gt_tlb_invalidation_fence *fence, *next;
+ struct xe_gt_tlb_inval_fence *fence, *next;
LNL_FLUSH_WORK(>->uc.guc.ct.g2h_worker);
- spin_lock_irq(>->tlb_invalidation.pending_lock);
+ spin_lock_irq(>->tlb_inval.pending_lock);
list_for_each_entry_safe(fence, next,
- >->tlb_invalidation.pending_fences, link) {
+ >->tlb_inval.pending_fences, link) {
s64 since_inval_ms = ktime_ms_delta(ktime_get(),
- fence->invalidation_time);
+ fence->inval_time);
if (msecs_to_jiffies(since_inval_ms) < tlb_timeout_jiffies(gt))
break;
- trace_xe_gt_tlb_invalidation_fence_timeout(xe, fence);
+ trace_xe_gt_tlb_inval_fence_timeout(xe, fence);
xe_gt_err(gt, "TLB invalidation fence timeout, seqno=%d recv=%d",
- fence->seqno, gt->tlb_invalidation.seqno_recv);
+ fence->seqno, gt->tlb_inval.seqno_recv);
fence->base.error = -ETIME;
- invalidation_fence_signal(xe, fence);
+ inval_fence_signal(xe, fence);
}
- if (!list_empty(>->tlb_invalidation.pending_fences))
+ if (!list_empty(>->tlb_inval.pending_fences))
queue_delayed_work(system_wq,
- >->tlb_invalidation.fence_tdr,
+ >->tlb_inval.fence_tdr,
tlb_timeout_jiffies(gt));
- spin_unlock_irq(>->tlb_invalidation.pending_lock);
+ spin_unlock_irq(>->tlb_inval.pending_lock);
}
/**
- * xe_gt_tlb_invalidation_init_early - Initialize GT TLB invalidation state
+ * xe_gt_tlb_inval_init_early - Initialize GT TLB invalidation state
* @gt: GT structure
*
* Initialize GT TLB invalidation state, purely software initialization, should
@@ -116,33 +115,33 @@ static void xe_gt_tlb_fence_timeout(struct work_struct *work)
*
* Return: 0 on success, negative error code on error.
*/
-int xe_gt_tlb_invalidation_init_early(struct xe_gt *gt)
+int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
{
- gt->tlb_invalidation.seqno = 1;
- INIT_LIST_HEAD(>->tlb_invalidation.pending_fences);
- spin_lock_init(>->tlb_invalidation.pending_lock);
- spin_lock_init(>->tlb_invalidation.lock);
- INIT_DELAYED_WORK(>->tlb_invalidation.fence_tdr,
+ gt->tlb_inval.seqno = 1;
+ INIT_LIST_HEAD(>->tlb_inval.pending_fences);
+ spin_lock_init(>->tlb_inval.pending_lock);
+ spin_lock_init(>->tlb_inval.lock);
+ INIT_DELAYED_WORK(>->tlb_inval.fence_tdr,
xe_gt_tlb_fence_timeout);
- gt->tlb_invalidation.job_wq =
+ gt->tlb_inval.job_wq =
drmm_alloc_ordered_workqueue(>_to_xe(gt)->drm, "gt-tbl-inval-job-wq",
WQ_MEM_RECLAIM);
- if (IS_ERR(gt->tlb_invalidation.job_wq))
- return PTR_ERR(gt->tlb_invalidation.job_wq);
+ if (IS_ERR(gt->tlb_inval.job_wq))
+ return PTR_ERR(gt->tlb_inval.job_wq);
return 0;
}
/**
- * xe_gt_tlb_invalidation_reset - Initialize GT TLB invalidation reset
+ * xe_gt_tlb_inval_reset - Initialize GT TLB invalidation reset
* @gt: GT structure
*
* Signal any pending invalidation fences, should be called during a GT reset
*/
-void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
+void xe_gt_tlb_inval_reset(struct xe_gt *gt)
{
- struct xe_gt_tlb_invalidation_fence *fence, *next;
+ struct xe_gt_tlb_inval_fence *fence, *next;
int pending_seqno;
/*
@@ -158,8 +157,8 @@ void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
* appear.
*/
- spin_lock_irq(>->tlb_invalidation.pending_lock);
- cancel_delayed_work(>->tlb_invalidation.fence_tdr);
+ spin_lock_irq(>->tlb_inval.pending_lock);
+ cancel_delayed_work(>->tlb_inval.fence_tdr);
/*
* We might have various kworkers waiting for TLB flushes to complete
* which are not tracked with an explicit TLB fence, however at this
@@ -167,21 +166,21 @@ void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
* make sure we signal them here under the assumption that we have
* completed a full GT reset.
*/
- if (gt->tlb_invalidation.seqno == 1)
+ if (gt->tlb_inval.seqno == 1)
pending_seqno = TLB_INVALIDATION_SEQNO_MAX - 1;
else
- pending_seqno = gt->tlb_invalidation.seqno - 1;
- WRITE_ONCE(gt->tlb_invalidation.seqno_recv, pending_seqno);
+ pending_seqno = gt->tlb_inval.seqno - 1;
+ WRITE_ONCE(gt->tlb_inval.seqno_recv, pending_seqno);
list_for_each_entry_safe(fence, next,
- >->tlb_invalidation.pending_fences, link)
- invalidation_fence_signal(gt_to_xe(gt), fence);
- spin_unlock_irq(>->tlb_invalidation.pending_lock);
+ >->tlb_inval.pending_fences, link)
+ inval_fence_signal(gt_to_xe(gt), fence);
+ spin_unlock_irq(>->tlb_inval.pending_lock);
}
-static bool tlb_invalidation_seqno_past(struct xe_gt *gt, int seqno)
+static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
{
- int seqno_recv = READ_ONCE(gt->tlb_invalidation.seqno_recv);
+ int seqno_recv = READ_ONCE(gt->tlb_inval.seqno_recv);
if (seqno - seqno_recv < -(TLB_INVALIDATION_SEQNO_MAX / 2))
return false;
@@ -192,9 +191,9 @@ static bool tlb_invalidation_seqno_past(struct xe_gt *gt, int seqno)
return seqno_recv >= seqno;
}
-static int send_tlb_invalidation(struct xe_guc *guc,
- struct xe_gt_tlb_invalidation_fence *fence,
- u32 *action, int len)
+static int send_tlb_inval(struct xe_guc *guc,
+ struct xe_gt_tlb_inval_fence *fence,
+ u32 *action, int len)
{
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = gt_to_xe(gt);
@@ -209,41 +208,41 @@ static int send_tlb_invalidation(struct xe_guc *guc,
* need to be updated.
*/
- seqno = gt->tlb_invalidation.seqno;
+ seqno = gt->tlb_inval.seqno;
fence->seqno = seqno;
- trace_xe_gt_tlb_invalidation_fence_send(xe, fence);
+ trace_xe_gt_tlb_inval_fence_send(xe, fence);
action[1] = seqno;
ret = xe_guc_ct_send(&guc->ct, action, len,
G2H_LEN_DW_TLB_INVALIDATE, 1);
if (!ret) {
- spin_lock_irq(>->tlb_invalidation.pending_lock);
+ spin_lock_irq(>->tlb_inval.pending_lock);
/*
* We haven't actually published the TLB fence as per
* pending_fences, but in theory our seqno could have already
* been written as we acquired the pending_lock. In such a case
* we can just go ahead and signal the fence here.
*/
- if (tlb_invalidation_seqno_past(gt, seqno)) {
- __invalidation_fence_signal(xe, fence);
+ if (tlb_inval_seqno_past(gt, seqno)) {
+ __inval_fence_signal(xe, fence);
} else {
- fence->invalidation_time = ktime_get();
+ fence->inval_time = ktime_get();
list_add_tail(&fence->link,
- >->tlb_invalidation.pending_fences);
+ >->tlb_inval.pending_fences);
- if (list_is_singular(>->tlb_invalidation.pending_fences))
+ if (list_is_singular(>->tlb_inval.pending_fences))
queue_delayed_work(system_wq,
- >->tlb_invalidation.fence_tdr,
+ >->tlb_inval.fence_tdr,
tlb_timeout_jiffies(gt));
}
- spin_unlock_irq(>->tlb_invalidation.pending_lock);
+ spin_unlock_irq(>->tlb_inval.pending_lock);
} else {
- __invalidation_fence_signal(xe, fence);
+ __inval_fence_signal(xe, fence);
}
if (!ret) {
- gt->tlb_invalidation.seqno = (gt->tlb_invalidation.seqno + 1) %
+ gt->tlb_inval.seqno = (gt->tlb_inval.seqno + 1) %
TLB_INVALIDATION_SEQNO_MAX;
- if (!gt->tlb_invalidation.seqno)
- gt->tlb_invalidation.seqno = 1;
+ if (!gt->tlb_inval.seqno)
+ gt->tlb_inval.seqno = 1;
}
xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
@@ -255,7 +254,7 @@ static int send_tlb_invalidation(struct xe_guc *guc,
XE_GUC_TLB_INVAL_FLUSH_CACHE)
/**
- * xe_gt_tlb_invalidation_guc - Issue a TLB invalidation on this GT for the GuC
+ * xe_gt_tlb_inval_guc - Issue a TLB invalidation on this GT for the GuC
* @gt: GT structure
* @fence: invalidation fence which will be signal on TLB invalidation
* completion
@@ -265,18 +264,17 @@ static int send_tlb_invalidation(struct xe_guc *guc,
*
* Return: 0 on success, negative error code on error
*/
-static int xe_gt_tlb_invalidation_guc(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence)
+static int xe_gt_tlb_inval_guc(struct xe_gt *gt,
+ struct xe_gt_tlb_inval_fence *fence)
{
u32 action[] = {
XE_GUC_ACTION_TLB_INVALIDATION,
- 0, /* seqno, replaced in send_tlb_invalidation */
+ 0, /* seqno, replaced in send_tlb_inval */
MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
};
int ret;
- ret = send_tlb_invalidation(>->uc.guc, fence, action,
- ARRAY_SIZE(action));
+ ret = send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
/*
* -ECANCELED indicates the CT is stopped for a GT reset. TLB caches
* should be nuked on a GT reset so this error can be ignored.
@@ -288,7 +286,7 @@ static int xe_gt_tlb_invalidation_guc(struct xe_gt *gt,
}
/**
- * xe_gt_tlb_invalidation_ggtt - Issue a TLB invalidation on this GT for the GGTT
+ * xe_gt_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
* @gt: GT structure
*
* Issue a TLB invalidation for the GGTT. Completion of TLB invalidation is
@@ -296,22 +294,22 @@ static int xe_gt_tlb_invalidation_guc(struct xe_gt *gt,
*
* Return: 0 on success, negative error code on error
*/
-int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt)
+int xe_gt_tlb_inval_ggtt(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
unsigned int fw_ref;
if (xe_guc_ct_enabled(>->uc.guc.ct) &&
gt->uc.guc.submission_state.enabled) {
- struct xe_gt_tlb_invalidation_fence fence;
+ struct xe_gt_tlb_inval_fence fence;
int ret;
- xe_gt_tlb_invalidation_fence_init(gt, &fence, true);
- ret = xe_gt_tlb_invalidation_guc(gt, &fence);
+ xe_gt_tlb_inval_fence_init(gt, &fence, true);
+ ret = xe_gt_tlb_inval_guc(gt, &fence);
if (ret)
return ret;
- xe_gt_tlb_invalidation_fence_wait(&fence);
+ xe_gt_tlb_inval_fence_wait(&fence);
} else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
struct xe_mmio *mmio = >->mmio;
@@ -334,34 +332,34 @@ int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt)
return 0;
}
-static int send_tlb_invalidation_all(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence)
+static int send_tlb_inval_all(struct xe_gt *gt,
+ struct xe_gt_tlb_inval_fence *fence)
{
u32 action[] = {
XE_GUC_ACTION_TLB_INVALIDATION_ALL,
- 0, /* seqno, replaced in send_tlb_invalidation */
+ 0, /* seqno, replaced in send_tlb_inval */
MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
};
- return send_tlb_invalidation(>->uc.guc, fence, action, ARRAY_SIZE(action));
+ return send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
}
/**
* xe_gt_tlb_invalidation_all - Invalidate all TLBs across PF and all VFs.
* @gt: the &xe_gt structure
- * @fence: the &xe_gt_tlb_invalidation_fence to be signaled on completion
+ * @fence: the &xe_gt_tlb_inval_fence to be signaled on completion
*
* Send a request to invalidate all TLBs across PF and all VFs.
*
* Return: 0 on success, negative error code on error
*/
-int xe_gt_tlb_invalidation_all(struct xe_gt *gt, struct xe_gt_tlb_invalidation_fence *fence)
+int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence)
{
int err;
xe_gt_assert(gt, gt == fence->gt);
- err = send_tlb_invalidation_all(gt, fence);
+ err = send_tlb_inval_all(gt, fence);
if (err)
xe_gt_err(gt, "TLB invalidation request failed (%pe)", ERR_PTR(err));
@@ -376,8 +374,7 @@ int xe_gt_tlb_invalidation_all(struct xe_gt *gt, struct xe_gt_tlb_invalidation_f
#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
/**
- * xe_gt_tlb_invalidation_range - Issue a TLB invalidation on this GT for an
- * address range
+ * xe_gt_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
*
* @gt: GT structure
* @fence: invalidation fence which will be signal on TLB invalidation
@@ -392,9 +389,8 @@ int xe_gt_tlb_invalidation_all(struct xe_gt *gt, struct xe_gt_tlb_invalidation_f
*
* Return: Negative error code on error, 0 on success
*/
-int xe_gt_tlb_invalidation_range(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence,
- u64 start, u64 end, u32 asid)
+int xe_gt_tlb_inval_range(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence,
+ u64 start, u64 end, u32 asid)
{
struct xe_device *xe = gt_to_xe(gt);
#define MAX_TLB_INVALIDATION_LEN 7
@@ -406,13 +402,13 @@ int xe_gt_tlb_invalidation_range(struct xe_gt *gt,
/* Execlists not supported */
if (gt_to_xe(gt)->info.force_execlist) {
- __invalidation_fence_signal(xe, fence);
+ __inval_fence_signal(xe, fence);
return 0;
}
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
- action[len++] = 0; /* seqno, replaced in send_tlb_invalidation */
- if (!xe->info.has_range_tlb_invalidation ||
+ action[len++] = 0; /* seqno, replaced in send_tlb_inval */
+ if (!xe->info.has_range_tlb_inval ||
length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
} else {
@@ -461,33 +457,33 @@ int xe_gt_tlb_invalidation_range(struct xe_gt *gt,
xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
- return send_tlb_invalidation(>->uc.guc, fence, action, len);
+ return send_tlb_inval(>->uc.guc, fence, action, len);
}
/**
- * xe_gt_tlb_invalidation_vm - Issue a TLB invalidation on this GT for a VM
+ * xe_gt_tlb_inval_vm - Issue a TLB invalidation on this GT for a VM
* @gt: graphics tile
* @vm: VM to invalidate
*
* Invalidate entire VM's address space
*/
-void xe_gt_tlb_invalidation_vm(struct xe_gt *gt, struct xe_vm *vm)
+void xe_gt_tlb_inval_vm(struct xe_gt *gt, struct xe_vm *vm)
{
- struct xe_gt_tlb_invalidation_fence fence;
+ struct xe_gt_tlb_inval_fence fence;
u64 range = 1ull << vm->xe->info.va_bits;
int ret;
- xe_gt_tlb_invalidation_fence_init(gt, &fence, true);
+ xe_gt_tlb_inval_fence_init(gt, &fence, true);
- ret = xe_gt_tlb_invalidation_range(gt, &fence, 0, range, vm->usm.asid);
+ ret = xe_gt_tlb_inval_range(gt, &fence, 0, range, vm->usm.asid);
if (ret < 0)
return;
- xe_gt_tlb_invalidation_fence_wait(&fence);
+ xe_gt_tlb_inval_fence_wait(&fence);
}
/**
- * xe_guc_tlb_invalidation_done_handler - TLB invalidation done handler
+ * xe_guc_tlb_inval_done_handler - TLB invalidation done handler
* @guc: guc
* @msg: message indicating TLB invalidation done
* @len: length of message
@@ -498,11 +494,11 @@ void xe_gt_tlb_invalidation_vm(struct xe_gt *gt, struct xe_vm *vm)
*
* Return: 0 on success, -EPROTO for malformed messages.
*/
-int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
{
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = gt_to_xe(gt);
- struct xe_gt_tlb_invalidation_fence *fence, *next;
+ struct xe_gt_tlb_inval_fence *fence, *next;
unsigned long flags;
if (unlikely(len != 1))
@@ -523,74 +519,74 @@ int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
* officially process the CT message like if racing against
* process_g2h_msg().
*/
- spin_lock_irqsave(>->tlb_invalidation.pending_lock, flags);
- if (tlb_invalidation_seqno_past(gt, msg[0])) {
- spin_unlock_irqrestore(>->tlb_invalidation.pending_lock, flags);
+ spin_lock_irqsave(>->tlb_inval.pending_lock, flags);
+ if (tlb_inval_seqno_past(gt, msg[0])) {
+ spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
return 0;
}
- WRITE_ONCE(gt->tlb_invalidation.seqno_recv, msg[0]);
+ WRITE_ONCE(gt->tlb_inval.seqno_recv, msg[0]);
list_for_each_entry_safe(fence, next,
- >->tlb_invalidation.pending_fences, link) {
- trace_xe_gt_tlb_invalidation_fence_recv(xe, fence);
+ >->tlb_inval.pending_fences, link) {
+ trace_xe_gt_tlb_inval_fence_recv(xe, fence);
- if (!tlb_invalidation_seqno_past(gt, fence->seqno))
+ if (!tlb_inval_seqno_past(gt, fence->seqno))
break;
- invalidation_fence_signal(xe, fence);
+ inval_fence_signal(xe, fence);
}
- if (!list_empty(>->tlb_invalidation.pending_fences))
+ if (!list_empty(>->tlb_inval.pending_fences))
mod_delayed_work(system_wq,
- >->tlb_invalidation.fence_tdr,
+ >->tlb_inval.fence_tdr,
tlb_timeout_jiffies(gt));
else
- cancel_delayed_work(>->tlb_invalidation.fence_tdr);
+ cancel_delayed_work(>->tlb_inval.fence_tdr);
- spin_unlock_irqrestore(>->tlb_invalidation.pending_lock, flags);
+ spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
return 0;
}
static const char *
-invalidation_fence_get_driver_name(struct dma_fence *dma_fence)
+inval_fence_get_driver_name(struct dma_fence *dma_fence)
{
return "xe";
}
static const char *
-invalidation_fence_get_timeline_name(struct dma_fence *dma_fence)
+inval_fence_get_timeline_name(struct dma_fence *dma_fence)
{
- return "invalidation_fence";
+ return "inval_fence";
}
-static const struct dma_fence_ops invalidation_fence_ops = {
- .get_driver_name = invalidation_fence_get_driver_name,
- .get_timeline_name = invalidation_fence_get_timeline_name,
+static const struct dma_fence_ops inval_fence_ops = {
+ .get_driver_name = inval_fence_get_driver_name,
+ .get_timeline_name = inval_fence_get_timeline_name,
};
/**
- * xe_gt_tlb_invalidation_fence_init - Initialize TLB invalidation fence
+ * xe_gt_tlb_inval_fence_init - Initialize TLB invalidation fence
* @gt: GT
* @fence: TLB invalidation fence to initialize
* @stack: fence is stack variable
*
- * Initialize TLB invalidation fence for use. xe_gt_tlb_invalidation_fence_fini
+ * Initialize TLB invalidation fence for use. xe_gt_tlb_inval_fence_fini
* will be automatically called when fence is signalled (all fences must signal),
* even on error.
*/
-void xe_gt_tlb_invalidation_fence_init(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence,
- bool stack)
+void xe_gt_tlb_inval_fence_init(struct xe_gt *gt,
+ struct xe_gt_tlb_inval_fence *fence,
+ bool stack)
{
xe_pm_runtime_get_noresume(gt_to_xe(gt));
- spin_lock_irq(>->tlb_invalidation.lock);
- dma_fence_init(&fence->base, &invalidation_fence_ops,
- >->tlb_invalidation.lock,
+ spin_lock_irq(>->tlb_inval.lock);
+ dma_fence_init(&fence->base, &inval_fence_ops,
+ >->tlb_inval.lock,
dma_fence_context_alloc(1), 1);
- spin_unlock_irq(>->tlb_invalidation.lock);
+ spin_unlock_irq(>->tlb_inval.lock);
INIT_LIST_HEAD(&fence->link);
if (stack)
set_bit(FENCE_STACK_BIT, &fence->base.flags);
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval.h
new file mode 100644
index 000000000000..801d4ecf88f0
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GT_TLB_INVAL_H_
+#define _XE_GT_TLB_INVAL_H_
+
+#include <linux/types.h>
+
+#include "xe_gt_tlb_inval_types.h"
+
+struct xe_gt;
+struct xe_guc;
+struct xe_vm;
+struct xe_vma;
+
+int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
+
+void xe_gt_tlb_inval_reset(struct xe_gt *gt);
+int xe_gt_tlb_inval_ggtt(struct xe_gt *gt);
+void xe_gt_tlb_inval_vm(struct xe_gt *gt, struct xe_vm *vm);
+int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence);
+int xe_gt_tlb_inval_range(struct xe_gt *gt,
+ struct xe_gt_tlb_inval_fence *fence,
+ u64 start, u64 end, u32 asid);
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
+
+void xe_gt_tlb_inval_fence_init(struct xe_gt *gt,
+ struct xe_gt_tlb_inval_fence *fence,
+ bool stack);
+void xe_gt_tlb_inval_fence_signal(struct xe_gt_tlb_inval_fence *fence);
+
+static inline void
+xe_gt_tlb_inval_fence_wait(struct xe_gt_tlb_inval_fence *fence)
+{
+ dma_fence_wait(&fence->base, false);
+}
+
+#endif /* _XE_GT_TLB_INVAL_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
index e9255be26467..41e0ea92ea5a 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
@@ -7,7 +7,7 @@
#include "xe_dep_scheduler.h"
#include "xe_exec_queue.h"
#include "xe_gt.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_gt_tlb_inval_job.h"
#include "xe_migrate.h"
#include "xe_pm.h"
@@ -41,11 +41,11 @@ static struct dma_fence *xe_gt_tlb_inval_job_run(struct xe_dep_job *dep_job)
{
struct xe_gt_tlb_inval_job *job =
container_of(dep_job, typeof(*job), dep);
- struct xe_gt_tlb_invalidation_fence *ifence =
+ struct xe_gt_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
- xe_gt_tlb_invalidation_range(job->gt, ifence, job->start,
- job->end, job->asid);
+ xe_gt_tlb_inval_range(job->gt, ifence, job->start,
+ job->end, job->asid);
return job->fence;
}
@@ -93,7 +93,7 @@ struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
q->tlb_inval[xe_gt_tlb_inval_context(gt)].dep_scheduler;
struct drm_sched_entity *entity =
xe_dep_scheduler_entity(dep_scheduler);
- struct xe_gt_tlb_invalidation_fence *ifence;
+ struct xe_gt_tlb_inval_fence *ifence;
int err;
job = kmalloc(sizeof(*job), GFP_KERNEL);
@@ -140,7 +140,7 @@ static void xe_gt_tlb_inval_job_destroy(struct kref *ref)
{
struct xe_gt_tlb_inval_job *job = container_of(ref, typeof(*job),
refcount);
- struct xe_gt_tlb_invalidation_fence *ifence =
+ struct xe_gt_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
struct xe_device *xe = gt_to_xe(job->gt);
struct xe_exec_queue *q = job->q;
@@ -148,7 +148,7 @@ static void xe_gt_tlb_inval_job_destroy(struct kref *ref)
if (!job->fence_armed)
kfree(ifence);
else
- /* Ref from xe_gt_tlb_invalidation_fence_init */
+ /* Ref from xe_gt_tlb_inval_fence_init */
dma_fence_put(job->fence);
drm_sched_job_cleanup(&job->dep.drm);
@@ -194,7 +194,7 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
struct xe_migrate *m,
struct dma_fence *fence)
{
- struct xe_gt_tlb_invalidation_fence *ifence =
+ struct xe_gt_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
if (!dma_fence_is_signaled(fence)) {
@@ -226,7 +226,7 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
xe_migrate_job_lock(m, job->q);
/* Creation ref pairs with put in xe_gt_tlb_inval_job_destroy */
- xe_gt_tlb_invalidation_fence_init(job->gt, ifence, false);
+ xe_gt_tlb_inval_fence_init(job->gt, ifence, false);
dma_fence_get(job->fence); /* Pairs with put in DRM scheduler */
drm_sched_job_arm(&job->dep.drm);
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
similarity index 55%
rename from drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
rename to drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
index de6e825e0851..919430359103 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
@@ -3,20 +3,20 @@
* Copyright © 2023 Intel Corporation
*/
-#ifndef _XE_GT_TLB_INVALIDATION_TYPES_H_
-#define _XE_GT_TLB_INVALIDATION_TYPES_H_
+#ifndef _XE_GT_TLB_INVAL_TYPES_H_
+#define _XE_GT_TLB_INVAL_TYPES_H_
#include <linux/dma-fence.h>
struct xe_gt;
/**
- * struct xe_gt_tlb_invalidation_fence - XE GT TLB invalidation fence
+ * struct xe_gt_tlb_inval_fence - XE GT TLB invalidation fence
*
- * Optionally passed to xe_gt_tlb_invalidation and will be signaled upon TLB
+ * Optionally passed to xe_gt_tlb_inval and will be signaled upon TLB
* invalidation completion.
*/
-struct xe_gt_tlb_invalidation_fence {
+struct xe_gt_tlb_inval_fence {
/** @base: dma fence base */
struct dma_fence base;
/** @gt: GT which fence belong to */
@@ -25,8 +25,8 @@ struct xe_gt_tlb_invalidation_fence {
struct list_head link;
/** @seqno: seqno of TLB invalidation to signal fence one */
int seqno;
- /** @invalidation_time: time of TLB invalidation */
- ktime_t invalidation_time;
+ /** @inval_time: time of TLB invalidation */
+ ktime_t inval_time;
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
deleted file mode 100644
index f7f0f2eaf4b5..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef _XE_GT_TLB_INVALIDATION_H_
-#define _XE_GT_TLB_INVALIDATION_H_
-
-#include <linux/types.h>
-
-#include "xe_gt_tlb_invalidation_types.h"
-
-struct xe_gt;
-struct xe_guc;
-struct xe_vm;
-struct xe_vma;
-
-int xe_gt_tlb_invalidation_init_early(struct xe_gt *gt);
-
-void xe_gt_tlb_invalidation_reset(struct xe_gt *gt);
-int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt);
-void xe_gt_tlb_invalidation_vm(struct xe_gt *gt, struct xe_vm *vm);
-int xe_gt_tlb_invalidation_all(struct xe_gt *gt, struct xe_gt_tlb_invalidation_fence *fence);
-int xe_gt_tlb_invalidation_range(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence,
- u64 start, u64 end, u32 asid);
-int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
-
-void xe_gt_tlb_invalidation_fence_init(struct xe_gt *gt,
- struct xe_gt_tlb_invalidation_fence *fence,
- bool stack);
-void xe_gt_tlb_invalidation_fence_signal(struct xe_gt_tlb_invalidation_fence *fence);
-
-static inline void
-xe_gt_tlb_invalidation_fence_wait(struct xe_gt_tlb_invalidation_fence *fence)
-{
- dma_fence_wait(&fence->base, false);
-}
-
-#endif /* _XE_GT_TLB_INVALIDATION_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index dfd4a16da5f0..38cdca4107c8 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -185,36 +185,36 @@ struct xe_gt {
struct work_struct worker;
} reset;
- /** @tlb_invalidation: TLB invalidation state */
+ /** @tlb_inval: TLB invalidation state */
struct {
- /** @tlb_invalidation.seqno: TLB invalidation seqno, protected by CT lock */
+ /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
#define TLB_INVALIDATION_SEQNO_MAX 0x100000
int seqno;
/**
- * @tlb_invalidation.seqno_recv: last received TLB invalidation seqno,
+ * @tlb_inval.seqno_recv: last received TLB invalidation seqno,
* protected by CT lock
*/
int seqno_recv;
/**
- * @tlb_invalidation.pending_fences: list of pending fences waiting TLB
+ * @tlb_inval.pending_fences: list of pending fences waiting TLB
* invaliations, protected by CT lock
*/
struct list_head pending_fences;
/**
- * @tlb_invalidation.pending_lock: protects @tlb_invalidation.pending_fences
- * and updating @tlb_invalidation.seqno_recv.
+ * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences
+ * and updating @tlb_inval.seqno_recv.
*/
spinlock_t pending_lock;
/**
- * @tlb_invalidation.fence_tdr: schedules a delayed call to
+ * @tlb_inval.fence_tdr: schedules a delayed call to
* xe_gt_tlb_fence_timeout after the timeut interval is over.
*/
struct delayed_work fence_tdr;
/** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */
struct workqueue_struct *job_wq;
- /** @tlb_invalidation.lock: protects TLB invalidation fences */
+ /** @tlb_inval.lock: protects TLB invalidation fences */
spinlock_t lock;
- } tlb_invalidation;
+ } tlb_inval;
/**
* @ccs_mode: Number of compute engines enabled.
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 3f4e6a46ff16..9131d121d941 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -26,7 +26,7 @@
#include "xe_gt_sriov_pf_control.h"
#include "xe_gt_sriov_pf_monitor.h"
#include "xe_gt_sriov_printk.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_guc.h"
#include "xe_guc_log.h"
#include "xe_guc_relay.h"
@@ -1416,8 +1416,7 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
ret = xe_guc_pagefault_handler(guc, payload, adj_len);
break;
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
- ret = xe_guc_tlb_invalidation_done_handler(guc, payload,
- adj_len);
+ ret = xe_guc_tlb_inval_done_handler(guc, payload, adj_len);
break;
case XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY:
ret = xe_guc_access_counter_notify_handler(guc, payload,
@@ -1618,8 +1617,7 @@ static void g2h_fast_path(struct xe_guc_ct *ct, u32 *msg, u32 len)
break;
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
__g2h_release_space(ct, len);
- ret = xe_guc_tlb_invalidation_done_handler(guc, payload,
- adj_len);
+ ret = xe_guc_tlb_inval_done_handler(guc, payload, adj_len);
break;
default:
xe_gt_warn(gt, "NOT_POSSIBLE");
diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c
index a2000307d5bf..8869ad491d99 100644
--- a/drivers/gpu/drm/xe/xe_lmtt.c
+++ b/drivers/gpu/drm/xe/xe_lmtt.c
@@ -11,7 +11,7 @@
#include "xe_assert.h"
#include "xe_bo.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_lmtt.h"
#include "xe_map.h"
#include "xe_mmio.h"
@@ -225,8 +225,8 @@ void xe_lmtt_init_hw(struct xe_lmtt *lmtt)
static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
{
- struct xe_gt_tlb_invalidation_fence fences[XE_MAX_GT_PER_TILE];
- struct xe_gt_tlb_invalidation_fence *fence = fences;
+ struct xe_gt_tlb_inval_fence fences[XE_MAX_GT_PER_TILE];
+ struct xe_gt_tlb_inval_fence *fence = fences;
struct xe_tile *tile = lmtt_to_tile(lmtt);
struct xe_gt *gt;
int result = 0;
@@ -234,8 +234,8 @@ static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
u8 id;
for_each_gt_on_tile(gt, tile, id) {
- xe_gt_tlb_invalidation_fence_init(gt, fence, true);
- err = xe_gt_tlb_invalidation_all(gt, fence);
+ xe_gt_tlb_inval_fence_init(gt, fence, true);
+ err = xe_gt_tlb_inval_all(gt, fence);
result = result ?: err;
fence++;
}
@@ -249,7 +249,7 @@ static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
*/
fence = fences;
for_each_gt_on_tile(gt, tile, id)
- xe_gt_tlb_invalidation_fence_wait(fence++);
+ xe_gt_tlb_inval_fence_wait(fence++);
return result;
}
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 52d46c66ae1e..2f1789d377aa 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -55,7 +55,7 @@ static const struct xe_graphics_desc graphics_xelp = {
};
#define XE_HP_FEATURES \
- .has_range_tlb_invalidation = true, \
+ .has_range_tlb_inval = true, \
.va_bits = 48, \
.vm_max_level = 3
@@ -103,7 +103,7 @@ static const struct xe_graphics_desc graphics_xelpg = {
.has_asid = 1, \
.has_atomic_enable_pte_bit = 1, \
.has_flat_ccs = 1, \
- .has_range_tlb_invalidation = 1, \
+ .has_range_tlb_inval = 1, \
.has_usm = 1, \
.has_64bit_timestamp = 1, \
.va_bits = 48, \
@@ -674,7 +674,7 @@ static int xe_info_init(struct xe_device *xe,
/* Runtime detection may change this later */
xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
- xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation;
+ xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
xe->info.has_usm = graphics_desc->has_usm;
xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 4de6f69ed975..b63002fc0f67 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -60,7 +60,7 @@ struct xe_graphics_desc {
u8 has_atomic_enable_pte_bit:1;
u8 has_flat_ccs:1;
u8 has_indirect_ring_state:1;
- u8 has_range_tlb_invalidation:1;
+ u8 has_range_tlb_inval:1;
u8 has_usm:1;
u8 has_64bit_timestamp:1;
};
diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c
index 10c8a1bcb86e..0c9f7fe42af6 100644
--- a/drivers/gpu/drm/xe/xe_svm.c
+++ b/drivers/gpu/drm/xe/xe_svm.c
@@ -7,7 +7,7 @@
#include "xe_bo.h"
#include "xe_gt_stats.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_migrate.h"
#include "xe_module.h"
#include "xe_pm.h"
@@ -225,7 +225,7 @@ static void xe_svm_invalidate(struct drm_gpusvm *gpusvm,
xe_device_wmb(xe);
- err = xe_vm_range_tilemask_tlb_invalidation(vm, adj_start, adj_end, tile_mask);
+ err = xe_vm_range_tilemask_tlb_inval(vm, adj_start, adj_end, tile_mask);
WARN_ON_ONCE(err);
range_notifier_event_end:
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 21486a6f693a..36538f50d06f 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -14,7 +14,7 @@
#include "xe_exec_queue_types.h"
#include "xe_gpu_scheduler_types.h"
-#include "xe_gt_tlb_invalidation_types.h"
+#include "xe_gt_tlb_inval_types.h"
#include "xe_gt_types.h"
#include "xe_guc_exec_queue_types.h"
#include "xe_sched_job.h"
@@ -25,13 +25,13 @@
#define __dev_name_gt(gt) __dev_name_xe(gt_to_xe((gt)))
#define __dev_name_eq(q) __dev_name_gt((q)->gt)
-DECLARE_EVENT_CLASS(xe_gt_tlb_invalidation_fence,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence),
+DECLARE_EVENT_CLASS(xe_gt_tlb_inval_fence,
+ TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
TP_ARGS(xe, fence),
TP_STRUCT__entry(
__string(dev, __dev_name_xe(xe))
- __field(struct xe_gt_tlb_invalidation_fence *, fence)
+ __field(struct xe_gt_tlb_inval_fence *, fence)
__field(int, seqno)
),
@@ -45,23 +45,23 @@ DECLARE_EVENT_CLASS(xe_gt_tlb_invalidation_fence,
__get_str(dev), __entry->fence, __entry->seqno)
);
-DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_send,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence),
+DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_send,
+ TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_recv,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence),
+DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_recv,
+ TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_signal,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence),
+DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_signal,
+ TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_timeout,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_invalidation_fence *fence),
+DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_timeout,
+ TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 432ea325677d..a4011a1e5e2c 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -28,7 +28,7 @@
#include "xe_drm_client.h"
#include "xe_exec_queue.h"
#include "xe_gt_pagefault.h"
-#include "xe_gt_tlb_invalidation.h"
+#include "xe_gt_tlb_inval.h"
#include "xe_migrate.h"
#include "xe_pat.h"
#include "xe_pm.h"
@@ -1850,7 +1850,7 @@ static void xe_vm_close(struct xe_vm *vm)
xe_pt_clear(xe, vm->pt_root[id]);
for_each_gt(gt, xe, id)
- xe_gt_tlb_invalidation_vm(gt, vm);
+ xe_gt_tlb_inval_vm(gt, vm);
}
}
@@ -3843,7 +3843,7 @@ void xe_vm_unlock(struct xe_vm *vm)
}
/**
- * xe_vm_range_tilemask_tlb_invalidation - Issue a TLB invalidation on this tilemask for an
+ * xe_vm_range_tilemask_tlb_inval - Issue a TLB invalidation on this tilemask for an
* address range
* @vm: The VM
* @start: start address
@@ -3854,10 +3854,11 @@ void xe_vm_unlock(struct xe_vm *vm)
*
* Returns 0 for success, negative error code otherwise.
*/
-int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start,
- u64 end, u8 tile_mask)
+int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
+ u64 end, u8 tile_mask)
{
- struct xe_gt_tlb_invalidation_fence fence[XE_MAX_TILES_PER_DEVICE * XE_MAX_GT_PER_TILE];
+ struct xe_gt_tlb_inval_fence
+ fence[XE_MAX_TILES_PER_DEVICE * XE_MAX_GT_PER_TILE];
struct xe_tile *tile;
u32 fence_id = 0;
u8 id;
@@ -3867,39 +3868,34 @@ int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start,
return 0;
for_each_tile(tile, vm->xe, id) {
- if (tile_mask & BIT(id)) {
- xe_gt_tlb_invalidation_fence_init(tile->primary_gt,
- &fence[fence_id], true);
-
- err = xe_gt_tlb_invalidation_range(tile->primary_gt,
- &fence[fence_id],
- start,
- end,
- vm->usm.asid);
- if (err)
- goto wait;
- ++fence_id;
+ if (!(tile_mask & BIT(id)))
+ continue;
- if (!tile->media_gt)
- continue;
+ xe_gt_tlb_inval_fence_init(tile->primary_gt,
+ &fence[fence_id], true);
- xe_gt_tlb_invalidation_fence_init(tile->media_gt,
- &fence[fence_id], true);
+ err = xe_gt_tlb_inval_range(tile->primary_gt, &fence[fence_id],
+ start, end, vm->usm.asid);
+ if (err)
+ goto wait;
+ ++fence_id;
- err = xe_gt_tlb_invalidation_range(tile->media_gt,
- &fence[fence_id],
- start,
- end,
- vm->usm.asid);
- if (err)
- goto wait;
- ++fence_id;
- }
+ if (!tile->media_gt)
+ continue;
+
+ xe_gt_tlb_inval_fence_init(tile->media_gt,
+ &fence[fence_id], true);
+
+ err = xe_gt_tlb_inval_range(tile->media_gt, &fence[fence_id],
+ start, end, vm->usm.asid);
+ if (err)
+ goto wait;
+ ++fence_id;
}
wait:
for (id = 0; id < fence_id; ++id)
- xe_gt_tlb_invalidation_fence_wait(&fence[id]);
+ xe_gt_tlb_inval_fence_wait(&fence[id]);
return err;
}
@@ -3958,8 +3954,8 @@ int xe_vm_invalidate_vma(struct xe_vma *vma)
xe_device_wmb(xe);
- ret = xe_vm_range_tilemask_tlb_invalidation(xe_vma_vm(vma), xe_vma_start(vma),
- xe_vma_end(vma), tile_mask);
+ ret = xe_vm_range_tilemask_tlb_inval(xe_vma_vm(vma), xe_vma_start(vma),
+ xe_vma_end(vma), tile_mask);
/* WRITE_ONCE pairs with READ_ONCE in xe_vm_has_valid_gpu_mapping() */
WRITE_ONCE(vma->tile_invalidated, vma->tile_mask);
diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
index 3475a118f666..fade8ad92bad 100644
--- a/drivers/gpu/drm/xe/xe_vm.h
+++ b/drivers/gpu/drm/xe/xe_vm.h
@@ -228,8 +228,8 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
struct xe_svm_range *range);
-int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start,
- u64 end, u8 tile_mask);
+int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
+ u64 end, u8 tile_mask);
int xe_vm_invalidate_vma(struct xe_vma *vma);
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 3/8] drm/xe: Add xe_tlb_inval structure
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
2025-07-30 20:45 ` [PATCH 1/8] drm/xe: Move explicit CT lock in TLB invalidation sequence stuartsummers
2025-07-30 20:45 ` [PATCH 2/8] drm/xe: s/tlb_invalidation/tlb_inval stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-30 20:45 ` [PATCH 4/8] drm/xe: Add xe_gt_tlb_invalidation_done_handler stuartsummers
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
Extract TLB invalidation state into a structure to decouple TLB
invalidations from the GT, allowing the structure to be embedded
anywhere in the driver.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h | 32 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_gt_types.h | 31 ++-------------------
2 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
index 919430359103..8b37d0b8f545 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
@@ -6,10 +6,42 @@
#ifndef _XE_GT_TLB_INVAL_TYPES_H_
#define _XE_GT_TLB_INVAL_TYPES_H_
+#include <linux/workqueue.h>
#include <linux/dma-fence.h>
struct xe_gt;
+/** struct xe_tlb_inval - TLB invalidation client */
+struct xe_tlb_inval {
+ /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
+#define TLB_INVALIDATION_SEQNO_MAX 0x100000
+ int seqno;
+ /**
+ * @tlb_inval.seqno_recv: last received TLB invalidation seqno,
+ * protected by CT lock
+ */
+ int seqno_recv;
+ /**
+ * @tlb_inval.pending_fences: list of pending fences waiting TLB
+ * invaliations, protected by CT lock
+ */
+ struct list_head pending_fences;
+ /**
+ * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences
+ * and updating @tlb_inval.seqno_recv.
+ */
+ spinlock_t pending_lock;
+ /**
+ * @tlb_inval.fence_tdr: schedules a delayed call to
+ * xe_gt_tlb_fence_timeout after the timeut interval is over.
+ */
+ struct delayed_work fence_tdr;
+ /** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */
+ struct workqueue_struct *job_wq;
+ /** @tlb_inval.lock: protects TLB invalidation fences */
+ spinlock_t lock;
+};
+
/**
* struct xe_gt_tlb_inval_fence - XE GT TLB invalidation fence
*
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 38cdca4107c8..ed21bd63b001 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -12,6 +12,7 @@
#include "xe_gt_sriov_pf_types.h"
#include "xe_gt_sriov_vf_types.h"
#include "xe_gt_stats_types.h"
+#include "xe_gt_tlb_inval_types.h"
#include "xe_hw_engine_types.h"
#include "xe_hw_fence_types.h"
#include "xe_oa_types.h"
@@ -186,35 +187,7 @@ struct xe_gt {
} reset;
/** @tlb_inval: TLB invalidation state */
- struct {
- /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
-#define TLB_INVALIDATION_SEQNO_MAX 0x100000
- int seqno;
- /**
- * @tlb_inval.seqno_recv: last received TLB invalidation seqno,
- * protected by CT lock
- */
- int seqno_recv;
- /**
- * @tlb_inval.pending_fences: list of pending fences waiting TLB
- * invaliations, protected by CT lock
- */
- struct list_head pending_fences;
- /**
- * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences
- * and updating @tlb_inval.seqno_recv.
- */
- spinlock_t pending_lock;
- /**
- * @tlb_inval.fence_tdr: schedules a delayed call to
- * xe_gt_tlb_fence_timeout after the timeut interval is over.
- */
- struct delayed_work fence_tdr;
- /** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */
- struct workqueue_struct *job_wq;
- /** @tlb_inval.lock: protects TLB invalidation fences */
- spinlock_t lock;
- } tlb_inval;
+ struct xe_tlb_inval tlb_inval;
/**
* @ccs_mode: Number of compute engines enabled.
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 4/8] drm/xe: Add xe_gt_tlb_invalidation_done_handler
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (2 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 3/8] drm/xe: Add xe_tlb_inval structure stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-30 20:45 ` [PATCH 5/8] drm/xe: Decouple TLB invalidations from GT stuartsummers
` (7 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
Decouple GT TLB seqno handling from G2H handler.
v2:
- Add kernel doc
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_gt_tlb_inval.c | 47 ++++++++++++++++++----------
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval.c b/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
index 188e09124887..3e69aab4a01d 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
@@ -483,27 +483,18 @@ void xe_gt_tlb_inval_vm(struct xe_gt *gt, struct xe_vm *vm)
}
/**
- * xe_guc_tlb_inval_done_handler - TLB invalidation done handler
- * @guc: guc
- * @msg: message indicating TLB invalidation done
- * @len: length of message
- *
- * Parse seqno of TLB invalidation, wake any waiters for seqno, and signal any
- * invalidation fences for seqno. Algorithm for this depends on seqno being
- * received in-order and asserts this assumption.
+ * xe_gt_tlb_inval_done_handler - GT TLB invalidation done handler
+ * @gt: gt
+ * @seqno: seqno of invalidation that is done
*
- * Return: 0 on success, -EPROTO for malformed messages.
+ * Update recv seqno, signal any GT TLB invalidation fences, and restart TDR
*/
-int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
+static void xe_gt_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
{
- struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = gt_to_xe(gt);
struct xe_gt_tlb_inval_fence *fence, *next;
unsigned long flags;
- if (unlikely(len != 1))
- return -EPROTO;
-
/*
* This can also be run both directly from the IRQ handler and also in
* process_g2h_msg(). Only one may process any individual CT message,
@@ -520,12 +511,12 @@ int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
* process_g2h_msg().
*/
spin_lock_irqsave(>->tlb_inval.pending_lock, flags);
- if (tlb_inval_seqno_past(gt, msg[0])) {
+ if (tlb_inval_seqno_past(gt, seqno)) {
spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
- return 0;
+ return;
}
- WRITE_ONCE(gt->tlb_inval.seqno_recv, msg[0]);
+ WRITE_ONCE(gt->tlb_inval.seqno_recv, seqno);
list_for_each_entry_safe(fence, next,
>->tlb_inval.pending_fences, link) {
@@ -545,6 +536,28 @@ int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
cancel_delayed_work(>->tlb_inval.fence_tdr);
spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
+}
+
+/**
+ * xe_guc_tlb_inval_done_handler - TLB invalidation done handler
+ * @guc: guc
+ * @msg: message indicating TLB invalidation done
+ * @len: length of message
+ *
+ * Parse seqno of TLB invalidation, wake any waiters for seqno, and signal any
+ * invalidation fences for seqno. Algorithm for this depends on seqno being
+ * received in-order and asserts this assumption.
+ *
+ * Return: 0 on success, -EPROTO for malformed messages.
+ */
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
+{
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ if (unlikely(len != 1))
+ return -EPROTO;
+
+ xe_gt_tlb_inval_done_handler(gt, msg[0]);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 5/8] drm/xe: Decouple TLB invalidations from GT
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (3 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 4/8] drm/xe: Add xe_gt_tlb_invalidation_done_handler stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-31 17:05 ` Summers, Stuart
2025-07-30 20:45 ` [PATCH 6/8] drm/xe: Prep TLB invalidation fence before sending stuartsummers
` (6 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
Decouple TLB invalidations from the GT by updating the TLB invalidation
layer to accept a `struct xe_tlb_inval` instead of a `struct xe_gt`.
Also, rename *gt_tlb* to *tlb*. The internals of the TLB invalidation
code still operate on a GT, but this is now hidden from the rest of the
driver.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/Makefile | 4 +-
drivers/gpu/drm/xe/xe_ggtt.c | 4 +-
drivers/gpu/drm/xe/xe_gt.c | 6 +-
drivers/gpu/drm/xe/xe_gt_tlb_inval.h | 40 -----
drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h | 34 ----
drivers/gpu/drm/xe/xe_gt_types.h | 2 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 2 +-
drivers/gpu/drm/xe/xe_lmtt.c | 12 +-
drivers/gpu/drm/xe/xe_migrate.h | 10 +-
drivers/gpu/drm/xe/xe_pt.c | 63 ++++---
drivers/gpu/drm/xe/xe_svm.c | 1 -
.../xe/{xe_gt_tlb_inval.c => xe_tlb_inval.c} | 143 ++++++++--------
drivers/gpu/drm/xe/xe_tlb_inval.h | 41 +++++
..._gt_tlb_inval_job.c => xe_tlb_inval_job.c} | 154 +++++++++---------
drivers/gpu/drm/xe/xe_tlb_inval_job.h | 34 ++++
...tlb_inval_types.h => xe_tlb_inval_types.h} | 35 ++--
drivers/gpu/drm/xe/xe_trace.h | 24 +--
drivers/gpu/drm/xe/xe_vm.c | 26 +--
18 files changed, 331 insertions(+), 304 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval.h
delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h
rename drivers/gpu/drm/xe/{xe_gt_tlb_inval.c => xe_tlb_inval.c} (79%)
create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval.h
rename drivers/gpu/drm/xe/{xe_gt_tlb_inval_job.c => xe_tlb_inval_job.c} (51%)
create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval_job.h
rename drivers/gpu/drm/xe/{xe_gt_tlb_inval_types.h => xe_tlb_inval_types.h} (54%)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 0a36b2463434..e4a363489072 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -61,8 +61,6 @@ xe-y += xe_bb.o \
xe_gt_pagefault.o \
xe_gt_sysfs.o \
xe_gt_throttle.o \
- xe_gt_tlb_inval.o \
- xe_gt_tlb_inval_job.o \
xe_gt_topology.o \
xe_guc.o \
xe_guc_ads.o \
@@ -117,6 +115,8 @@ xe-y += xe_bb.o \
xe_sync.o \
xe_tile.o \
xe_tile_sysfs.o \
+ xe_tlb_inval.o \
+ xe_tlb_inval_job.o \
xe_trace.o \
xe_trace_bo.o \
xe_trace_guc.o \
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 78d426778151..d4d1de3ed7b3 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -23,13 +23,13 @@
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_printk.h"
-#include "xe_gt_tlb_inval.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_pm.h"
#include "xe_res_cursor.h"
#include "xe_sriov.h"
#include "xe_tile_sriov_vf.h"
+#include "xe_tlb_inval.h"
#include "xe_wa.h"
#include "xe_wopcm.h"
@@ -438,7 +438,7 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
if (!gt)
return;
- err = xe_gt_tlb_inval_ggtt(gt);
+ err = xe_tlb_inval_ggtt(>->tlb_inval);
xe_gt_WARN(gt, err, "Failed to invalidate GGTT (%pe)", ERR_PTR(err));
}
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 95ed95d38494..98384f2545dc 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -37,7 +37,6 @@
#include "xe_gt_sriov_pf.h"
#include "xe_gt_sriov_vf.h"
#include "xe_gt_sysfs.h"
-#include "xe_gt_tlb_inval.h"
#include "xe_gt_topology.h"
#include "xe_guc_exec_queue_types.h"
#include "xe_guc_pc.h"
@@ -57,6 +56,7 @@
#include "xe_sa.h"
#include "xe_sched_job.h"
#include "xe_sriov.h"
+#include "xe_tlb_inval.h"
#include "xe_tuning.h"
#include "xe_uc.h"
#include "xe_uc_fw.h"
@@ -840,7 +840,7 @@ static int gt_reset(struct xe_gt *gt)
xe_uc_stop(>->uc);
- xe_gt_tlb_inval_reset(gt);
+ xe_tlb_inval_reset(>->tlb_inval);
err = do_gt_reset(gt);
if (err)
@@ -1054,5 +1054,5 @@ void xe_gt_declare_wedged(struct xe_gt *gt)
xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode);
xe_uc_declare_wedged(>->uc);
- xe_gt_tlb_inval_reset(gt);
+ xe_tlb_inval_reset(>->tlb_inval);
}
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval.h
deleted file mode 100644
index 801d4ecf88f0..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef _XE_GT_TLB_INVAL_H_
-#define _XE_GT_TLB_INVAL_H_
-
-#include <linux/types.h>
-
-#include "xe_gt_tlb_inval_types.h"
-
-struct xe_gt;
-struct xe_guc;
-struct xe_vm;
-struct xe_vma;
-
-int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
-
-void xe_gt_tlb_inval_reset(struct xe_gt *gt);
-int xe_gt_tlb_inval_ggtt(struct xe_gt *gt);
-void xe_gt_tlb_inval_vm(struct xe_gt *gt, struct xe_vm *vm);
-int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence);
-int xe_gt_tlb_inval_range(struct xe_gt *gt,
- struct xe_gt_tlb_inval_fence *fence,
- u64 start, u64 end, u32 asid);
-int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
-
-void xe_gt_tlb_inval_fence_init(struct xe_gt *gt,
- struct xe_gt_tlb_inval_fence *fence,
- bool stack);
-void xe_gt_tlb_inval_fence_signal(struct xe_gt_tlb_inval_fence *fence);
-
-static inline void
-xe_gt_tlb_inval_fence_wait(struct xe_gt_tlb_inval_fence *fence)
-{
- dma_fence_wait(&fence->base, false);
-}
-
-#endif /* _XE_GT_TLB_INVAL_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h
deleted file mode 100644
index 883896194a34..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2025 Intel Corporation
- */
-
-#ifndef _XE_GT_TLB_INVAL_JOB_H_
-#define _XE_GT_TLB_INVAL_JOB_H_
-
-#include <linux/types.h>
-
-struct dma_fence;
-struct drm_sched_job;
-struct kref;
-struct xe_exec_queue;
-struct xe_gt;
-struct xe_gt_tlb_inval_job;
-struct xe_migrate;
-
-struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
- struct xe_gt *gt,
- u64 start, u64 end,
- u32 asid);
-
-int xe_gt_tlb_inval_job_alloc_dep(struct xe_gt_tlb_inval_job *job);
-
-struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
- struct xe_migrate *m,
- struct dma_fence *fence);
-
-void xe_gt_tlb_inval_job_get(struct xe_gt_tlb_inval_job *job);
-
-void xe_gt_tlb_inval_job_put(struct xe_gt_tlb_inval_job *job);
-
-#endif
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index ed21bd63b001..cdba2e9f584b 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -12,12 +12,12 @@
#include "xe_gt_sriov_pf_types.h"
#include "xe_gt_sriov_vf_types.h"
#include "xe_gt_stats_types.h"
-#include "xe_gt_tlb_inval_types.h"
#include "xe_hw_engine_types.h"
#include "xe_hw_fence_types.h"
#include "xe_oa_types.h"
#include "xe_reg_sr_types.h"
#include "xe_sa_types.h"
+#include "xe_tlb_inval_types.h"
#include "xe_uc_types.h"
struct xe_exec_queue_ops;
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 9131d121d941..5f38041cff4c 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -26,13 +26,13 @@
#include "xe_gt_sriov_pf_control.h"
#include "xe_gt_sriov_pf_monitor.h"
#include "xe_gt_sriov_printk.h"
-#include "xe_gt_tlb_inval.h"
#include "xe_guc.h"
#include "xe_guc_log.h"
#include "xe_guc_relay.h"
#include "xe_guc_submit.h"
#include "xe_map.h"
#include "xe_pm.h"
+#include "xe_tlb_inval.h"
#include "xe_trace_guc.h"
static void receive_g2h(struct xe_guc_ct *ct);
diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c
index 8869ad491d99..16fcee64025b 100644
--- a/drivers/gpu/drm/xe/xe_lmtt.c
+++ b/drivers/gpu/drm/xe/xe_lmtt.c
@@ -11,7 +11,7 @@
#include "xe_assert.h"
#include "xe_bo.h"
-#include "xe_gt_tlb_inval.h"
+#include "xe_tlb_inval.h"
#include "xe_lmtt.h"
#include "xe_map.h"
#include "xe_mmio.h"
@@ -225,8 +225,8 @@ void xe_lmtt_init_hw(struct xe_lmtt *lmtt)
static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
{
- struct xe_gt_tlb_inval_fence fences[XE_MAX_GT_PER_TILE];
- struct xe_gt_tlb_inval_fence *fence = fences;
+ struct xe_tlb_inval_fence fences[XE_MAX_GT_PER_TILE];
+ struct xe_tlb_inval_fence *fence = fences;
struct xe_tile *tile = lmtt_to_tile(lmtt);
struct xe_gt *gt;
int result = 0;
@@ -234,8 +234,8 @@ static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
u8 id;
for_each_gt_on_tile(gt, tile, id) {
- xe_gt_tlb_inval_fence_init(gt, fence, true);
- err = xe_gt_tlb_inval_all(gt, fence);
+ xe_tlb_inval_fence_init(>->tlb_inval, fence, true);
+ err = xe_tlb_inval_all(>->tlb_inval, fence);
result = result ?: err;
fence++;
}
@@ -249,7 +249,7 @@ static int lmtt_invalidate_hw(struct xe_lmtt *lmtt)
*/
fence = fences;
for_each_gt_on_tile(gt, tile, id)
- xe_gt_tlb_inval_fence_wait(fence++);
+ xe_tlb_inval_fence_wait(fence++);
return result;
}
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index e81ea6b27fb5..68d52022cfab 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -14,7 +14,7 @@ struct ttm_resource;
struct xe_bo;
struct xe_gt;
-struct xe_gt_tlb_inval_job;
+struct xe_tlb_inval_job;
struct xe_exec_queue;
struct xe_migrate;
struct xe_migrate_pt_update;
@@ -93,13 +93,13 @@ struct xe_migrate_pt_update {
/** @job: The job if a GPU page-table update. NULL otherwise */
struct xe_sched_job *job;
/**
- * @ijob: The GT TLB invalidation job for primary tile. NULL otherwise
+ * @ijob: The TLB invalidation job for primary GT. NULL otherwise
*/
- struct xe_gt_tlb_inval_job *ijob;
+ struct xe_tlb_inval_job *ijob;
/**
- * @mjob: The GT TLB invalidation job for media tile. NULL otherwise
+ * @mjob: The TLB invalidation job for media GT. NULL otherwise
*/
- struct xe_gt_tlb_inval_job *mjob;
+ struct xe_tlb_inval_job *mjob;
/** @tile_id: Tile ID of the update */
u8 tile_id;
};
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 330cc0f54a3f..f6bae5bbf95f 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -13,7 +13,7 @@
#include "xe_drm_client.h"
#include "xe_exec_queue.h"
#include "xe_gt.h"
-#include "xe_gt_tlb_inval_job.h"
+#include "xe_tlb_inval_job.h"
#include "xe_migrate.h"
#include "xe_pt_types.h"
#include "xe_pt_walk.h"
@@ -21,6 +21,7 @@
#include "xe_sched_job.h"
#include "xe_sync.h"
#include "xe_svm.h"
+#include "xe_tlb_inval_job.h"
#include "xe_trace.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_vm.h"
@@ -1261,8 +1262,8 @@ static int op_add_deps(struct xe_vm *vm, struct xe_vma_op *op,
}
static int xe_pt_vm_dependencies(struct xe_sched_job *job,
- struct xe_gt_tlb_inval_job *ijob,
- struct xe_gt_tlb_inval_job *mjob,
+ struct xe_tlb_inval_job *ijob,
+ struct xe_tlb_inval_job *mjob,
struct xe_vm *vm,
struct xe_vma_ops *vops,
struct xe_vm_pgtable_update_ops *pt_update_ops,
@@ -1332,13 +1333,13 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
if (job) {
if (ijob) {
- err = xe_gt_tlb_inval_job_alloc_dep(ijob);
+ err = xe_tlb_inval_job_alloc_dep(ijob);
if (err)
return err;
}
if (mjob) {
- err = xe_gt_tlb_inval_job_alloc_dep(mjob);
+ err = xe_tlb_inval_job_alloc_dep(mjob);
if (err)
return err;
}
@@ -2338,6 +2339,15 @@ static const struct xe_migrate_pt_update_ops svm_migrate_ops = {
static const struct xe_migrate_pt_update_ops svm_migrate_ops;
#endif
+static struct xe_dep_scheduler *to_dep_scheduler(struct xe_exec_queue *q,
+ struct xe_gt *gt)
+{
+ if (xe_gt_is_media_type(gt))
+ return q->tlb_inval[XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT].dep_scheduler;
+
+ return q->tlb_inval[XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT].dep_scheduler;
+}
+
/**
* xe_pt_update_ops_run() - Run PT update operations
* @tile: Tile of PT update operations
@@ -2356,7 +2366,7 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
struct xe_vm_pgtable_update_ops *pt_update_ops =
&vops->pt_update_ops[tile->id];
struct dma_fence *fence, *ifence, *mfence;
- struct xe_gt_tlb_inval_job *ijob = NULL, *mjob = NULL;
+ struct xe_tlb_inval_job *ijob = NULL, *mjob = NULL;
struct dma_fence **fences = NULL;
struct dma_fence_array *cf = NULL;
struct xe_range_fence *rfence;
@@ -2388,11 +2398,15 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
#endif
if (pt_update_ops->needs_invalidation) {
- ijob = xe_gt_tlb_inval_job_create(pt_update_ops->q,
- tile->primary_gt,
- pt_update_ops->start,
- pt_update_ops->last,
- vm->usm.asid);
+ struct xe_exec_queue *q = pt_update_ops->q;
+ struct xe_dep_scheduler *dep_scheduler =
+ to_dep_scheduler(q, tile->primary_gt);
+
+ ijob = xe_tlb_inval_job_create(q, &tile->primary_gt->tlb_inval,
+ dep_scheduler,
+ pt_update_ops->start,
+ pt_update_ops->last,
+ vm->usm.asid);
if (IS_ERR(ijob)) {
err = PTR_ERR(ijob);
goto kill_vm_tile1;
@@ -2400,11 +2414,14 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
update.ijob = ijob;
if (tile->media_gt) {
- mjob = xe_gt_tlb_inval_job_create(pt_update_ops->q,
- tile->media_gt,
- pt_update_ops->start,
- pt_update_ops->last,
- vm->usm.asid);
+ dep_scheduler = to_dep_scheduler(q, tile->media_gt);
+
+ mjob = xe_tlb_inval_job_create(q,
+ &tile->media_gt->tlb_inval,
+ dep_scheduler,
+ pt_update_ops->start,
+ pt_update_ops->last,
+ vm->usm.asid);
if (IS_ERR(mjob)) {
err = PTR_ERR(mjob);
goto free_ijob;
@@ -2455,13 +2472,13 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
if (ijob) {
struct dma_fence *__fence;
- ifence = xe_gt_tlb_inval_job_push(ijob, tile->migrate, fence);
+ ifence = xe_tlb_inval_job_push(ijob, tile->migrate, fence);
__fence = ifence;
if (mjob) {
fences[0] = ifence;
- mfence = xe_gt_tlb_inval_job_push(mjob, tile->migrate,
- fence);
+ mfence = xe_tlb_inval_job_push(mjob, tile->migrate,
+ fence);
fences[1] = mfence;
dma_fence_array_init(cf, 2, fences,
@@ -2504,8 +2521,8 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
if (pt_update_ops->needs_userptr_lock)
up_read(&vm->userptr.notifier_lock);
- xe_gt_tlb_inval_job_put(mjob);
- xe_gt_tlb_inval_job_put(ijob);
+ xe_tlb_inval_job_put(mjob);
+ xe_tlb_inval_job_put(ijob);
return fence;
@@ -2514,8 +2531,8 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
free_ijob:
kfree(cf);
kfree(fences);
- xe_gt_tlb_inval_job_put(mjob);
- xe_gt_tlb_inval_job_put(ijob);
+ xe_tlb_inval_job_put(mjob);
+ xe_tlb_inval_job_put(ijob);
kill_vm_tile1:
if (err != -EAGAIN && err != -ENODATA && tile->id)
xe_vm_kill(vops->vm, false);
diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c
index 0c9f7fe42af6..b8f8b1a577b6 100644
--- a/drivers/gpu/drm/xe/xe_svm.c
+++ b/drivers/gpu/drm/xe/xe_svm.c
@@ -7,7 +7,6 @@
#include "xe_bo.h"
#include "xe_gt_stats.h"
-#include "xe_gt_tlb_inval.h"
#include "xe_migrate.h"
#include "xe_module.h"
#include "xe_pm.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
similarity index 79%
rename from drivers/gpu/drm/xe/xe_gt_tlb_inval.c
rename to drivers/gpu/drm/xe/xe_tlb_inval.c
index 3e69aab4a01d..288960ea0caa 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -13,7 +13,7 @@
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_gt_stats.h"
-#include "xe_gt_tlb_inval.h"
+#include "xe_tlb_inval.h"
#include "xe_mmio.h"
#include "xe_pm.h"
#include "xe_sriov.h"
@@ -38,40 +38,46 @@ static long tlb_timeout_jiffies(struct xe_gt *gt)
return hw_tlb_timeout + 2 * delay;
}
-static void xe_gt_tlb_inval_fence_fini(struct xe_gt_tlb_inval_fence *fence)
+static void xe_tlb_inval_fence_fini(struct xe_tlb_inval_fence *fence)
{
- if (WARN_ON_ONCE(!fence->gt))
+ struct xe_gt *gt;
+
+ if (WARN_ON_ONCE(!fence->tlb_inval))
return;
- xe_pm_runtime_put(gt_to_xe(fence->gt));
- fence->gt = NULL; /* fini() should be called once */
+ gt = fence->tlb_inval->private;
+ xe_pm_runtime_put(gt_to_xe(gt));
+ fence->tlb_inval = NULL; /* fini() should be called once */
}
static void
-__inval_fence_signal(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence)
+__inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
{
bool stack = test_bit(FENCE_STACK_BIT, &fence->base.flags);
- trace_xe_gt_tlb_inval_fence_signal(xe, fence);
- xe_gt_tlb_inval_fence_fini(fence);
+ trace_xe_tlb_inval_fence_signal(xe, fence);
+ xe_tlb_inval_fence_fini(fence);
dma_fence_signal(&fence->base);
if (!stack)
dma_fence_put(&fence->base);
}
static void
-inval_fence_signal(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence)
+inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
{
list_del(&fence->link);
__inval_fence_signal(xe, fence);
}
-void xe_gt_tlb_inval_fence_signal(struct xe_gt_tlb_inval_fence *fence)
+void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence)
{
- if (WARN_ON_ONCE(!fence->gt))
+ struct xe_gt *gt;
+
+ if (WARN_ON_ONCE(!fence->tlb_inval))
return;
- __inval_fence_signal(gt_to_xe(fence->gt), fence);
+ gt = fence->tlb_inval->private;
+ __inval_fence_signal(gt_to_xe(gt), fence);
}
static void xe_gt_tlb_fence_timeout(struct work_struct *work)
@@ -79,7 +85,7 @@ static void xe_gt_tlb_fence_timeout(struct work_struct *work)
struct xe_gt *gt = container_of(work, struct xe_gt,
tlb_inval.fence_tdr.work);
struct xe_device *xe = gt_to_xe(gt);
- struct xe_gt_tlb_inval_fence *fence, *next;
+ struct xe_tlb_inval_fence *fence, *next;
LNL_FLUSH_WORK(>->uc.guc.ct.g2h_worker);
@@ -92,7 +98,7 @@ static void xe_gt_tlb_fence_timeout(struct work_struct *work)
if (msecs_to_jiffies(since_inval_ms) < tlb_timeout_jiffies(gt))
break;
- trace_xe_gt_tlb_inval_fence_timeout(xe, fence);
+ trace_xe_tlb_inval_fence_timeout(xe, fence);
xe_gt_err(gt, "TLB invalidation fence timeout, seqno=%d recv=%d",
fence->seqno, gt->tlb_inval.seqno_recv);
@@ -107,16 +113,17 @@ static void xe_gt_tlb_fence_timeout(struct work_struct *work)
}
/**
- * xe_gt_tlb_inval_init_early - Initialize GT TLB invalidation state
+ * xe_tlb_inval_init_early - Initialize TLB invalidation state
* @gt: GT structure
*
- * Initialize GT TLB invalidation state, purely software initialization, should
+ * Initialize TLB invalidation state, purely software initialization, should
* be called once during driver load.
*
* Return: 0 on success, negative error code on error.
*/
int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
{
+ gt->tlb_inval.private = gt;
gt->tlb_inval.seqno = 1;
INIT_LIST_HEAD(>->tlb_inval.pending_fences);
spin_lock_init(>->tlb_inval.pending_lock);
@@ -134,14 +141,15 @@ int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
}
/**
- * xe_gt_tlb_inval_reset - Initialize GT TLB invalidation reset
- * @gt: GT structure
+ * xe_tlb_inval_reset - Initialize TLB invalidation reset
+ * @tlb_inval: TLB invalidation client
*
* Signal any pending invalidation fences, should be called during a GT reset
*/
-void xe_gt_tlb_inval_reset(struct xe_gt *gt)
+void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval)
{
- struct xe_gt_tlb_inval_fence *fence, *next;
+ struct xe_gt *gt = tlb_inval->private;
+ struct xe_tlb_inval_fence *fence, *next;
int pending_seqno;
/*
@@ -192,7 +200,7 @@ static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
}
static int send_tlb_inval(struct xe_guc *guc,
- struct xe_gt_tlb_inval_fence *fence,
+ struct xe_tlb_inval_fence *fence,
u32 *action, int len)
{
struct xe_gt *gt = guc_to_gt(guc);
@@ -210,7 +218,7 @@ static int send_tlb_inval(struct xe_guc *guc,
seqno = gt->tlb_inval.seqno;
fence->seqno = seqno;
- trace_xe_gt_tlb_inval_fence_send(xe, fence);
+ trace_xe_tlb_inval_fence_send(xe, fence);
action[1] = seqno;
ret = xe_guc_ct_send(&guc->ct, action, len,
G2H_LEN_DW_TLB_INVALIDATE, 1);
@@ -254,7 +262,7 @@ static int send_tlb_inval(struct xe_guc *guc,
XE_GUC_TLB_INVAL_FLUSH_CACHE)
/**
- * xe_gt_tlb_inval_guc - Issue a TLB invalidation on this GT for the GuC
+ * xe_tlb_inval_guc - Issue a TLB invalidation on this GT for the GuC
* @gt: GT structure
* @fence: invalidation fence which will be signal on TLB invalidation
* completion
@@ -264,8 +272,8 @@ static int send_tlb_inval(struct xe_guc *guc,
*
* Return: 0 on success, negative error code on error
*/
-static int xe_gt_tlb_inval_guc(struct xe_gt *gt,
- struct xe_gt_tlb_inval_fence *fence)
+static int xe_tlb_inval_guc(struct xe_gt *gt,
+ struct xe_tlb_inval_fence *fence)
{
u32 action[] = {
XE_GUC_ACTION_TLB_INVALIDATION,
@@ -286,30 +294,31 @@ static int xe_gt_tlb_inval_guc(struct xe_gt *gt,
}
/**
- * xe_gt_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
- * @gt: GT structure
+ * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
+ * @tlb_inval: TLB invalidation client
*
* Issue a TLB invalidation for the GGTT. Completion of TLB invalidation is
* synchronous.
*
* Return: 0 on success, negative error code on error
*/
-int xe_gt_tlb_inval_ggtt(struct xe_gt *gt)
+int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
{
+ struct xe_gt *gt = tlb_inval->private;
struct xe_device *xe = gt_to_xe(gt);
unsigned int fw_ref;
if (xe_guc_ct_enabled(>->uc.guc.ct) &&
gt->uc.guc.submission_state.enabled) {
- struct xe_gt_tlb_inval_fence fence;
+ struct xe_tlb_inval_fence fence;
int ret;
- xe_gt_tlb_inval_fence_init(gt, &fence, true);
- ret = xe_gt_tlb_inval_guc(gt, &fence);
+ xe_tlb_inval_fence_init(tlb_inval, &fence, true);
+ ret = xe_tlb_inval_guc(gt, &fence);
if (ret)
return ret;
- xe_gt_tlb_inval_fence_wait(&fence);
+ xe_tlb_inval_fence_wait(&fence);
} else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
struct xe_mmio *mmio = >->mmio;
@@ -332,14 +341,17 @@ int xe_gt_tlb_inval_ggtt(struct xe_gt *gt)
return 0;
}
-static int send_tlb_inval_all(struct xe_gt *gt,
- struct xe_gt_tlb_inval_fence *fence)
+static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence)
{
u32 action[] = {
XE_GUC_ACTION_TLB_INVALIDATION_ALL,
0, /* seqno, replaced in send_tlb_inval */
MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
};
+ struct xe_gt *gt = tlb_inval->private;
+
+ xe_gt_assert(gt, fence);
return send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
}
@@ -347,19 +359,19 @@ static int send_tlb_inval_all(struct xe_gt *gt,
/**
* xe_gt_tlb_invalidation_all - Invalidate all TLBs across PF and all VFs.
* @gt: the &xe_gt structure
- * @fence: the &xe_gt_tlb_inval_fence to be signaled on completion
+ * @fence: the &xe_tlb_inval_fence to be signaled on completion
*
* Send a request to invalidate all TLBs across PF and all VFs.
*
* Return: 0 on success, negative error code on error
*/
-int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence)
+int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence)
{
+ struct xe_gt *gt = tlb_inval->private;
int err;
- xe_gt_assert(gt, gt == fence->gt);
-
- err = send_tlb_inval_all(gt, fence);
+ err = send_tlb_inval_all(tlb_inval, fence);
if (err)
xe_gt_err(gt, "TLB invalidation request failed (%pe)", ERR_PTR(err));
@@ -374,9 +386,8 @@ int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence)
#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
/**
- * xe_gt_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
- *
- * @gt: GT structure
+ * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
+ * @tlb_inval: TLB invalidation client
* @fence: invalidation fence which will be signal on TLB invalidation
* completion
* @start: start address
@@ -389,9 +400,11 @@ int xe_gt_tlb_inval_all(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence)
*
* Return: Negative error code on error, 0 on success
*/
-int xe_gt_tlb_inval_range(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence,
- u64 start, u64 end, u32 asid)
+int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence, u64 start, u64 end,
+ u32 asid)
{
+ struct xe_gt *gt = tlb_inval->private;
struct xe_device *xe = gt_to_xe(gt);
#define MAX_TLB_INVALIDATION_LEN 7
u32 action[MAX_TLB_INVALIDATION_LEN];
@@ -461,38 +474,38 @@ int xe_gt_tlb_inval_range(struct xe_gt *gt, struct xe_gt_tlb_inval_fence *fence,
}
/**
- * xe_gt_tlb_inval_vm - Issue a TLB invalidation on this GT for a VM
- * @gt: graphics tile
+ * xe_tlb_inval_vm - Issue a TLB invalidation on this GT for a VM
+ * @tlb_inval: TLB invalidation client
* @vm: VM to invalidate
*
* Invalidate entire VM's address space
*/
-void xe_gt_tlb_inval_vm(struct xe_gt *gt, struct xe_vm *vm)
+void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm)
{
- struct xe_gt_tlb_inval_fence fence;
+ struct xe_tlb_inval_fence fence;
u64 range = 1ull << vm->xe->info.va_bits;
int ret;
- xe_gt_tlb_inval_fence_init(gt, &fence, true);
+ xe_tlb_inval_fence_init(tlb_inval, &fence, true);
- ret = xe_gt_tlb_inval_range(gt, &fence, 0, range, vm->usm.asid);
+ ret = xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm->usm.asid);
if (ret < 0)
return;
- xe_gt_tlb_inval_fence_wait(&fence);
+ xe_tlb_inval_fence_wait(&fence);
}
/**
- * xe_gt_tlb_inval_done_handler - GT TLB invalidation done handler
+ * xe_tlb_inval_done_handler - TLB invalidation done handler
* @gt: gt
* @seqno: seqno of invalidation that is done
*
- * Update recv seqno, signal any GT TLB invalidation fences, and restart TDR
+ * Update recv seqno, signal any TLB invalidation fences, and restart TDR
*/
-static void xe_gt_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
+static void xe_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
{
struct xe_device *xe = gt_to_xe(gt);
- struct xe_gt_tlb_inval_fence *fence, *next;
+ struct xe_tlb_inval_fence *fence, *next;
unsigned long flags;
/*
@@ -520,7 +533,7 @@ static void xe_gt_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
list_for_each_entry_safe(fence, next,
>->tlb_inval.pending_fences, link) {
- trace_xe_gt_tlb_inval_fence_recv(xe, fence);
+ trace_xe_tlb_inval_fence_recv(xe, fence);
if (!tlb_inval_seqno_past(gt, fence->seqno))
break;
@@ -557,7 +570,7 @@ int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
if (unlikely(len != 1))
return -EPROTO;
- xe_gt_tlb_inval_done_handler(gt, msg[0]);
+ xe_tlb_inval_done_handler(gt, msg[0]);
return 0;
}
@@ -580,19 +593,21 @@ static const struct dma_fence_ops inval_fence_ops = {
};
/**
- * xe_gt_tlb_inval_fence_init - Initialize TLB invalidation fence
- * @gt: GT
+ * xe_tlb_inval_fence_init - Initialize TLB invalidation fence
+ * @tlb_inval: TLB invalidation client
* @fence: TLB invalidation fence to initialize
* @stack: fence is stack variable
*
- * Initialize TLB invalidation fence for use. xe_gt_tlb_inval_fence_fini
+ * Initialize TLB invalidation fence for use. xe_tlb_inval_fence_fini
* will be automatically called when fence is signalled (all fences must signal),
* even on error.
*/
-void xe_gt_tlb_inval_fence_init(struct xe_gt *gt,
- struct xe_gt_tlb_inval_fence *fence,
- bool stack)
+void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence,
+ bool stack)
{
+ struct xe_gt *gt = tlb_inval->private;
+
xe_pm_runtime_get_noresume(gt_to_xe(gt));
spin_lock_irq(>->tlb_inval.lock);
@@ -605,5 +620,5 @@ void xe_gt_tlb_inval_fence_init(struct xe_gt *gt,
set_bit(FENCE_STACK_BIT, &fence->base.flags);
else
dma_fence_get(&fence->base);
- fence->gt = gt;
+ fence->tlb_inval = tlb_inval;
}
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.h b/drivers/gpu/drm/xe/xe_tlb_inval.h
new file mode 100644
index 000000000000..7adee3f8c551
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_TLB_INVAL_H_
+#define _XE_TLB_INVAL_H_
+
+#include <linux/types.h>
+
+#include "xe_tlb_inval_types.h"
+
+struct xe_gt;
+struct xe_guc;
+struct xe_vm;
+struct xe_vma;
+
+int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
+
+void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval);
+int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
+void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm);
+int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence);
+int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence,
+ u64 start, u64 end, u32 asid);
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
+
+void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence,
+ bool stack);
+void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence);
+
+static inline void
+xe_tlb_inval_fence_wait(struct xe_tlb_inval_fence *fence)
+{
+ dma_fence_wait(&fence->base, false);
+}
+
+#endif /* _XE_TLB_INVAL_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
similarity index 51%
rename from drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
rename to drivers/gpu/drm/xe/xe_tlb_inval_job.c
index 41e0ea92ea5a..492def04a559 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -3,21 +3,22 @@
* Copyright © 2025 Intel Corporation
*/
+#include "xe_assert.h"
#include "xe_dep_job_types.h"
#include "xe_dep_scheduler.h"
#include "xe_exec_queue.h"
-#include "xe_gt.h"
-#include "xe_gt_tlb_inval.h"
-#include "xe_gt_tlb_inval_job.h"
+#include "xe_gt_types.h"
+#include "xe_tlb_inval.h"
+#include "xe_tlb_inval_job.h"
#include "xe_migrate.h"
#include "xe_pm.h"
-/** struct xe_gt_tlb_inval_job - GT TLB invalidation job */
-struct xe_gt_tlb_inval_job {
+/** struct xe_tlb_inval_job - TLB invalidation job */
+struct xe_tlb_inval_job {
/** @dep: base generic dependency Xe job */
struct xe_dep_job dep;
- /** @gt: GT to invalidate */
- struct xe_gt *gt;
+ /** @tlb_inval: TLB invalidation client */
+ struct xe_tlb_inval *tlb_inval;
/** @q: exec queue issuing the invalidate */
struct xe_exec_queue *q;
/** @refcount: ref count of this job */
@@ -37,63 +38,56 @@ struct xe_gt_tlb_inval_job {
bool fence_armed;
};
-static struct dma_fence *xe_gt_tlb_inval_job_run(struct xe_dep_job *dep_job)
+static struct dma_fence *xe_tlb_inval_job_run(struct xe_dep_job *dep_job)
{
- struct xe_gt_tlb_inval_job *job =
+ struct xe_tlb_inval_job *job =
container_of(dep_job, typeof(*job), dep);
- struct xe_gt_tlb_inval_fence *ifence =
+ struct xe_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
- xe_gt_tlb_inval_range(job->gt, ifence, job->start,
- job->end, job->asid);
+ xe_tlb_inval_range(job->tlb_inval, ifence, job->start,
+ job->end, job->asid);
return job->fence;
}
-static void xe_gt_tlb_inval_job_free(struct xe_dep_job *dep_job)
+static void xe_tlb_inval_job_free(struct xe_dep_job *dep_job)
{
- struct xe_gt_tlb_inval_job *job =
+ struct xe_tlb_inval_job *job =
container_of(dep_job, typeof(*job), dep);
- /* Pairs with get in xe_gt_tlb_inval_job_push */
- xe_gt_tlb_inval_job_put(job);
+ /* Pairs with get in xe_tlb_inval_job_push */
+ xe_tlb_inval_job_put(job);
}
static const struct xe_dep_job_ops dep_job_ops = {
- .run_job = xe_gt_tlb_inval_job_run,
- .free_job = xe_gt_tlb_inval_job_free,
+ .run_job = xe_tlb_inval_job_run,
+ .free_job = xe_tlb_inval_job_free,
};
-static int xe_gt_tlb_inval_context(struct xe_gt *gt)
-{
- return xe_gt_is_media_type(gt) ? XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT :
- XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT;
-}
-
/**
- * xe_gt_tlb_inval_job_create() - GT TLB invalidation job create
- * @gt: GT to invalidate
+ * xe_tlb_inval_job_create() - TLB invalidation job create
* @q: exec queue issuing the invalidate
+ * @tlb_inval: TLB invalidation client
+ * @dep_scheduler: Dependency scheduler for job
* @start: Start address to invalidate
* @end: End address to invalidate
* @asid: Address space ID to invalidate
*
- * Create a GT TLB invalidation job and initialize internal fields. The caller is
+ * Create a TLB invalidation job and initialize internal fields. The caller is
* responsible for releasing the creation reference.
*
- * Return: GT TLB invalidation job object on success, ERR_PTR failure
+ * Return: TLB invalidation job object on success, ERR_PTR failure
*/
-struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
- struct xe_gt *gt,
- u64 start, u64 end,
- u32 asid)
+struct xe_tlb_inval_job *
+xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
+ struct xe_dep_scheduler *dep_scheduler, u64 start,
+ u64 end, u32 asid)
{
- struct xe_gt_tlb_inval_job *job;
- struct xe_dep_scheduler *dep_scheduler =
- q->tlb_inval[xe_gt_tlb_inval_context(gt)].dep_scheduler;
+ struct xe_tlb_inval_job *job;
struct drm_sched_entity *entity =
xe_dep_scheduler_entity(dep_scheduler);
- struct xe_gt_tlb_inval_fence *ifence;
+ struct xe_tlb_inval_fence *ifence;
int err;
job = kmalloc(sizeof(*job), GFP_KERNEL);
@@ -101,14 +95,14 @@ struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
return ERR_PTR(-ENOMEM);
job->q = q;
- job->gt = gt;
+ job->tlb_inval = tlb_inval;
job->start = start;
job->end = end;
job->asid = asid;
job->fence_armed = false;
job->dep.ops = &dep_job_ops;
kref_init(&job->refcount);
- xe_exec_queue_get(q); /* Pairs with put in xe_gt_tlb_inval_job_destroy */
+ xe_exec_queue_get(q); /* Pairs with put in xe_tlb_inval_job_destroy */
ifence = kmalloc(sizeof(*ifence), GFP_KERNEL);
if (!ifence) {
@@ -122,8 +116,8 @@ struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
if (err)
goto err_fence;
- /* Pairs with put in xe_gt_tlb_inval_job_destroy */
- xe_pm_runtime_get_noresume(gt_to_xe(job->gt));
+ /* Pairs with put in xe_tlb_inval_job_destroy */
+ xe_pm_runtime_get_noresume(gt_to_xe(q->gt));
return job;
@@ -136,40 +130,40 @@ struct xe_gt_tlb_inval_job *xe_gt_tlb_inval_job_create(struct xe_exec_queue *q,
return ERR_PTR(err);
}
-static void xe_gt_tlb_inval_job_destroy(struct kref *ref)
+static void xe_tlb_inval_job_destroy(struct kref *ref)
{
- struct xe_gt_tlb_inval_job *job = container_of(ref, typeof(*job),
- refcount);
- struct xe_gt_tlb_inval_fence *ifence =
+ struct xe_tlb_inval_job *job = container_of(ref, typeof(*job),
+ refcount);
+ struct xe_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
- struct xe_device *xe = gt_to_xe(job->gt);
struct xe_exec_queue *q = job->q;
+ struct xe_device *xe = gt_to_xe(q->gt);
if (!job->fence_armed)
kfree(ifence);
else
- /* Ref from xe_gt_tlb_inval_fence_init */
+ /* Ref from xe_tlb_inval_fence_init */
dma_fence_put(job->fence);
drm_sched_job_cleanup(&job->dep.drm);
kfree(job);
- xe_exec_queue_put(q); /* Pairs with get from xe_gt_tlb_inval_job_create */
- xe_pm_runtime_put(xe); /* Pairs with get from xe_gt_tlb_inval_job_create */
+ xe_exec_queue_put(q); /* Pairs with get from xe_tlb_inval_job_create */
+ xe_pm_runtime_put(xe); /* Pairs with get from xe_tlb_inval_job_create */
}
/**
- * xe_gt_tlb_inval_alloc_dep() - GT TLB invalidation job alloc dependency
- * @job: GT TLB invalidation job to alloc dependency for
+ * xe_tlb_inval_alloc_dep() - TLB invalidation job alloc dependency
+ * @job: TLB invalidation job to alloc dependency for
*
- * Allocate storage for a dependency in the GT TLB invalidation fence. This
+ * Allocate storage for a dependency in the TLB invalidation fence. This
* function should be called at most once per job and must be paired with
- * xe_gt_tlb_inval_job_push being called with a real fence.
+ * xe_tlb_inval_job_push being called with a real fence.
*
* Return: 0 on success, -errno on failure
*/
-int xe_gt_tlb_inval_job_alloc_dep(struct xe_gt_tlb_inval_job *job)
+int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job)
{
- xe_assert(gt_to_xe(job->gt), !xa_load(&job->dep.drm.dependencies, 0));
+ xe_assert(gt_to_xe(job->q->gt), !xa_load(&job->dep.drm.dependencies, 0));
might_alloc(GFP_KERNEL);
return drm_sched_job_add_dependency(&job->dep.drm,
@@ -177,24 +171,24 @@ int xe_gt_tlb_inval_job_alloc_dep(struct xe_gt_tlb_inval_job *job)
}
/**
- * xe_gt_tlb_inval_job_push() - GT TLB invalidation job push
- * @job: GT TLB invalidation job to push
+ * xe_tlb_inval_job_push() - TLB invalidation job push
+ * @job: TLB invalidation job to push
* @m: The migration object being used
- * @fence: Dependency for GT TLB invalidation job
+ * @fence: Dependency for TLB invalidation job
*
- * Pushes a GT TLB invalidation job for execution, using @fence as a dependency.
- * Storage for @fence must be preallocated with xe_gt_tlb_inval_job_alloc_dep
+ * Pushes a TLB invalidation job for execution, using @fence as a dependency.
+ * Storage for @fence must be preallocated with xe_tlb_inval_job_alloc_dep
* prior to this call if @fence is not signaled. Takes a reference to the job’s
* finished fence, which the caller is responsible for releasing, and return it
* to the caller. This function is safe to be called in the path of reclaim.
*
* Return: Job's finished fence on success, cannot fail
*/
-struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
- struct xe_migrate *m,
- struct dma_fence *fence)
+struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
+ struct xe_migrate *m,
+ struct dma_fence *fence)
{
- struct xe_gt_tlb_inval_fence *ifence =
+ struct xe_tlb_inval_fence *ifence =
container_of(job->fence, typeof(*ifence), base);
if (!dma_fence_is_signaled(fence)) {
@@ -202,20 +196,20 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
/*
* Can be in path of reclaim, hence the preallocation of fence
- * storage in xe_gt_tlb_inval_job_alloc_dep. Verify caller did
+ * storage in xe_tlb_inval_job_alloc_dep. Verify caller did
* this correctly.
*/
- xe_assert(gt_to_xe(job->gt),
+ xe_assert(gt_to_xe(job->q->gt),
xa_load(&job->dep.drm.dependencies, 0) ==
dma_fence_get_stub());
dma_fence_get(fence); /* ref released once dependency processed by scheduler */
ptr = xa_store(&job->dep.drm.dependencies, 0, fence,
GFP_ATOMIC);
- xe_assert(gt_to_xe(job->gt), !xa_is_err(ptr));
+ xe_assert(gt_to_xe(job->q->gt), !xa_is_err(ptr));
}
- xe_gt_tlb_inval_job_get(job); /* Pairs with put in free_job */
+ xe_tlb_inval_job_get(job); /* Pairs with put in free_job */
job->fence_armed = true;
/*
@@ -225,8 +219,8 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
*/
xe_migrate_job_lock(m, job->q);
- /* Creation ref pairs with put in xe_gt_tlb_inval_job_destroy */
- xe_gt_tlb_inval_fence_init(job->gt, ifence, false);
+ /* Creation ref pairs with put in xe_tlb_inval_job_destroy */
+ xe_tlb_inval_fence_init(job->tlb_inval, ifence, false);
dma_fence_get(job->fence); /* Pairs with put in DRM scheduler */
drm_sched_job_arm(&job->dep.drm);
@@ -241,7 +235,7 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
/*
* Not using job->fence, as it has its own dma-fence context, which does
- * not allow GT TLB invalidation fences on the same queue, GT tuple to
+ * not allow TLB invalidation fences on the same queue, GT tuple to
* be squashed in dma-resv/DRM scheduler. Instead, we use the DRM scheduler
* context and job's finished fence, which enables squashing.
*/
@@ -249,26 +243,26 @@ struct dma_fence *xe_gt_tlb_inval_job_push(struct xe_gt_tlb_inval_job *job,
}
/**
- * xe_gt_tlb_inval_job_get() - Get a reference to GT TLB invalidation job
- * @job: GT TLB invalidation job object
+ * xe_tlb_inval_job_get() - Get a reference to TLB invalidation job
+ * @job: TLB invalidation job object
*
- * Increment the GT TLB invalidation job's reference count
+ * Increment the TLB invalidation job's reference count
*/
-void xe_gt_tlb_inval_job_get(struct xe_gt_tlb_inval_job *job)
+void xe_tlb_inval_job_get(struct xe_tlb_inval_job *job)
{
kref_get(&job->refcount);
}
/**
- * xe_gt_tlb_inval_job_put() - Put a reference to GT TLB invalidation job
- * @job: GT TLB invalidation job object
+ * xe_tlb_inval_job_put() - Put a reference to TLB invalidation job
+ * @job: TLB invalidation job object
*
- * Decrement the GT TLB invalidation job's reference count, call
- * xe_gt_tlb_inval_job_destroy when reference count == 0. Skips decrement if
+ * Decrement the TLB invalidation job's reference count, call
+ * xe_tlb_inval_job_destroy when reference count == 0. Skips decrement if
* input @job is NULL or IS_ERR.
*/
-void xe_gt_tlb_inval_job_put(struct xe_gt_tlb_inval_job *job)
+void xe_tlb_inval_job_put(struct xe_tlb_inval_job *job)
{
if (!IS_ERR_OR_NULL(job))
- kref_put(&job->refcount, xe_gt_tlb_inval_job_destroy);
+ kref_put(&job->refcount, xe_tlb_inval_job_destroy);
}
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
new file mode 100644
index 000000000000..32fb41599a19
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_TLB_INVAL_JOB_H_
+#define _XE_TLB_INVAL_JOB_H_
+
+#include <linux/types.h>
+
+struct dma_fence;
+struct drm_sched_job;
+struct xe_dep_scheduler;
+struct xe_exec_queue;
+struct xe_tlb_inval;
+struct xe_tlb_inval_job;
+struct xe_migrate;
+
+struct xe_tlb_inval_job *
+xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
+ struct xe_dep_scheduler *dep_scheduler,
+ u64 start, u64 end, u32 asid);
+
+int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job);
+
+struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
+ struct xe_migrate *m,
+ struct dma_fence *fence);
+
+void xe_tlb_inval_job_get(struct xe_tlb_inval_job *job);
+
+void xe_tlb_inval_job_put(struct xe_tlb_inval_job *job);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
similarity index 54%
rename from drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
rename to drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 8b37d0b8f545..05b6adc929bb 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -3,56 +3,55 @@
* Copyright © 2023 Intel Corporation
*/
-#ifndef _XE_GT_TLB_INVAL_TYPES_H_
-#define _XE_GT_TLB_INVAL_TYPES_H_
+#ifndef _XE_TLB_INVAL_TYPES_H_
+#define _XE_TLB_INVAL_TYPES_H_
#include <linux/workqueue.h>
#include <linux/dma-fence.h>
-struct xe_gt;
-
/** struct xe_tlb_inval - TLB invalidation client */
struct xe_tlb_inval {
+ /** @private: Backend private pointer */
+ void *private;
/** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
#define TLB_INVALIDATION_SEQNO_MAX 0x100000
int seqno;
/**
- * @tlb_inval.seqno_recv: last received TLB invalidation seqno,
- * protected by CT lock
+ * @seqno_recv: last received TLB invalidation seqno, protected by
+ * CT lock
*/
int seqno_recv;
/**
- * @tlb_inval.pending_fences: list of pending fences waiting TLB
- * invaliations, protected by CT lock
+ * @pending_fences: list of pending fences waiting TLB invaliations,
+ * protected CT lock
*/
struct list_head pending_fences;
/**
- * @tlb_inval.pending_lock: protects @tlb_inval.pending_fences
- * and updating @tlb_inval.seqno_recv.
+ * @pending_lock: protects @pending_fences and updating @seqno_recv.
*/
spinlock_t pending_lock;
/**
- * @tlb_inval.fence_tdr: schedules a delayed call to
- * xe_gt_tlb_fence_timeout after the timeut interval is over.
+ * @fence_tdr: schedules a delayed call to xe_tlb_fence_timeout after
+ * the timeout interval is over.
*/
struct delayed_work fence_tdr;
- /** @wtlb_invalidation.wq: schedules GT TLB invalidation jobs */
+ /** @job_wq: schedules TLB invalidation jobs */
struct workqueue_struct *job_wq;
/** @tlb_inval.lock: protects TLB invalidation fences */
spinlock_t lock;
};
/**
- * struct xe_gt_tlb_inval_fence - XE GT TLB invalidation fence
+ * struct xe_tlb_inval_fence - TLB invalidation fence
*
- * Optionally passed to xe_gt_tlb_inval and will be signaled upon TLB
+ * Optionally passed to xe_tlb_inval* functions and will be signaled upon TLB
* invalidation completion.
*/
-struct xe_gt_tlb_inval_fence {
+struct xe_tlb_inval_fence {
/** @base: dma fence base */
struct dma_fence base;
- /** @gt: GT which fence belong to */
- struct xe_gt *gt;
+ /** @tlb_inval: TLB invalidation client which fence belong to */
+ struct xe_tlb_inval *tlb_inval;
/** @link: link into list of pending tlb fences */
struct list_head link;
/** @seqno: seqno of TLB invalidation to signal fence one */
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 36538f50d06f..314f42fcbcbd 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -14,10 +14,10 @@
#include "xe_exec_queue_types.h"
#include "xe_gpu_scheduler_types.h"
-#include "xe_gt_tlb_inval_types.h"
#include "xe_gt_types.h"
#include "xe_guc_exec_queue_types.h"
#include "xe_sched_job.h"
+#include "xe_tlb_inval_types.h"
#include "xe_vm.h"
#define __dev_name_xe(xe) dev_name((xe)->drm.dev)
@@ -25,13 +25,13 @@
#define __dev_name_gt(gt) __dev_name_xe(gt_to_xe((gt)))
#define __dev_name_eq(q) __dev_name_gt((q)->gt)
-DECLARE_EVENT_CLASS(xe_gt_tlb_inval_fence,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
+DECLARE_EVENT_CLASS(xe_tlb_inval_fence,
+ TP_PROTO(struct xe_device *xe, struct xe_tlb_inval_fence *fence),
TP_ARGS(xe, fence),
TP_STRUCT__entry(
__string(dev, __dev_name_xe(xe))
- __field(struct xe_gt_tlb_inval_fence *, fence)
+ __field(struct xe_tlb_inval_fence *, fence)
__field(int, seqno)
),
@@ -45,23 +45,23 @@ DECLARE_EVENT_CLASS(xe_gt_tlb_inval_fence,
__get_str(dev), __entry->fence, __entry->seqno)
);
-DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_send,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
+DEFINE_EVENT(xe_tlb_inval_fence, xe_tlb_inval_fence_send,
+ TP_PROTO(struct xe_device *xe, struct xe_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_recv,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
+DEFINE_EVENT(xe_tlb_inval_fence, xe_tlb_inval_fence_recv,
+ TP_PROTO(struct xe_device *xe, struct xe_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_signal,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
+DEFINE_EVENT(xe_tlb_inval_fence, xe_tlb_inval_fence_signal,
+ TP_PROTO(struct xe_device *xe, struct xe_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
-DEFINE_EVENT(xe_gt_tlb_inval_fence, xe_gt_tlb_inval_fence_timeout,
- TP_PROTO(struct xe_device *xe, struct xe_gt_tlb_inval_fence *fence),
+DEFINE_EVENT(xe_tlb_inval_fence, xe_tlb_inval_fence_timeout,
+ TP_PROTO(struct xe_device *xe, struct xe_tlb_inval_fence *fence),
TP_ARGS(xe, fence)
);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index a4011a1e5e2c..5c530051723f 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -28,7 +28,6 @@
#include "xe_drm_client.h"
#include "xe_exec_queue.h"
#include "xe_gt_pagefault.h"
-#include "xe_gt_tlb_inval.h"
#include "xe_migrate.h"
#include "xe_pat.h"
#include "xe_pm.h"
@@ -38,6 +37,7 @@
#include "xe_res_cursor.h"
#include "xe_svm.h"
#include "xe_sync.h"
+#include "xe_tlb_inval.h"
#include "xe_trace_bo.h"
#include "xe_wa.h"
#include "xe_hmm.h"
@@ -1850,7 +1850,7 @@ static void xe_vm_close(struct xe_vm *vm)
xe_pt_clear(xe, vm->pt_root[id]);
for_each_gt(gt, xe, id)
- xe_gt_tlb_inval_vm(gt, vm);
+ xe_tlb_inval_vm(>->tlb_inval, vm);
}
}
@@ -3857,7 +3857,7 @@ void xe_vm_unlock(struct xe_vm *vm)
int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
u64 end, u8 tile_mask)
{
- struct xe_gt_tlb_inval_fence
+ struct xe_tlb_inval_fence
fence[XE_MAX_TILES_PER_DEVICE * XE_MAX_GT_PER_TILE];
struct xe_tile *tile;
u32 fence_id = 0;
@@ -3871,11 +3871,12 @@ int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
if (!(tile_mask & BIT(id)))
continue;
- xe_gt_tlb_inval_fence_init(tile->primary_gt,
- &fence[fence_id], true);
+ xe_tlb_inval_fence_init(&tile->primary_gt->tlb_inval,
+ &fence[fence_id], true);
- err = xe_gt_tlb_inval_range(tile->primary_gt, &fence[fence_id],
- start, end, vm->usm.asid);
+ err = xe_tlb_inval_range(&tile->primary_gt->tlb_inval,
+ &fence[fence_id], start, end,
+ vm->usm.asid);
if (err)
goto wait;
++fence_id;
@@ -3883,11 +3884,12 @@ int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
if (!tile->media_gt)
continue;
- xe_gt_tlb_inval_fence_init(tile->media_gt,
- &fence[fence_id], true);
+ xe_tlb_inval_fence_init(&tile->media_gt->tlb_inval,
+ &fence[fence_id], true);
- err = xe_gt_tlb_inval_range(tile->media_gt, &fence[fence_id],
- start, end, vm->usm.asid);
+ err = xe_tlb_inval_range(&tile->media_gt->tlb_inval,
+ &fence[fence_id], start, end,
+ vm->usm.asid);
if (err)
goto wait;
++fence_id;
@@ -3895,7 +3897,7 @@ int xe_vm_range_tilemask_tlb_inval(struct xe_vm *vm, u64 start,
wait:
for (id = 0; id < fence_id; ++id)
- xe_gt_tlb_inval_fence_wait(&fence[id]);
+ xe_tlb_inval_fence_wait(&fence[id]);
return err;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 5/8] drm/xe: Decouple TLB invalidations from GT
2025-07-30 20:45 ` [PATCH 5/8] drm/xe: Decouple TLB invalidations from GT stuartsummers
@ 2025-07-31 17:05 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2025-07-31 17:05 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew, Kassabri, Farah
On Wed, 2025-07-30 at 20:45 +0000, stuartsummers wrote:
> From: Matthew Brost <matthew.brost@intel.com>
>
> Decouple TLB invalidations from the GT by updating the TLB
> invalidation
> layer to accept a `struct xe_tlb_inval` instead of a `struct xe_gt`.
> Also, rename *gt_tlb* to *tlb*. The internals of the TLB invalidation
> code still operate on a GT, but this is now hidden from the rest of
> the
> driver.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 4 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 4 +-
> drivers/gpu/drm/xe/xe_gt.c | 6 +-
> drivers/gpu/drm/xe/xe_gt_tlb_inval.h | 40 -----
> drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h | 34 ----
> drivers/gpu/drm/xe/xe_gt_types.h | 2 +-
> drivers/gpu/drm/xe/xe_guc_ct.c | 2 +-
> drivers/gpu/drm/xe/xe_lmtt.c | 12 +-
> drivers/gpu/drm/xe/xe_migrate.h | 10 +-
> drivers/gpu/drm/xe/xe_pt.c | 63 ++++---
> drivers/gpu/drm/xe/xe_svm.c | 1 -
> .../xe/{xe_gt_tlb_inval.c => xe_tlb_inval.c} | 143 ++++++++--------
> drivers/gpu/drm/xe/xe_tlb_inval.h | 41 +++++
> ..._gt_tlb_inval_job.c => xe_tlb_inval_job.c} | 154 +++++++++-------
> --
> drivers/gpu/drm/xe/xe_tlb_inval_job.h | 34 ++++
> ...tlb_inval_types.h => xe_tlb_inval_types.h} | 35 ++--
> drivers/gpu/drm/xe/xe_trace.h | 24 +--
> drivers/gpu/drm/xe/xe_vm.c | 26 +--
> 18 files changed, 331 insertions(+), 304 deletions(-)
> delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval.h
> delete mode 100644 drivers/gpu/drm/xe/xe_gt_tlb_inval_job.h
> rename drivers/gpu/drm/xe/{xe_gt_tlb_inval.c => xe_tlb_inval.c}
> (79%)
> create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval.h
> rename drivers/gpu/drm/xe/{xe_gt_tlb_inval_job.c =>
> xe_tlb_inval_job.c} (51%)
> create mode 100644 drivers/gpu/drm/xe/xe_tlb_inval_job.h
> rename drivers/gpu/drm/xe/{xe_gt_tlb_inval_types.h =>
> xe_tlb_inval_types.h} (54%)
>
<cut>
> }
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.h
> b/drivers/gpu/drm/xe/xe_tlb_inval.h
> new file mode 100644
> index 000000000000..7adee3f8c551
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_TLB_INVAL_H_
> +#define _XE_TLB_INVAL_H_
> +
> +#include <linux/types.h>
> +
> +#include "xe_tlb_inval_types.h"
> +
> +struct xe_gt;
> +struct xe_guc;
> +struct xe_vm;
> +struct xe_vma;
Looks like I missed a couple extra structs here... I'll remove xe_vma
here and drm_sched_job from xe_tlb_inval_job.h below in the next rev
(see below).
> +
> +int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
> +
> +void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval);
> +int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
> +void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm
> *vm);
> +int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
> + struct xe_tlb_inval_fence *fence);
> +int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
> + struct xe_tlb_inval_fence *fence,
> + u64 start, u64 end, u32 asid);
> +int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32
> len);
> +
> +void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
> + struct xe_tlb_inval_fence *fence,
> + bool stack);
> +void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence);
> +
> +static inline void
> +xe_tlb_inval_fence_wait(struct xe_tlb_inval_fence *fence)
> +{
> + dma_fence_wait(&fence->base, false);
> +}
> +
> +#endif /* _XE_TLB_INVAL_ */
> diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
> b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
> similarity index 51%
> rename from drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
> rename to drivers/gpu/drm/xe/xe_tlb_inval_job.c
> index 41e0ea92ea5a..492def04a559 100644
> --- a/drivers/gpu/drm/xe/xe_gt_tlb_inval_job.c
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
> @@ -3,21 +3,22 @@
> * Copyright © 2025 Intel Corporation
> */
>
<cut>
> {
> if (!IS_ERR_OR_NULL(job))
> - kref_put(&job->refcount,
> xe_gt_tlb_inval_job_destroy);
> + kref_put(&job->refcount, xe_tlb_inval_job_destroy);
> }
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> new file mode 100644
> index 000000000000..32fb41599a19
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_TLB_INVAL_JOB_H_
> +#define _XE_TLB_INVAL_JOB_H_
> +
> +#include <linux/types.h>
> +
> +struct dma_fence;
> +struct drm_sched_job;
And here.
Otherwise the patch looks good to me. Would be nice to get another ack
since I'm making some minor changes here before merging..
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Thanks,
Stuart
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 6/8] drm/xe: Prep TLB invalidation fence before sending
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (4 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 5/8] drm/xe: Decouple TLB invalidations from GT stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-07-31 18:38 ` Summers, Stuart
2025-07-30 20:45 ` [PATCH 7/8] drm/xe: Add helpers to send TLB invalidations stuartsummers
` (5 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe
From: Matthew Brost <matthew.brost@intel.com>
It is a bit backwards to add a TLB invalidation fence to the pending
list after issuing the invalidation. Perform this step before issuing
the TLB invalidation in a helper function.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_tlb_inval.c | 103 +++++++++++++++---------------
1 file changed, 51 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 288960ea0caa..2ffd677ee180 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -65,19 +65,19 @@ __inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
static void
inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
{
+ lockdep_assert_held(&fence->tlb_inval->pending_lock);
+
list_del(&fence->link);
__inval_fence_signal(xe, fence);
}
-void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence)
+static void
+inval_fence_signal_unlocked(struct xe_device *xe,
+ struct xe_tlb_inval_fence *fence)
{
- struct xe_gt *gt;
-
- if (WARN_ON_ONCE(!fence->tlb_inval))
- return;
-
- gt = fence->tlb_inval->private;
- __inval_fence_signal(gt_to_xe(gt), fence);
+ spin_lock_irq(&fence->tlb_inval->pending_lock);
+ inval_fence_signal(xe, fence);
+ spin_unlock_irq(&fence->tlb_inval->pending_lock);
}
static void xe_gt_tlb_fence_timeout(struct work_struct *work)
@@ -199,14 +199,10 @@ static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
return seqno_recv >= seqno;
}
-static int send_tlb_inval(struct xe_guc *guc,
- struct xe_tlb_inval_fence *fence,
+static int send_tlb_inval(struct xe_guc *guc, struct xe_tlb_inval_fence *fence,
u32 *action, int len)
{
struct xe_gt *gt = guc_to_gt(guc);
- struct xe_device *xe = gt_to_xe(gt);
- int seqno;
- int ret;
xe_gt_assert(gt, fence);
@@ -216,45 +212,36 @@ static int send_tlb_inval(struct xe_guc *guc,
* need to be updated.
*/
- seqno = gt->tlb_inval.seqno;
- fence->seqno = seqno;
- trace_xe_tlb_inval_fence_send(xe, fence);
- action[1] = seqno;
- ret = xe_guc_ct_send(&guc->ct, action, len,
- G2H_LEN_DW_TLB_INVALIDATE, 1);
- if (!ret) {
- spin_lock_irq(>->tlb_inval.pending_lock);
- /*
- * We haven't actually published the TLB fence as per
- * pending_fences, but in theory our seqno could have already
- * been written as we acquired the pending_lock. In such a case
- * we can just go ahead and signal the fence here.
- */
- if (tlb_inval_seqno_past(gt, seqno)) {
- __inval_fence_signal(xe, fence);
- } else {
- fence->inval_time = ktime_get();
- list_add_tail(&fence->link,
- >->tlb_inval.pending_fences);
-
- if (list_is_singular(>->tlb_inval.pending_fences))
- queue_delayed_work(system_wq,
- >->tlb_inval.fence_tdr,
- tlb_timeout_jiffies(gt));
- }
- spin_unlock_irq(>->tlb_inval.pending_lock);
- } else {
- __inval_fence_signal(xe, fence);
- }
- if (!ret) {
- gt->tlb_inval.seqno = (gt->tlb_inval.seqno + 1) %
- TLB_INVALIDATION_SEQNO_MAX;
- if (!gt->tlb_inval.seqno)
- gt->tlb_inval.seqno = 1;
- }
xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
+ action[1] = fence->seqno;
- return ret;
+ return xe_guc_ct_send(&guc->ct, action, len,
+ G2H_LEN_DW_TLB_INVALIDATE, 1);
+}
+
+static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence *fence)
+{
+ struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
+ struct xe_gt *gt = tlb_inval->private;
+ struct xe_device *xe = gt_to_xe(gt);
+
+ fence->seqno = tlb_inval->seqno;
+ trace_xe_tlb_inval_fence_send(xe, fence);
+
+ spin_lock_irq(&tlb_inval->pending_lock);
+ fence->inval_time = ktime_get();
+ list_add_tail(&fence->link, &tlb_inval->pending_fences);
+
+ if (list_is_singular(&tlb_inval->pending_fences))
+ queue_delayed_work(system_wq,
+ &tlb_inval->fence_tdr,
+ tlb_timeout_jiffies(gt));
+ spin_unlock_irq(&tlb_inval->pending_lock);
+
+ tlb_inval->seqno = (tlb_inval->seqno + 1) %
+ TLB_INVALIDATION_SEQNO_MAX;
+ if (!tlb_inval->seqno)
+ tlb_inval->seqno = 1;
}
#define MAKE_INVAL_OP(type) ((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
@@ -282,7 +269,12 @@ static int xe_tlb_inval_guc(struct xe_gt *gt,
};
int ret;
+ xe_tlb_inval_fence_prep(fence);
+
ret = send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
+ if (ret < 0)
+ inval_fence_signal_unlocked(gt_to_xe(gt), fence);
+
/*
* -ECANCELED indicates the CT is stopped for a GT reset. TLB caches
* should be nuked on a GT reset so this error can be ignored.
@@ -409,7 +401,7 @@ int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
#define MAX_TLB_INVALIDATION_LEN 7
u32 action[MAX_TLB_INVALIDATION_LEN];
u64 length = end - start;
- int len = 0;
+ int len = 0, ret;
xe_gt_assert(gt, fence);
@@ -470,7 +462,14 @@ int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
- return send_tlb_inval(>->uc.guc, fence, action, len);
+ xe_tlb_inval_fence_prep(fence);
+
+ ret = send_tlb_inval(>->uc.guc, fence, action,
+ ARRAY_SIZE(action));
+ if (ret < 0)
+ inval_fence_signal_unlocked(xe, fence);
+
+ return ret;
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 6/8] drm/xe: Prep TLB invalidation fence before sending
2025-07-30 20:45 ` [PATCH 6/8] drm/xe: Prep TLB invalidation fence before sending stuartsummers
@ 2025-07-31 18:38 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2025-07-31 18:38 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew, Kassabri, Farah
On Wed, 2025-07-30 at 20:45 +0000, stuartsummers wrote:
> From: Matthew Brost <matthew.brost@intel.com>
>
> It is a bit backwards to add a TLB invalidation fence to the pending
> list after issuing the invalidation. Perform this step before issuing
> the TLB invalidation in a helper function.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/xe_tlb_inval.c | 103 +++++++++++++++-------------
> --
> 1 file changed, 51 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_tlb_inval.c
> index 288960ea0caa..2ffd677ee180 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
> @@ -65,19 +65,19 @@ __inval_fence_signal(struct xe_device *xe, struct
> xe_tlb_inval_fence *fence)
> static void
> inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence
> *fence)
> {
> + lockdep_assert_held(&fence->tlb_inval->pending_lock);
> +
> list_del(&fence->link);
> __inval_fence_signal(xe, fence);
> }
>
> -void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence)
> +static void
> +inval_fence_signal_unlocked(struct xe_device *xe,
> + struct xe_tlb_inval_fence *fence)
> {
> - struct xe_gt *gt;
> -
> - if (WARN_ON_ONCE(!fence->tlb_inval))
> - return;
> -
> - gt = fence->tlb_inval->private;
> - __inval_fence_signal(gt_to_xe(gt), fence);
> + spin_lock_irq(&fence->tlb_inval->pending_lock);
> + inval_fence_signal(xe, fence);
> + spin_unlock_irq(&fence->tlb_inval->pending_lock);
> }
>
> static void xe_gt_tlb_fence_timeout(struct work_struct *work)
> @@ -199,14 +199,10 @@ static bool tlb_inval_seqno_past(struct xe_gt
> *gt, int seqno)
> return seqno_recv >= seqno;
> }
>
> -static int send_tlb_inval(struct xe_guc *guc,
> - struct xe_tlb_inval_fence *fence,
> +static int send_tlb_inval(struct xe_guc *guc, struct
> xe_tlb_inval_fence *fence,
> u32 *action, int len)
> {
> struct xe_gt *gt = guc_to_gt(guc);
> - struct xe_device *xe = gt_to_xe(gt);
> - int seqno;
> - int ret;
>
> xe_gt_assert(gt, fence);
>
> @@ -216,45 +212,36 @@ static int send_tlb_inval(struct xe_guc *guc,
> * need to be updated.
> */
>
> - seqno = gt->tlb_inval.seqno;
> - fence->seqno = seqno;
> - trace_xe_tlb_inval_fence_send(xe, fence);
> - action[1] = seqno;
> - ret = xe_guc_ct_send(&guc->ct, action, len,
> - G2H_LEN_DW_TLB_INVALIDATE, 1);
> - if (!ret) {
> - spin_lock_irq(>->tlb_inval.pending_lock);
> - /*
> - * We haven't actually published the TLB fence as per
> - * pending_fences, but in theory our seqno could have
> already
> - * been written as we acquired the pending_lock. In
> such a case
> - * we can just go ahead and signal the fence here.
> - */
> - if (tlb_inval_seqno_past(gt, seqno)) {
> - __inval_fence_signal(xe, fence);
> - } else {
> - fence->inval_time = ktime_get();
> - list_add_tail(&fence->link,
> - >->tlb_inval.pending_fences);
> -
> - if (list_is_singular(>-
> >tlb_inval.pending_fences))
> - queue_delayed_work(system_wq,
> - >-
> >tlb_inval.fence_tdr,
> -
> tlb_timeout_jiffies(gt));
> - }
> - spin_unlock_irq(>->tlb_inval.pending_lock);
> - } else {
> - __inval_fence_signal(xe, fence);
> - }
> - if (!ret) {
> - gt->tlb_inval.seqno = (gt->tlb_inval.seqno + 1) %
> - TLB_INVALIDATION_SEQNO_MAX;
> - if (!gt->tlb_inval.seqno)
> - gt->tlb_inval.seqno = 1;
> - }
> xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
> + action[1] = fence->seqno;
>
> - return ret;
> + return xe_guc_ct_send(&guc->ct, action, len,
> + G2H_LEN_DW_TLB_INVALIDATE, 1);
> +}
> +
> +static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence
> *fence)
> +{
> + struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
> + struct xe_gt *gt = tlb_inval->private;
> + struct xe_device *xe = gt_to_xe(gt);
> +
> + fence->seqno = tlb_inval->seqno;
> + trace_xe_tlb_inval_fence_send(xe, fence);
> +
> + spin_lock_irq(&tlb_inval->pending_lock);
> + fence->inval_time = ktime_get();
> + list_add_tail(&fence->link, &tlb_inval->pending_fences);
> +
> + if (list_is_singular(&tlb_inval->pending_fences))
> + queue_delayed_work(system_wq,
> + &tlb_inval->fence_tdr,
> + tlb_timeout_jiffies(gt));
> + spin_unlock_irq(&tlb_inval->pending_lock);
> +
> + tlb_inval->seqno = (tlb_inval->seqno + 1) %
> + TLB_INVALIDATION_SEQNO_MAX;
> + if (!tlb_inval->seqno)
> + tlb_inval->seqno = 1;
> }
>
> #define MAKE_INVAL_OP(type) ((type <<
> XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
> @@ -282,7 +269,12 @@ static int xe_tlb_inval_guc(struct xe_gt *gt,
> };
> int ret;
>
> + xe_tlb_inval_fence_prep(fence);
> +
> ret = send_tlb_inval(>->uc.guc, fence, action,
> ARRAY_SIZE(action));
> + if (ret < 0)
> + inval_fence_signal_unlocked(gt_to_xe(gt), fence);
> +
> /*
> * -ECANCELED indicates the CT is stopped for a GT reset. TLB
> caches
> * should be nuked on a GT reset so this error can be
> ignored.
> @@ -409,7 +401,7 @@ int xe_tlb_inval_range(struct xe_tlb_inval
> *tlb_inval,
> #define MAX_TLB_INVALIDATION_LEN 7
> u32 action[MAX_TLB_INVALIDATION_LEN];
> u64 length = end - start;
> - int len = 0;
> + int len = 0, ret;
>
> xe_gt_assert(gt, fence);
>
> @@ -470,7 +462,14 @@ int xe_tlb_inval_range(struct xe_tlb_inval
> *tlb_inval,
>
> xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
>
> - return send_tlb_inval(>->uc.guc, fence, action, len);
> + xe_tlb_inval_fence_prep(fence);
> +
> + ret = send_tlb_inval(>->uc.guc, fence, action,
> + ARRAY_SIZE(action));
> + if (ret < 0)
> + inval_fence_signal_unlocked(xe, fence);
> +
> + return ret;
> }
>
> /**
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 7/8] drm/xe: Add helpers to send TLB invalidations
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (5 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 6/8] drm/xe: Prep TLB invalidation fence before sending stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-08-06 21:41 ` Summers, Stuart
2025-07-30 20:45 ` [PATCH 8/8] drm/xe: Split TLB invalidation code in frontend and backend stuartsummers
` (4 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
Break out the GuC specific code into helpers as part of the process to
decouple frontback TLB invalidation code from the backend.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_tlb_inval.c | 230 +++++++++++++++---------------
1 file changed, 115 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 2ffd677ee180..5db7f26bce2e 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -199,12 +199,11 @@ static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
return seqno_recv >= seqno;
}
-static int send_tlb_inval(struct xe_guc *guc, struct xe_tlb_inval_fence *fence,
- u32 *action, int len)
+static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int len)
{
struct xe_gt *gt = guc_to_gt(guc);
- xe_gt_assert(gt, fence);
+ xe_gt_assert(gt, action[1]); /* Seqno */
/*
* XXX: The seqno algorithm relies on TLB invalidation being processed
@@ -213,7 +212,6 @@ static int send_tlb_inval(struct xe_guc *guc, struct xe_tlb_inval_fence *fence,
*/
xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
- action[1] = fence->seqno;
return xe_guc_ct_send(&guc->ct, action, len,
G2H_LEN_DW_TLB_INVALIDATE, 1);
@@ -248,89 +246,15 @@ static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence *fence)
XE_GUC_TLB_INVAL_MODE_HEAVY << XE_GUC_TLB_INVAL_MODE_SHIFT | \
XE_GUC_TLB_INVAL_FLUSH_CACHE)
-/**
- * xe_tlb_inval_guc - Issue a TLB invalidation on this GT for the GuC
- * @gt: GT structure
- * @fence: invalidation fence which will be signal on TLB invalidation
- * completion
- *
- * Issue a TLB invalidation for the GuC. Completion of TLB is asynchronous and
- * caller can use the invalidation fence to wait for completion.
- *
- * Return: 0 on success, negative error code on error
- */
-static int xe_tlb_inval_guc(struct xe_gt *gt,
- struct xe_tlb_inval_fence *fence)
+static int send_tlb_inval_ggtt(struct xe_gt *gt, int seqno)
{
u32 action[] = {
XE_GUC_ACTION_TLB_INVALIDATION,
- 0, /* seqno, replaced in send_tlb_inval */
+ seqno,
MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
};
- int ret;
-
- xe_tlb_inval_fence_prep(fence);
-
- ret = send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
- if (ret < 0)
- inval_fence_signal_unlocked(gt_to_xe(gt), fence);
-
- /*
- * -ECANCELED indicates the CT is stopped for a GT reset. TLB caches
- * should be nuked on a GT reset so this error can be ignored.
- */
- if (ret == -ECANCELED)
- return 0;
-
- return ret;
-}
-
-/**
- * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
- * @tlb_inval: TLB invalidation client
- *
- * Issue a TLB invalidation for the GGTT. Completion of TLB invalidation is
- * synchronous.
- *
- * Return: 0 on success, negative error code on error
- */
-int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
-{
- struct xe_gt *gt = tlb_inval->private;
- struct xe_device *xe = gt_to_xe(gt);
- unsigned int fw_ref;
-
- if (xe_guc_ct_enabled(>->uc.guc.ct) &&
- gt->uc.guc.submission_state.enabled) {
- struct xe_tlb_inval_fence fence;
- int ret;
-
- xe_tlb_inval_fence_init(tlb_inval, &fence, true);
- ret = xe_tlb_inval_guc(gt, &fence);
- if (ret)
- return ret;
- xe_tlb_inval_fence_wait(&fence);
- } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
- struct xe_mmio *mmio = >->mmio;
-
- if (IS_SRIOV_VF(xe))
- return 0;
-
- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
- if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
- xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
- PVC_GUC_TLB_INV_DESC1_INVALIDATE);
- xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
- PVC_GUC_TLB_INV_DESC0_VALID);
- } else {
- xe_mmio_write32(mmio, GUC_TLB_INV_CR,
- GUC_TLB_INV_CR_INVALIDATE);
- }
- xe_force_wake_put(gt_to_fw(gt), fw_ref);
- }
-
- return 0;
+ return send_tlb_inval(>->uc.guc, action, ARRAY_SIZE(action));
}
static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
@@ -345,7 +269,7 @@ static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
xe_gt_assert(gt, fence);
- return send_tlb_inval(>->uc.guc, fence, action, ARRAY_SIZE(action));
+ return send_tlb_inval(>->uc.guc, action, ARRAY_SIZE(action));
}
/**
@@ -377,43 +301,17 @@ int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
*/
#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
-/**
- * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
- * @tlb_inval: TLB invalidation client
- * @fence: invalidation fence which will be signal on TLB invalidation
- * completion
- * @start: start address
- * @end: end address
- * @asid: address space id
- *
- * Issue a range based TLB invalidation if supported, if not fallback to a full
- * TLB invalidation. Completion of TLB is asynchronous and caller can use
- * the invalidation fence to wait for completion.
- *
- * Return: Negative error code on error, 0 on success
- */
-int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
- struct xe_tlb_inval_fence *fence, u64 start, u64 end,
- u32 asid)
+static int send_tlb_inval_ppgtt(struct xe_gt *gt, u64 start, u64 end,
+ u32 asid, int seqno)
{
- struct xe_gt *gt = tlb_inval->private;
- struct xe_device *xe = gt_to_xe(gt);
#define MAX_TLB_INVALIDATION_LEN 7
u32 action[MAX_TLB_INVALIDATION_LEN];
u64 length = end - start;
- int len = 0, ret;
-
- xe_gt_assert(gt, fence);
-
- /* Execlists not supported */
- if (gt_to_xe(gt)->info.force_execlist) {
- __inval_fence_signal(xe, fence);
- return 0;
- }
+ int len = 0;
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
- action[len++] = 0; /* seqno, replaced in send_tlb_inval */
- if (!xe->info.has_range_tlb_inval ||
+ action[len++] = seqno;
+ if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
} else {
@@ -462,10 +360,112 @@ int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
+ return send_tlb_inval(>->uc.guc, action, len);
+}
+
+static int __xe_tlb_inval_ggtt(struct xe_gt *gt,
+ struct xe_tlb_inval_fence *fence)
+{
+ int ret;
+
+ xe_tlb_inval_fence_prep(fence);
+
+ ret = send_tlb_inval_ggtt(gt, fence->seqno);
+ if (ret < 0)
+ inval_fence_signal_unlocked(gt_to_xe(gt), fence);
+
+ /*
+ * -ECANCELED indicates the CT is stopped for a GT reset. TLB caches
+ * should be nuked on a GT reset so this error can be ignored.
+ */
+ if (ret == -ECANCELED)
+ return 0;
+
+ return ret;
+}
+
+/**
+ * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
+ * @tlb_inval: TLB invalidation client
+ *
+ * Issue a TLB invalidation for the GGTT. Completion of TLB invalidation is
+ * synchronous.
+ *
+ * Return: 0 on success, negative error code on error
+ */
+int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
+{
+ struct xe_gt *gt = tlb_inval->private;
+ struct xe_device *xe = gt_to_xe(gt);
+ unsigned int fw_ref;
+
+ if (xe_guc_ct_enabled(>->uc.guc.ct) &&
+ gt->uc.guc.submission_state.enabled) {
+ struct xe_tlb_inval_fence fence;
+ int ret;
+
+ xe_tlb_inval_fence_init(tlb_inval, &fence, true);
+ ret = __xe_tlb_inval_ggtt(gt, &fence);
+ if (ret)
+ return ret;
+
+ xe_tlb_inval_fence_wait(&fence);
+ } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
+ struct xe_mmio *mmio = >->mmio;
+
+ if (IS_SRIOV_VF(xe))
+ return 0;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
+ PVC_GUC_TLB_INV_DESC1_INVALIDATE);
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
+ PVC_GUC_TLB_INV_DESC0_VALID);
+ } else {
+ xe_mmio_write32(mmio, GUC_TLB_INV_CR,
+ GUC_TLB_INV_CR_INVALIDATE);
+ }
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ }
+
+ return 0;
+}
+
+/**
+ * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
+ * @tlb_inval: TLB invalidation client
+ * @fence: invalidation fence which will be signal on TLB invalidation
+ * completion
+ * @start: start address
+ * @end: end address
+ * @asid: address space id
+ *
+ * Issue a range based TLB invalidation if supported, if not fallback to a full
+ * TLB invalidation. Completion of TLB is asynchronous and caller can use
+ * the invalidation fence to wait for completion.
+ *
+ * Return: Negative error code on error, 0 on success
+ */
+int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
+ struct xe_tlb_inval_fence *fence, u64 start, u64 end,
+ u32 asid)
+{
+ struct xe_gt *gt = tlb_inval->private;
+ struct xe_device *xe = gt_to_xe(gt);
+ int ret;
+
+ xe_gt_assert(gt, fence);
+
+ /* Execlists not supported */
+ if (xe->info.force_execlist) {
+ __inval_fence_signal(xe, fence);
+ return 0;
+ }
+
xe_tlb_inval_fence_prep(fence);
- ret = send_tlb_inval(>->uc.guc, fence, action,
- ARRAY_SIZE(action));
+ ret = send_tlb_inval_ppgtt(gt, start, end, asid, fence->seqno);
if (ret < 0)
inval_fence_signal_unlocked(xe, fence);
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 7/8] drm/xe: Add helpers to send TLB invalidations
2025-07-30 20:45 ` [PATCH 7/8] drm/xe: Add helpers to send TLB invalidations stuartsummers
@ 2025-08-06 21:41 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2025-08-06 21:41 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew, Kassabri, Farah
On Wed, 2025-07-30 at 20:45 +0000, stuartsummers wrote:
> From: Matthew Brost <matthew.brost@intel.com>
>
> Break out the GuC specific code into helpers as part of the process
> to
> decouple frontback TLB invalidation code from the backend.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Changes here make sense to me. This has also had some time for reviews
on the list and I'd like to get this change merged soon if possible.
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/xe_tlb_inval.c | 230 +++++++++++++++-------------
> --
> 1 file changed, 115 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_tlb_inval.c
> index 2ffd677ee180..5db7f26bce2e 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
> @@ -199,12 +199,11 @@ static bool tlb_inval_seqno_past(struct xe_gt
> *gt, int seqno)
> return seqno_recv >= seqno;
> }
>
> -static int send_tlb_inval(struct xe_guc *guc, struct
> xe_tlb_inval_fence *fence,
> - u32 *action, int len)
> +static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int
> len)
> {
> struct xe_gt *gt = guc_to_gt(guc);
>
> - xe_gt_assert(gt, fence);
> + xe_gt_assert(gt, action[1]); /* Seqno */
>
> /*
> * XXX: The seqno algorithm relies on TLB invalidation being
> processed
> @@ -213,7 +212,6 @@ static int send_tlb_inval(struct xe_guc *guc,
> struct xe_tlb_inval_fence *fence,
> */
>
> xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
> - action[1] = fence->seqno;
>
> return xe_guc_ct_send(&guc->ct, action, len,
> G2H_LEN_DW_TLB_INVALIDATE, 1);
> @@ -248,89 +246,15 @@ static void xe_tlb_inval_fence_prep(struct
> xe_tlb_inval_fence *fence)
> XE_GUC_TLB_INVAL_MODE_HEAVY <<
> XE_GUC_TLB_INVAL_MODE_SHIFT | \
> XE_GUC_TLB_INVAL_FLUSH_CACHE)
>
> -/**
> - * xe_tlb_inval_guc - Issue a TLB invalidation on this GT for the
> GuC
> - * @gt: GT structure
> - * @fence: invalidation fence which will be signal on TLB
> invalidation
> - * completion
> - *
> - * Issue a TLB invalidation for the GuC. Completion of TLB is
> asynchronous and
> - * caller can use the invalidation fence to wait for completion.
> - *
> - * Return: 0 on success, negative error code on error
> - */
> -static int xe_tlb_inval_guc(struct xe_gt *gt,
> - struct xe_tlb_inval_fence *fence)
> +static int send_tlb_inval_ggtt(struct xe_gt *gt, int seqno)
> {
> u32 action[] = {
> XE_GUC_ACTION_TLB_INVALIDATION,
> - 0, /* seqno, replaced in send_tlb_inval */
> + seqno,
> MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
> };
> - int ret;
> -
> - xe_tlb_inval_fence_prep(fence);
> -
> - ret = send_tlb_inval(>->uc.guc, fence, action,
> ARRAY_SIZE(action));
> - if (ret < 0)
> - inval_fence_signal_unlocked(gt_to_xe(gt), fence);
> -
> - /*
> - * -ECANCELED indicates the CT is stopped for a GT reset. TLB
> caches
> - * should be nuked on a GT reset so this error can be
> ignored.
> - */
> - if (ret == -ECANCELED)
> - return 0;
> -
> - return ret;
> -}
> -
> -/**
> - * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the
> GGTT
> - * @tlb_inval: TLB invalidation client
> - *
> - * Issue a TLB invalidation for the GGTT. Completion of TLB
> invalidation is
> - * synchronous.
> - *
> - * Return: 0 on success, negative error code on error
> - */
> -int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
> -{
> - struct xe_gt *gt = tlb_inval->private;
> - struct xe_device *xe = gt_to_xe(gt);
> - unsigned int fw_ref;
> -
> - if (xe_guc_ct_enabled(>->uc.guc.ct) &&
> - gt->uc.guc.submission_state.enabled) {
> - struct xe_tlb_inval_fence fence;
> - int ret;
> -
> - xe_tlb_inval_fence_init(tlb_inval, &fence, true);
> - ret = xe_tlb_inval_guc(gt, &fence);
> - if (ret)
> - return ret;
>
> - xe_tlb_inval_fence_wait(&fence);
> - } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe))
> {
> - struct xe_mmio *mmio = >->mmio;
> -
> - if (IS_SRIOV_VF(xe))
> - return 0;
> -
> - fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> - if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe)
> >= 20) {
> - xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
> -
> PVC_GUC_TLB_INV_DESC1_INVALIDAT
> E);
> - xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
> - PVC_GUC_TLB_INV_DESC0_VALID);
> - } else {
> - xe_mmio_write32(mmio, GUC_TLB_INV_CR,
> - GUC_TLB_INV_CR_INVALIDATE);
> - }
> - xe_force_wake_put(gt_to_fw(gt), fw_ref);
> - }
> -
> - return 0;
> + return send_tlb_inval(>->uc.guc, action,
> ARRAY_SIZE(action));
> }
>
> static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
> @@ -345,7 +269,7 @@ static int send_tlb_inval_all(struct xe_tlb_inval
> *tlb_inval,
>
> xe_gt_assert(gt, fence);
>
> - return send_tlb_inval(>->uc.guc, fence, action,
> ARRAY_SIZE(action));
> + return send_tlb_inval(>->uc.guc, action,
> ARRAY_SIZE(action));
> }
>
> /**
> @@ -377,43 +301,17 @@ int xe_tlb_inval_all(struct xe_tlb_inval
> *tlb_inval,
> */
> #define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
>
> -/**
> - * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an
> address range
> - * @tlb_inval: TLB invalidation client
> - * @fence: invalidation fence which will be signal on TLB
> invalidation
> - * completion
> - * @start: start address
> - * @end: end address
> - * @asid: address space id
> - *
> - * Issue a range based TLB invalidation if supported, if not
> fallback to a full
> - * TLB invalidation. Completion of TLB is asynchronous and caller
> can use
> - * the invalidation fence to wait for completion.
> - *
> - * Return: Negative error code on error, 0 on success
> - */
> -int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
> - struct xe_tlb_inval_fence *fence, u64 start,
> u64 end,
> - u32 asid)
> +static int send_tlb_inval_ppgtt(struct xe_gt *gt, u64 start, u64
> end,
> + u32 asid, int seqno)
> {
> - struct xe_gt *gt = tlb_inval->private;
> - struct xe_device *xe = gt_to_xe(gt);
> #define MAX_TLB_INVALIDATION_LEN 7
> u32 action[MAX_TLB_INVALIDATION_LEN];
> u64 length = end - start;
> - int len = 0, ret;
> -
> - xe_gt_assert(gt, fence);
> -
> - /* Execlists not supported */
> - if (gt_to_xe(gt)->info.force_execlist) {
> - __inval_fence_signal(xe, fence);
> - return 0;
> - }
> + int len = 0;
>
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> - action[len++] = 0; /* seqno, replaced in send_tlb_inval */
> - if (!xe->info.has_range_tlb_inval ||
> + action[len++] = seqno;
> + if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> } else {
> @@ -462,10 +360,112 @@ int xe_tlb_inval_range(struct xe_tlb_inval
> *tlb_inval,
>
> xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
>
> + return send_tlb_inval(>->uc.guc, action, len);
> +}
> +
> +static int __xe_tlb_inval_ggtt(struct xe_gt *gt,
> + struct xe_tlb_inval_fence *fence)
> +{
> + int ret;
> +
> + xe_tlb_inval_fence_prep(fence);
> +
> + ret = send_tlb_inval_ggtt(gt, fence->seqno);
> + if (ret < 0)
> + inval_fence_signal_unlocked(gt_to_xe(gt), fence);
> +
> + /*
> + * -ECANCELED indicates the CT is stopped for a GT reset. TLB
> caches
> + * should be nuked on a GT reset so this error can be
> ignored.
> + */
> + if (ret == -ECANCELED)
> + return 0;
> +
> + return ret;
> +}
> +
> +/**
> + * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the
> GGTT
> + * @tlb_inval: TLB invalidation client
> + *
> + * Issue a TLB invalidation for the GGTT. Completion of TLB
> invalidation is
> + * synchronous.
> + *
> + * Return: 0 on success, negative error code on error
> + */
> +int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
> +{
> + struct xe_gt *gt = tlb_inval->private;
> + struct xe_device *xe = gt_to_xe(gt);
> + unsigned int fw_ref;
> +
> + if (xe_guc_ct_enabled(>->uc.guc.ct) &&
> + gt->uc.guc.submission_state.enabled) {
> + struct xe_tlb_inval_fence fence;
> + int ret;
> +
> + xe_tlb_inval_fence_init(tlb_inval, &fence, true);
> + ret = __xe_tlb_inval_ggtt(gt, &fence);
> + if (ret)
> + return ret;
> +
> + xe_tlb_inval_fence_wait(&fence);
> + } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe))
> {
> + struct xe_mmio *mmio = >->mmio;
> +
> + if (IS_SRIOV_VF(xe))
> + return 0;
> +
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> + if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe)
> >= 20) {
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
> + PVC_GUC_TLB_INV_DESC1_INVALID
> ATE);
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
> + PVC_GUC_TLB_INV_DESC0_VALID);
> + } else {
> + xe_mmio_write32(mmio, GUC_TLB_INV_CR,
> + GUC_TLB_INV_CR_INVALIDATE);
> + }
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an
> address range
> + * @tlb_inval: TLB invalidation client
> + * @fence: invalidation fence which will be signal on TLB
> invalidation
> + * completion
> + * @start: start address
> + * @end: end address
> + * @asid: address space id
> + *
> + * Issue a range based TLB invalidation if supported, if not
> fallback to a full
> + * TLB invalidation. Completion of TLB is asynchronous and caller
> can use
> + * the invalidation fence to wait for completion.
> + *
> + * Return: Negative error code on error, 0 on success
> + */
> +int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
> + struct xe_tlb_inval_fence *fence, u64 start,
> u64 end,
> + u32 asid)
> +{
> + struct xe_gt *gt = tlb_inval->private;
> + struct xe_device *xe = gt_to_xe(gt);
> + int ret;
> +
> + xe_gt_assert(gt, fence);
> +
> + /* Execlists not supported */
> + if (xe->info.force_execlist) {
> + __inval_fence_signal(xe, fence);
> + return 0;
> + }
> +
> xe_tlb_inval_fence_prep(fence);
>
> - ret = send_tlb_inval(>->uc.guc, fence, action,
> - ARRAY_SIZE(action));
> + ret = send_tlb_inval_ppgtt(gt, start, end, asid, fence-
> >seqno);
> if (ret < 0)
> inval_fence_signal_unlocked(xe, fence);
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 8/8] drm/xe: Split TLB invalidation code in frontend and backend
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (6 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 7/8] drm/xe: Add helpers to send TLB invalidations stuartsummers
@ 2025-07-30 20:45 ` stuartsummers
2025-08-06 22:19 ` Summers, Stuart
2025-07-30 20:52 ` ✗ CI.checkpatch: warning for Add TLB invalidation abstraction (rev2) Patchwork
` (3 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: stuartsummers @ 2025-07-30 20:45 UTC (permalink / raw)
Cc: matthew.brost, farah.kassabri, intel-xe, Stuart Summers
From: Matthew Brost <matthew.brost@intel.com>
The frontend exposes an API to the driver to send invalidations, handles
sequence number assignment, synchronization (fences), and provides a
timeout mechanism. The backend issues the actual invalidation to the
hardware (or firmware).
The new layering easily allows issuing TLB invalidations to different
hardware or firmware interfaces.
Normalize some naming while here too.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_guc_ct.c | 2 +-
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 242 ++++++++++++
drivers/gpu/drm/xe/xe_guc_tlb_inval.h | 19 +
drivers/gpu/drm/xe/xe_tlb_inval.c | 478 +++++++-----------------
drivers/gpu/drm/xe/xe_tlb_inval.h | 14 +-
drivers/gpu/drm/xe/xe_tlb_inval_types.h | 67 +++-
7 files changed, 470 insertions(+), 353 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.c
create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e4a363489072..65853f6e63c1 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -75,6 +75,7 @@ xe-y += xe_bb.o \
xe_guc_log.o \
xe_guc_pc.o \
xe_guc_submit.o \
+ xe_guc_tlb_inval.o \
xe_heci_gsc.o \
xe_huc.o \
xe_hw_engine.o \
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 5f38041cff4c..848065a25c44 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -30,9 +30,9 @@
#include "xe_guc_log.h"
#include "xe_guc_relay.h"
#include "xe_guc_submit.h"
+#include "xe_guc_tlb_inval.h"
#include "xe_map.h"
#include "xe_pm.h"
-#include "xe_tlb_inval.h"
#include "xe_trace_guc.h"
static void receive_g2h(struct xe_guc_ct *ct);
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
new file mode 100644
index 000000000000..6bf2103602f8
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "abi/guc_actions_abi.h"
+
+#include "xe_device.h"
+#include "xe_gt_stats.h"
+#include "xe_gt_types.h"
+#include "xe_guc.h"
+#include "xe_guc_ct.h"
+#include "xe_guc_tlb_inval.h"
+#include "xe_force_wake.h"
+#include "xe_mmio.h"
+#include "xe_tlb_inval.h"
+
+#include "regs/xe_guc_regs.h"
+
+/*
+ * XXX: The seqno algorithm relies on TLB invalidation being processed in order
+ * which they currently are by the GuC, if that changes the algorithm will need
+ * to be updated.
+ */
+
+static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int len)
+{
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ xe_gt_assert(gt, action[1]); /* Seqno */
+
+ xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
+ return xe_guc_ct_send(&guc->ct, action, len,
+ G2H_LEN_DW_TLB_INVALIDATE, 1);
+}
+
+#define MAKE_INVAL_OP(type) ((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
+ XE_GUC_TLB_INVAL_MODE_HEAVY << XE_GUC_TLB_INVAL_MODE_SHIFT | \
+ XE_GUC_TLB_INVAL_FLUSH_CACHE)
+
+static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32 seqno)
+{
+ struct xe_guc *guc = tlb_inval->private;
+ u32 action[] = {
+ XE_GUC_ACTION_TLB_INVALIDATION_ALL,
+ seqno,
+ MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
+ };
+
+ return send_tlb_inval(guc, action, ARRAY_SIZE(action));
+}
+
+static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32 seqno)
+{
+ struct xe_guc *guc = tlb_inval->private;
+ struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_device *xe = guc_to_xe(guc);
+
+ /*
+ * Returning -ECANCELED in this function is squashed at the caller and
+ * signals waiters.
+ */
+
+ if (xe_guc_ct_enabled(&guc->ct) && guc->submission_state.enabled) {
+ u32 action[] = {
+ XE_GUC_ACTION_TLB_INVALIDATION,
+ seqno,
+ MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
+ };
+
+ return send_tlb_inval(guc, action, ARRAY_SIZE(action));
+ } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
+ struct xe_mmio *mmio = >->mmio;
+ unsigned int fw_ref;
+
+ if (IS_SRIOV_VF(xe))
+ return -ECANCELED;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
+ PVC_GUC_TLB_INV_DESC1_INVALIDATE);
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
+ PVC_GUC_TLB_INV_DESC0_VALID);
+ } else {
+ xe_mmio_write32(mmio, GUC_TLB_INV_CR,
+ GUC_TLB_INV_CR_INVALIDATE);
+ }
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ }
+
+ return -ECANCELED;
+}
+
+/*
+ * Ensure that roundup_pow_of_two(length) doesn't overflow.
+ * Note that roundup_pow_of_two() operates on unsigned long,
+ * not on u64.
+ */
+#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
+
+static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
+ u64 start, u64 end, u32 asid)
+{
+#define MAX_TLB_INVALIDATION_LEN 7
+ struct xe_guc *guc = tlb_inval->private;
+ struct xe_gt *gt = guc_to_gt(guc);
+ u32 action[MAX_TLB_INVALIDATION_LEN];
+ u64 length = end - start;
+ int len = 0;
+
+ if (guc_to_xe(guc)->info.force_execlist)
+ return -ECANCELED;
+
+ action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
+ action[len++] = seqno;
+ if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
+ length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
+ action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
+ } else {
+ u64 orig_start = start;
+ u64 align;
+
+ if (length < SZ_4K)
+ length = SZ_4K;
+
+ /*
+ * We need to invalidate a higher granularity if start address
+ * is not aligned to length. When start is not aligned with
+ * length we need to find the length large enough to create an
+ * address mask covering the required range.
+ */
+ align = roundup_pow_of_two(length);
+ start = ALIGN_DOWN(start, align);
+ end = ALIGN(end, align);
+ length = align;
+ while (start + length < end) {
+ length <<= 1;
+ start = ALIGN_DOWN(orig_start, length);
+ }
+
+ /*
+ * Minimum invalidation size for a 2MB page that the hardware
+ * expects is 16MB
+ */
+ if (length >= SZ_2M) {
+ length = max_t(u64, SZ_16M, length);
+ start = ALIGN_DOWN(orig_start, length);
+ }
+
+ xe_gt_assert(gt, length >= SZ_4K);
+ xe_gt_assert(gt, is_power_of_2(length));
+ xe_gt_assert(gt, !(length & GENMASK(ilog2(SZ_16M) - 1,
+ ilog2(SZ_2M) + 1)));
+ xe_gt_assert(gt, IS_ALIGNED(start, length));
+
+ action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
+ action[len++] = asid;
+ action[len++] = lower_32_bits(start);
+ action[len++] = upper_32_bits(start);
+ action[len++] = ilog2(length) - ilog2(SZ_4K);
+ }
+
+ xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
+
+ return send_tlb_inval(guc, action, len);
+}
+
+static bool tlb_inval_initialized(struct xe_tlb_inval *tlb_inval)
+{
+ struct xe_guc *guc = tlb_inval->private;
+
+ return xe_guc_ct_initialized(&guc->ct);
+}
+
+static void tlb_inval_flush(struct xe_tlb_inval *tlb_inval)
+{
+ struct xe_guc *guc = tlb_inval->private;
+
+ LNL_FLUSH_WORK(&guc->ct.g2h_worker);
+}
+
+static long tlb_inval_timeout_delay(struct xe_tlb_inval *tlb_inval)
+{
+ struct xe_guc *guc = tlb_inval->private;
+
+ /* this reflects what HW/GuC needs to process TLB inv request */
+ const long hw_tlb_timeout = HZ / 4;
+
+ /* this estimates actual delay caused by the CTB transport */
+ long delay = xe_guc_ct_queue_proc_time_jiffies(&guc->ct);
+
+ return hw_tlb_timeout + 2 * delay;
+}
+
+static const struct xe_tlb_inval_ops guc_tlb_inval_ops = {
+ .all = send_tlb_inval_all,
+ .ggtt = send_tlb_inval_ggtt,
+ .ppgtt = send_tlb_inval_ppgtt,
+ .initialized = tlb_inval_initialized,
+ .flush = tlb_inval_flush,
+ .timeout_delay = tlb_inval_timeout_delay,
+};
+
+/**
+ * xe_guc_tlb_inval_init_early() - Init GuC TLB invalidation early
+ * @guc: GuC object
+ * @tlb_inval: TLB invalidation client
+ *
+ * Inititialize GuC TLB invalidation by setting back pointer in TLB invalidation
+ * client to the GuC and setting GuC backend ops.
+ */
+void xe_guc_tlb_inval_init_early(struct xe_guc *guc,
+ struct xe_tlb_inval *tlb_inval)
+{
+ tlb_inval->private = guc;
+ tlb_inval->ops = &guc_tlb_inval_ops;
+}
+
+/**
+ * xe_guc_tlb_inval_done_handler() - TLB invalidation done handler
+ * @guc: guc
+ * @msg: message indicating TLB invalidation done
+ * @len: length of message
+ *
+ * Parse seqno of TLB invalidation, wake any waiters for seqno, and signal any
+ * invalidation fences for seqno. Algorithm for this depends on seqno being
+ * received in-order and asserts this assumption.
+ *
+ * Return: 0 on success, -EPROTO for malformed messages.
+ */
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
+{
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ if (unlikely(len != 1))
+ return -EPROTO;
+
+ xe_tlb_inval_done_handler(>->tlb_inval, msg[0]);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.h b/drivers/gpu/drm/xe/xe_guc_tlb_inval.h
new file mode 100644
index 000000000000..07d668b02e3d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_GUC_TLB_INVAL_H_
+#define _XE_GUC_TLB_INVAL_H_
+
+#include <linux/types.h>
+
+struct xe_guc;
+struct xe_tlb_inval;
+
+void xe_guc_tlb_inval_init_early(struct xe_guc *guc,
+ struct xe_tlb_inval *tlb_inval);
+
+int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 5db7f26bce2e..c5d999b0d3fc 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -12,50 +12,45 @@
#include "xe_gt_printk.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
+#include "xe_guc_tlb_inval.h"
#include "xe_gt_stats.h"
#include "xe_tlb_inval.h"
#include "xe_mmio.h"
#include "xe_pm.h"
-#include "xe_sriov.h"
+#include "xe_tlb_inval.h"
#include "xe_trace.h"
-#include "regs/xe_guc_regs.h"
-
-#define FENCE_STACK_BIT DMA_FENCE_FLAG_USER_BITS
-/*
- * TLB inval depends on pending commands in the CT queue and then the real
- * invalidation time. Double up the time to process full CT queue
- * just to be on the safe side.
+/**
+ * DOC: Xe TLB invalidation
+ *
+ * Xe TLB invalidation is implemented in two layers. The first is the frontend
+ * API, which provides an interface for TLB invalidations to the driver code.
+ * The frontend handles seqno assignment, synchronization (fences), and the
+ * timeout mechanism. The frontend is implemented via an embedded structure
+ * xe_tlb_inval that includes a set of ops hooking into the backend. The backend
+ * interacts with the hardware (or firmware) to perform the actual invalidation.
*/
-static long tlb_timeout_jiffies(struct xe_gt *gt)
-{
- /* this reflects what HW/GuC needs to process TLB inv request */
- const long hw_tlb_timeout = HZ / 4;
- /* this estimates actual delay caused by the CTB transport */
- long delay = xe_guc_ct_queue_proc_time_jiffies(>->uc.guc.ct);
-
- return hw_tlb_timeout + 2 * delay;
-}
+#define FENCE_STACK_BIT DMA_FENCE_FLAG_USER_BITS
static void xe_tlb_inval_fence_fini(struct xe_tlb_inval_fence *fence)
{
- struct xe_gt *gt;
-
if (WARN_ON_ONCE(!fence->tlb_inval))
return;
- gt = fence->tlb_inval->private;
- xe_pm_runtime_put(gt_to_xe(gt));
+ xe_pm_runtime_put(fence->tlb_inval->xe);
fence->tlb_inval = NULL; /* fini() should be called once */
}
static void
-__inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
+xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence)
{
bool stack = test_bit(FENCE_STACK_BIT, &fence->base.flags);
- trace_xe_tlb_inval_fence_signal(xe, fence);
+ lockdep_assert_held(&fence->tlb_inval->pending_lock);
+
+ list_del(&fence->link);
+ trace_xe_tlb_inval_fence_signal(fence->tlb_inval->xe, fence);
xe_tlb_inval_fence_fini(fence);
dma_fence_signal(&fence->base);
if (!stack)
@@ -63,57 +58,50 @@ __inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
}
static void
-inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence *fence)
+xe_tlb_inval_fence_signal_unlocked(struct xe_tlb_inval_fence *fence)
{
- lockdep_assert_held(&fence->tlb_inval->pending_lock);
-
- list_del(&fence->link);
- __inval_fence_signal(xe, fence);
-}
+ struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
-static void
-inval_fence_signal_unlocked(struct xe_device *xe,
- struct xe_tlb_inval_fence *fence)
-{
- spin_lock_irq(&fence->tlb_inval->pending_lock);
- inval_fence_signal(xe, fence);
- spin_unlock_irq(&fence->tlb_inval->pending_lock);
+ spin_lock_irq(&tlb_inval->pending_lock);
+ xe_tlb_inval_fence_signal(fence);
+ spin_unlock_irq(&tlb_inval->pending_lock);
}
-static void xe_gt_tlb_fence_timeout(struct work_struct *work)
+static void xe_tlb_inval_fence_timeout(struct work_struct *work)
{
- struct xe_gt *gt = container_of(work, struct xe_gt,
- tlb_inval.fence_tdr.work);
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_tlb_inval *tlb_inval = container_of(work, struct xe_tlb_inval,
+ fence_tdr.work);
+ struct xe_device *xe = tlb_inval->xe;
struct xe_tlb_inval_fence *fence, *next;
+ long timeout_delay = tlb_inval->ops->timeout_delay(tlb_inval);
- LNL_FLUSH_WORK(>->uc.guc.ct.g2h_worker);
+ tlb_inval->ops->flush(tlb_inval);
- spin_lock_irq(>->tlb_inval.pending_lock);
+ spin_lock_irq(&tlb_inval->pending_lock);
list_for_each_entry_safe(fence, next,
- >->tlb_inval.pending_fences, link) {
+ &tlb_inval->pending_fences, link) {
s64 since_inval_ms = ktime_ms_delta(ktime_get(),
fence->inval_time);
- if (msecs_to_jiffies(since_inval_ms) < tlb_timeout_jiffies(gt))
+ if (msecs_to_jiffies(since_inval_ms) < timeout_delay)
break;
trace_xe_tlb_inval_fence_timeout(xe, fence);
- xe_gt_err(gt, "TLB invalidation fence timeout, seqno=%d recv=%d",
- fence->seqno, gt->tlb_inval.seqno_recv);
+ drm_err(&xe->drm,
+ "TLB invalidation fence timeout, seqno=%d recv=%d",
+ fence->seqno, tlb_inval->seqno_recv);
fence->base.error = -ETIME;
- inval_fence_signal(xe, fence);
+ xe_tlb_inval_fence_signal(fence);
}
- if (!list_empty(>->tlb_inval.pending_fences))
- queue_delayed_work(system_wq,
- >->tlb_inval.fence_tdr,
- tlb_timeout_jiffies(gt));
- spin_unlock_irq(>->tlb_inval.pending_lock);
+ if (!list_empty(&tlb_inval->pending_fences))
+ queue_delayed_work(system_wq, &tlb_inval->fence_tdr,
+ timeout_delay);
+ spin_unlock_irq(&tlb_inval->pending_lock);
}
/**
- * xe_tlb_inval_init_early - Initialize TLB invalidation state
+ * xe_gt_tlb_inval_init_early() - Initialize TLB invalidation state
* @gt: GT structure
*
* Initialize TLB invalidation state, purely software initialization, should
@@ -123,13 +111,12 @@ static void xe_gt_tlb_fence_timeout(struct work_struct *work)
*/
int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
{
- gt->tlb_inval.private = gt;
+ gt->tlb_inval.xe = gt_to_xe(gt);
gt->tlb_inval.seqno = 1;
INIT_LIST_HEAD(>->tlb_inval.pending_fences);
spin_lock_init(>->tlb_inval.pending_lock);
spin_lock_init(>->tlb_inval.lock);
- INIT_DELAYED_WORK(>->tlb_inval.fence_tdr,
- xe_gt_tlb_fence_timeout);
+ INIT_DELAYED_WORK(>->tlb_inval.fence_tdr, xe_tlb_inval_fence_timeout);
gt->tlb_inval.job_wq =
drmm_alloc_ordered_workqueue(>_to_xe(gt)->drm, "gt-tbl-inval-job-wq",
@@ -137,58 +124,62 @@ int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
if (IS_ERR(gt->tlb_inval.job_wq))
return PTR_ERR(gt->tlb_inval.job_wq);
+ /* XXX: Blindly setting up backend to GuC */
+ xe_guc_tlb_inval_init_early(>->uc.guc, >->tlb_inval);
+
return 0;
}
/**
- * xe_tlb_inval_reset - Initialize TLB invalidation reset
+ * xe_tlb_inval_reset() - TLB invalidation reset
* @tlb_inval: TLB invalidation client
*
* Signal any pending invalidation fences, should be called during a GT reset
*/
void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval)
{
- struct xe_gt *gt = tlb_inval->private;
struct xe_tlb_inval_fence *fence, *next;
int pending_seqno;
/*
- * we can get here before the CTs are even initialized if we're wedging
- * very early, in which case there are not going to be any pending
- * fences so we can bail immediately.
+ * we can get here before the backends are even initialized if we're
+ * wedging very early, in which case there are not going to be any
+ * pendind fences so we can bail immediately.
*/
- if (!xe_guc_ct_initialized(>->uc.guc.ct))
+ if (!tlb_inval->ops->initialized(tlb_inval))
return;
/*
- * CT channel is already disabled at this point. No new TLB requests can
+ * Backend is already disabled at this point. No new TLB requests can
* appear.
*/
- spin_lock_irq(>->tlb_inval.pending_lock);
- cancel_delayed_work(>->tlb_inval.fence_tdr);
+ spin_lock_irq(&tlb_inval->pending_lock);
+ cancel_delayed_work(&tlb_inval->fence_tdr);
/*
* We might have various kworkers waiting for TLB flushes to complete
* which are not tracked with an explicit TLB fence, however at this
- * stage that will never happen since the CT is already disabled, so
- * make sure we signal them here under the assumption that we have
+ * stage that will never happen since the backend is already disabled,
+ * so make sure we signal them here under the assumption that we have
* completed a full GT reset.
*/
- if (gt->tlb_inval.seqno == 1)
+ if (tlb_inval->seqno == 1)
pending_seqno = TLB_INVALIDATION_SEQNO_MAX - 1;
else
- pending_seqno = gt->tlb_inval.seqno - 1;
- WRITE_ONCE(gt->tlb_inval.seqno_recv, pending_seqno);
+ pending_seqno = tlb_inval->seqno - 1;
+ WRITE_ONCE(tlb_inval->seqno_recv, pending_seqno);
list_for_each_entry_safe(fence, next,
- >->tlb_inval.pending_fences, link)
- inval_fence_signal(gt_to_xe(gt), fence);
- spin_unlock_irq(>->tlb_inval.pending_lock);
+ &tlb_inval->pending_fences, link)
+ xe_tlb_inval_fence_signal(fence);
+ spin_unlock_irq(&tlb_inval->pending_lock);
}
-static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
+static bool xe_tlb_inval_seqno_past(struct xe_tlb_inval *tlb_inval, int seqno)
{
- int seqno_recv = READ_ONCE(gt->tlb_inval.seqno_recv);
+ int seqno_recv = READ_ONCE(tlb_inval->seqno_recv);
+
+ lockdep_assert_held(&tlb_inval->pending_lock);
if (seqno - seqno_recv < -(TLB_INVALIDATION_SEQNO_MAX / 2))
return false;
@@ -199,41 +190,20 @@ static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
return seqno_recv >= seqno;
}
-static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int len)
-{
- struct xe_gt *gt = guc_to_gt(guc);
-
- xe_gt_assert(gt, action[1]); /* Seqno */
-
- /*
- * XXX: The seqno algorithm relies on TLB invalidation being processed
- * in order which they currently are, if that changes the algorithm will
- * need to be updated.
- */
-
- xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
-
- return xe_guc_ct_send(&guc->ct, action, len,
- G2H_LEN_DW_TLB_INVALIDATE, 1);
-}
-
static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence *fence)
{
struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
- struct xe_gt *gt = tlb_inval->private;
- struct xe_device *xe = gt_to_xe(gt);
fence->seqno = tlb_inval->seqno;
- trace_xe_tlb_inval_fence_send(xe, fence);
+ trace_xe_tlb_inval_fence_send(tlb_inval->xe, fence);
spin_lock_irq(&tlb_inval->pending_lock);
fence->inval_time = ktime_get();
list_add_tail(&fence->link, &tlb_inval->pending_fences);
if (list_is_singular(&tlb_inval->pending_fences))
- queue_delayed_work(system_wq,
- &tlb_inval->fence_tdr,
- tlb_timeout_jiffies(gt));
+ queue_delayed_work(system_wq, &tlb_inval->fence_tdr,
+ tlb_inval->ops->timeout_delay(tlb_inval));
spin_unlock_irq(&tlb_inval->pending_lock);
tlb_inval->seqno = (tlb_inval->seqno + 1) %
@@ -242,198 +212,61 @@ static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence *fence)
tlb_inval->seqno = 1;
}
-#define MAKE_INVAL_OP(type) ((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
- XE_GUC_TLB_INVAL_MODE_HEAVY << XE_GUC_TLB_INVAL_MODE_SHIFT | \
- XE_GUC_TLB_INVAL_FLUSH_CACHE)
-
-static int send_tlb_inval_ggtt(struct xe_gt *gt, int seqno)
-{
- u32 action[] = {
- XE_GUC_ACTION_TLB_INVALIDATION,
- seqno,
- MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
- };
-
- return send_tlb_inval(>->uc.guc, action, ARRAY_SIZE(action));
-}
-
-static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
- struct xe_tlb_inval_fence *fence)
-{
- u32 action[] = {
- XE_GUC_ACTION_TLB_INVALIDATION_ALL,
- 0, /* seqno, replaced in send_tlb_inval */
- MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
- };
- struct xe_gt *gt = tlb_inval->private;
-
- xe_gt_assert(gt, fence);
-
- return send_tlb_inval(>->uc.guc, action, ARRAY_SIZE(action));
-}
+#define xe_tlb_inval_issue(__tlb_inval, __fence, op, args...) \
+({ \
+ int __ret; \
+ \
+ xe_assert((__tlb_inval)->xe, (__tlb_inval)->ops); \
+ xe_assert((__tlb_inval)->xe, (__fence)); \
+ \
+ xe_tlb_inval_fence_prep((__fence)); \
+ __ret = op((__tlb_inval), (__fence)->seqno, ##args); \
+ if (__ret < 0) \
+ xe_tlb_inval_fence_signal_unlocked((__fence)); \
+ \
+ __ret == -ECANCELED ? 0 : __ret; \
+})
/**
- * xe_gt_tlb_invalidation_all - Invalidate all TLBs across PF and all VFs.
- * @gt: the &xe_gt structure
- * @fence: the &xe_tlb_inval_fence to be signaled on completion
+ * xe_tlb_inval_all() - Issue a TLB invalidation for all TLBs
+ * @tlb_inval: TLB invalidation client
+ * @fence: invalidation fence which will be signal on TLB invalidation
+ * completion
*
- * Send a request to invalidate all TLBs across PF and all VFs.
+ * Issue a TLB invalidation for all TLBs. Completion of TLB is asynchronous and
+ * caller can use the invalidation fence to wait for completion.
*
* Return: 0 on success, negative error code on error
*/
int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence)
{
- struct xe_gt *gt = tlb_inval->private;
- int err;
-
- err = send_tlb_inval_all(tlb_inval, fence);
- if (err)
- xe_gt_err(gt, "TLB invalidation request failed (%pe)", ERR_PTR(err));
-
- return err;
-}
-
-/*
- * Ensure that roundup_pow_of_two(length) doesn't overflow.
- * Note that roundup_pow_of_two() operates on unsigned long,
- * not on u64.
- */
-#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
-
-static int send_tlb_inval_ppgtt(struct xe_gt *gt, u64 start, u64 end,
- u32 asid, int seqno)
-{
-#define MAX_TLB_INVALIDATION_LEN 7
- u32 action[MAX_TLB_INVALIDATION_LEN];
- u64 length = end - start;
- int len = 0;
-
- action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
- action[len++] = seqno;
- if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
- length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
- action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
- } else {
- u64 orig_start = start;
- u64 align;
-
- if (length < SZ_4K)
- length = SZ_4K;
-
- /*
- * We need to invalidate a higher granularity if start address
- * is not aligned to length. When start is not aligned with
- * length we need to find the length large enough to create an
- * address mask covering the required range.
- */
- align = roundup_pow_of_two(length);
- start = ALIGN_DOWN(start, align);
- end = ALIGN(end, align);
- length = align;
- while (start + length < end) {
- length <<= 1;
- start = ALIGN_DOWN(orig_start, length);
- }
-
- /*
- * Minimum invalidation size for a 2MB page that the hardware
- * expects is 16MB
- */
- if (length >= SZ_2M) {
- length = max_t(u64, SZ_16M, length);
- start = ALIGN_DOWN(orig_start, length);
- }
-
- xe_gt_assert(gt, length >= SZ_4K);
- xe_gt_assert(gt, is_power_of_2(length));
- xe_gt_assert(gt, !(length & GENMASK(ilog2(SZ_16M) - 1,
- ilog2(SZ_2M) + 1)));
- xe_gt_assert(gt, IS_ALIGNED(start, length));
-
- action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
- action[len++] = asid;
- action[len++] = lower_32_bits(start);
- action[len++] = upper_32_bits(start);
- action[len++] = ilog2(length) - ilog2(SZ_4K);
- }
-
- xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
-
- return send_tlb_inval(>->uc.guc, action, len);
-}
-
-static int __xe_tlb_inval_ggtt(struct xe_gt *gt,
- struct xe_tlb_inval_fence *fence)
-{
- int ret;
-
- xe_tlb_inval_fence_prep(fence);
-
- ret = send_tlb_inval_ggtt(gt, fence->seqno);
- if (ret < 0)
- inval_fence_signal_unlocked(gt_to_xe(gt), fence);
-
- /*
- * -ECANCELED indicates the CT is stopped for a GT reset. TLB caches
- * should be nuked on a GT reset so this error can be ignored.
- */
- if (ret == -ECANCELED)
- return 0;
-
- return ret;
+ return xe_tlb_inval_issue(tlb_inval, fence, tlb_inval->ops->all);
}
/**
- * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the GGTT
+ * xe_tlb_inval_ggtt() - Issue a TLB invalidation for the GGTT
* @tlb_inval: TLB invalidation client
*
- * Issue a TLB invalidation for the GGTT. Completion of TLB invalidation is
- * synchronous.
+ * Issue a TLB invalidation for the GGTT. Completion of TLB is asynchronous and
+ * caller can use the invalidation fence to wait for completion.
*
* Return: 0 on success, negative error code on error
*/
int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
{
- struct xe_gt *gt = tlb_inval->private;
- struct xe_device *xe = gt_to_xe(gt);
- unsigned int fw_ref;
-
- if (xe_guc_ct_enabled(>->uc.guc.ct) &&
- gt->uc.guc.submission_state.enabled) {
- struct xe_tlb_inval_fence fence;
- int ret;
-
- xe_tlb_inval_fence_init(tlb_inval, &fence, true);
- ret = __xe_tlb_inval_ggtt(gt, &fence);
- if (ret)
- return ret;
-
- xe_tlb_inval_fence_wait(&fence);
- } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
- struct xe_mmio *mmio = >->mmio;
-
- if (IS_SRIOV_VF(xe))
- return 0;
-
- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
- if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
- xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
- PVC_GUC_TLB_INV_DESC1_INVALIDATE);
- xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
- PVC_GUC_TLB_INV_DESC0_VALID);
- } else {
- xe_mmio_write32(mmio, GUC_TLB_INV_CR,
- GUC_TLB_INV_CR_INVALIDATE);
- }
- xe_force_wake_put(gt_to_fw(gt), fw_ref);
- }
+ struct xe_tlb_inval_fence fence, *fence_ptr = &fence;
+ int ret;
- return 0;
+ xe_tlb_inval_fence_init(tlb_inval, fence_ptr, true);
+ ret = xe_tlb_inval_issue(tlb_inval, fence_ptr, tlb_inval->ops->ggtt);
+ xe_tlb_inval_fence_wait(fence_ptr);
+
+ return ret;
}
/**
- * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an address range
+ * xe_tlb_inval_range() - Issue a TLB invalidation for an address range
* @tlb_inval: TLB invalidation client
* @fence: invalidation fence which will be signal on TLB invalidation
* completion
@@ -451,29 +284,12 @@ int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence, u64 start, u64 end,
u32 asid)
{
- struct xe_gt *gt = tlb_inval->private;
- struct xe_device *xe = gt_to_xe(gt);
- int ret;
-
- xe_gt_assert(gt, fence);
-
- /* Execlists not supported */
- if (xe->info.force_execlist) {
- __inval_fence_signal(xe, fence);
- return 0;
- }
-
- xe_tlb_inval_fence_prep(fence);
-
- ret = send_tlb_inval_ppgtt(gt, start, end, asid, fence->seqno);
- if (ret < 0)
- inval_fence_signal_unlocked(xe, fence);
-
- return ret;
+ return xe_tlb_inval_issue(tlb_inval, fence, tlb_inval->ops->ppgtt,
+ start, end, asid);
}
/**
- * xe_tlb_inval_vm - Issue a TLB invalidation on this GT for a VM
+ * xe_tlb_inval_vm() - Issue a TLB invalidation for a VM
* @tlb_inval: TLB invalidation client
* @vm: VM to invalidate
*
@@ -483,27 +299,22 @@ void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm)
{
struct xe_tlb_inval_fence fence;
u64 range = 1ull << vm->xe->info.va_bits;
- int ret;
xe_tlb_inval_fence_init(tlb_inval, &fence, true);
-
- ret = xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm->usm.asid);
- if (ret < 0)
- return;
-
+ xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm->usm.asid);
xe_tlb_inval_fence_wait(&fence);
}
/**
- * xe_tlb_inval_done_handler - TLB invalidation done handler
- * @gt: gt
+ * xe_tlb_inval_done_handler() - TLB invalidation done handler
+ * @tlb_inval: TLB invalidation client
* @seqno: seqno of invalidation that is done
*
* Update recv seqno, signal any TLB invalidation fences, and restart TDR
*/
-static void xe_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
+void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int seqno)
{
- struct xe_device *xe = gt_to_xe(gt);
+ struct xe_device *xe = tlb_inval->xe;
struct xe_tlb_inval_fence *fence, *next;
unsigned long flags;
@@ -522,77 +333,53 @@ static void xe_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
* officially process the CT message like if racing against
* process_g2h_msg().
*/
- spin_lock_irqsave(>->tlb_inval.pending_lock, flags);
- if (tlb_inval_seqno_past(gt, seqno)) {
- spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
+ spin_lock_irqsave(&tlb_inval->pending_lock, flags);
+ if (xe_tlb_inval_seqno_past(tlb_inval, seqno)) {
+ spin_unlock_irqrestore(&tlb_inval->pending_lock, flags);
return;
}
- WRITE_ONCE(gt->tlb_inval.seqno_recv, seqno);
+ WRITE_ONCE(tlb_inval->seqno_recv, seqno);
list_for_each_entry_safe(fence, next,
- >->tlb_inval.pending_fences, link) {
+ &tlb_inval->pending_fences, link) {
trace_xe_tlb_inval_fence_recv(xe, fence);
- if (!tlb_inval_seqno_past(gt, fence->seqno))
+ if (!xe_tlb_inval_seqno_past(tlb_inval, fence->seqno))
break;
- inval_fence_signal(xe, fence);
+ xe_tlb_inval_fence_signal(fence);
}
- if (!list_empty(>->tlb_inval.pending_fences))
+ if (!list_empty(&tlb_inval->pending_fences))
mod_delayed_work(system_wq,
- >->tlb_inval.fence_tdr,
- tlb_timeout_jiffies(gt));
+ &tlb_inval->fence_tdr,
+ tlb_inval->ops->timeout_delay(tlb_inval));
else
- cancel_delayed_work(>->tlb_inval.fence_tdr);
+ cancel_delayed_work(&tlb_inval->fence_tdr);
- spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
-}
-
-/**
- * xe_guc_tlb_inval_done_handler - TLB invalidation done handler
- * @guc: guc
- * @msg: message indicating TLB invalidation done
- * @len: length of message
- *
- * Parse seqno of TLB invalidation, wake any waiters for seqno, and signal any
- * invalidation fences for seqno. Algorithm for this depends on seqno being
- * received in-order and asserts this assumption.
- *
- * Return: 0 on success, -EPROTO for malformed messages.
- */
-int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
-{
- struct xe_gt *gt = guc_to_gt(guc);
-
- if (unlikely(len != 1))
- return -EPROTO;
-
- xe_tlb_inval_done_handler(gt, msg[0]);
-
- return 0;
+ spin_unlock_irqrestore(&tlb_inval->pending_lock, flags);
}
static const char *
-inval_fence_get_driver_name(struct dma_fence *dma_fence)
+xe_inval_fence_get_driver_name(struct dma_fence *dma_fence)
{
return "xe";
}
static const char *
-inval_fence_get_timeline_name(struct dma_fence *dma_fence)
+xe_inval_fence_get_timeline_name(struct dma_fence *dma_fence)
{
- return "inval_fence";
+ return "tlb_inval_fence";
}
static const struct dma_fence_ops inval_fence_ops = {
- .get_driver_name = inval_fence_get_driver_name,
- .get_timeline_name = inval_fence_get_timeline_name,
+ .get_driver_name = xe_inval_fence_get_driver_name,
+ .get_timeline_name = xe_inval_fence_get_timeline_name,
};
/**
- * xe_tlb_inval_fence_init - Initialize TLB invalidation fence
+ * xe_tlb_inval_fence_init() - Initialize TLB invalidation fence
* @tlb_inval: TLB invalidation client
* @fence: TLB invalidation fence to initialize
* @stack: fence is stack variable
@@ -605,15 +392,12 @@ void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
bool stack)
{
- struct xe_gt *gt = tlb_inval->private;
-
- xe_pm_runtime_get_noresume(gt_to_xe(gt));
+ xe_pm_runtime_get_noresume(tlb_inval->xe);
- spin_lock_irq(>->tlb_inval.lock);
- dma_fence_init(&fence->base, &inval_fence_ops,
- >->tlb_inval.lock,
+ spin_lock_irq(&tlb_inval->lock);
+ dma_fence_init(&fence->base, &inval_fence_ops, &tlb_inval->lock,
dma_fence_context_alloc(1), 1);
- spin_unlock_irq(>->tlb_inval.lock);
+ spin_unlock_irq(&tlb_inval->lock);
INIT_LIST_HEAD(&fence->link);
if (stack)
set_bit(FENCE_STACK_BIT, &fence->base.flags);
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.h b/drivers/gpu/drm/xe/xe_tlb_inval.h
index 7adee3f8c551..cdeafc8d4391 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.h
@@ -18,24 +18,30 @@ struct xe_vma;
int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval);
-int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
-void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm);
int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence);
+int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
+void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm);
int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
u64 start, u64 end, u32 asid);
-int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len);
void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
bool stack);
-void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence);
+/**
+ * xe_tlb_inval_fence_wait() - TLB invalidiation fence wait
+ * @fence: TLB invalidation fence to wait on
+ *
+ * Wait on a TLB invalidiation fence until it signals, non interruptable
+ */
static inline void
xe_tlb_inval_fence_wait(struct xe_tlb_inval_fence *fence)
{
dma_fence_wait(&fence->base, false);
}
+void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int seqno);
+
#endif /* _XE_TLB_INVAL_ */
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 05b6adc929bb..03ff6d718fa6 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -9,10 +9,75 @@
#include <linux/workqueue.h>
#include <linux/dma-fence.h>
-/** struct xe_tlb_inval - TLB invalidation client */
+struct xe_tlb_inval;
+
+/** struct xe_tlb_inval_ops - TLB invalidation ops (backend) */
+struct xe_tlb_inval_ops {
+ /**
+ * @all: Invalidate all TLBs
+ * @tlb_inval: TLB invalidation client
+ * @seqno: Seqno of TLB invalidation
+ *
+ * Return 0 on success, -ECANCELED if backend is mid-reset, error on
+ * failure
+ */
+ int (*all)(struct xe_tlb_inval *tlb_inval, u32 seqno);
+
+ /**
+ * @ggtt: Invalidate global translation TLBs
+ * @tlb_inval: TLB invalidation client
+ * @seqno: Seqno of TLB invalidation
+ *
+ * Return 0 on success, -ECANCELED if backend is mid-reset, error on
+ * failure
+ */
+ int (*ggtt)(struct xe_tlb_inval *tlb_inval, u32 seqno);
+
+ /**
+ * @ppttt: Invalidate per-process translation TLBs
+ * @tlb_inval: TLB invalidation client
+ * @seqno: Seqno of TLB invalidation
+ * @start: Start address
+ * @end: End address
+ * @asid: Address space ID
+ *
+ * Return 0 on success, -ECANCELED if backend is mid-reset, error on
+ * failure
+ */
+ int (*ppgtt)(struct xe_tlb_inval *tlb_inval, u32 seqno, u64 start,
+ u64 end, u32 asid);
+
+ /**
+ * @initialized: Backend is initialized
+ * @tlb_inval: TLB invalidation client
+ *
+ * Return: True if back is initialized, False otherwise
+ */
+ bool (*initialized)(struct xe_tlb_inval *tlb_inval);
+
+ /**
+ * @flush: Flush pending TLB invalidations
+ * @tlb_inval: TLB invalidation client
+ */
+ void (*flush)(struct xe_tlb_inval *tlb_inval);
+
+ /**
+ * @timeout_delay: Timeout delay for TLB invalidation
+ * @tlb_inval: TLB invalidation client
+ *
+ * Return: Timeout delay for TLB invalidation in jiffies
+ */
+ long (*timeout_delay)(struct xe_tlb_inval *tlb_inval);
+};
+
+/** struct xe_tlb_inval - TLB invalidation client (frontend) */
struct xe_tlb_inval {
/** @private: Backend private pointer */
void *private;
+ /** @xe: Pointer to Xe device */
+ struct xe_device *xe;
+ /** @ops: TLB invalidation ops */
+ const struct xe_tlb_inval_ops *ops;
/** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
#define TLB_INVALIDATION_SEQNO_MAX 0x100000
int seqno;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 8/8] drm/xe: Split TLB invalidation code in frontend and backend
2025-07-30 20:45 ` [PATCH 8/8] drm/xe: Split TLB invalidation code in frontend and backend stuartsummers
@ 2025-08-06 22:19 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2025-08-06 22:19 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew, Kassabri, Farah
On Wed, 2025-07-30 at 20:45 +0000, stuartsummers wrote:
> From: Matthew Brost <matthew.brost@intel.com>
>
> The frontend exposes an API to the driver to send invalidations,
> handles
> sequence number assignment, synchronization (fences), and provides a
> timeout mechanism. The backend issues the actual invalidation to the
> hardware (or firmware).
>
> The new layering easily allows issuing TLB invalidations to different
> hardware or firmware interfaces.
>
> Normalize some naming while here too.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_guc_ct.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 242 ++++++++++++
> drivers/gpu/drm/xe/xe_guc_tlb_inval.h | 19 +
> drivers/gpu/drm/xe/xe_tlb_inval.c | 478 +++++++---------------
> --
> drivers/gpu/drm/xe/xe_tlb_inval.h | 14 +-
> drivers/gpu/drm/xe/xe_tlb_inval_types.h | 67 +++-
> 7 files changed, 470 insertions(+), 353 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> create mode 100644 drivers/gpu/drm/xe/xe_guc_tlb_inval.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile
> b/drivers/gpu/drm/xe/Makefile
> index e4a363489072..65853f6e63c1 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -75,6 +75,7 @@ xe-y += xe_bb.o \
> xe_guc_log.o \
> xe_guc_pc.o \
> xe_guc_submit.o \
> + xe_guc_tlb_inval.o \
> xe_heci_gsc.o \
> xe_huc.o \
> xe_hw_engine.o \
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 5f38041cff4c..848065a25c44 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -30,9 +30,9 @@
> #include "xe_guc_log.h"
> #include "xe_guc_relay.h"
> #include "xe_guc_submit.h"
> +#include "xe_guc_tlb_inval.h"
> #include "xe_map.h"
> #include "xe_pm.h"
> -#include "xe_tlb_inval.h"
> #include "xe_trace_guc.h"
>
> static void receive_g2h(struct xe_guc_ct *ct);
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> new file mode 100644
> index 000000000000..6bf2103602f8
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "abi/guc_actions_abi.h"
> +
> +#include "xe_device.h"
> +#include "xe_gt_stats.h"
> +#include "xe_gt_types.h"
> +#include "xe_guc.h"
> +#include "xe_guc_ct.h"
> +#include "xe_guc_tlb_inval.h"
> +#include "xe_force_wake.h"
> +#include "xe_mmio.h"
> +#include "xe_tlb_inval.h"
> +
> +#include "regs/xe_guc_regs.h"
> +
> +/*
> + * XXX: The seqno algorithm relies on TLB invalidation being
> processed in order
> + * which they currently are by the GuC, if that changes the
> algorithm will need
> + * to be updated.
> + */
> +
> +static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int
> len)
> +{
> + struct xe_gt *gt = guc_to_gt(guc);
> +
> + xe_gt_assert(gt, action[1]); /* Seqno */
> +
> + xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
> + return xe_guc_ct_send(&guc->ct, action, len,
> + G2H_LEN_DW_TLB_INVALIDATE, 1);
> +}
> +
> +#define MAKE_INVAL_OP(type) ((type <<
> XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
> + XE_GUC_TLB_INVAL_MODE_HEAVY <<
> XE_GUC_TLB_INVAL_MODE_SHIFT | \
> + XE_GUC_TLB_INVAL_FLUSH_CACHE)
> +
> +static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32
> seqno)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> + u32 action[] = {
> + XE_GUC_ACTION_TLB_INVALIDATION_ALL,
> + seqno,
> + MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
> + };
> +
> + return send_tlb_inval(guc, action, ARRAY_SIZE(action));
> +}
> +
> +static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32
> seqno)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> + struct xe_gt *gt = guc_to_gt(guc);
> + struct xe_device *xe = guc_to_xe(guc);
> +
> + /*
> + * Returning -ECANCELED in this function is squashed at the
> caller and
> + * signals waiters.
> + */
> +
> + if (xe_guc_ct_enabled(&guc->ct) && guc-
> >submission_state.enabled) {
> + u32 action[] = {
> + XE_GUC_ACTION_TLB_INVALIDATION,
> + seqno,
> + MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
> + };
> +
> + return send_tlb_inval(guc, action,
> ARRAY_SIZE(action));
> + } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe))
> {
> + struct xe_mmio *mmio = >->mmio;
> + unsigned int fw_ref;
> +
> + if (IS_SRIOV_VF(xe))
> + return -ECANCELED;
> +
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> + if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe)
> >= 20) {
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
> + PVC_GUC_TLB_INV_DESC1_INVALID
> ATE);
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
> + PVC_GUC_TLB_INV_DESC0_VALID);
> + } else {
> + xe_mmio_write32(mmio, GUC_TLB_INV_CR,
> + GUC_TLB_INV_CR_INVALIDATE);
> + }
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + }
> +
> + return -ECANCELED;
> +}
> +
> +/*
> + * Ensure that roundup_pow_of_two(length) doesn't overflow.
> + * Note that roundup_pow_of_two() operates on unsigned long,
> + * not on u64.
> + */
> +#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
> +
> +static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32
> seqno,
> + u64 start, u64 end, u32 asid)
> +{
> +#define MAX_TLB_INVALIDATION_LEN 7
> + struct xe_guc *guc = tlb_inval->private;
> + struct xe_gt *gt = guc_to_gt(guc);
> + u32 action[MAX_TLB_INVALIDATION_LEN];
> + u64 length = end - start;
> + int len = 0;
> +
> + if (guc_to_xe(guc)->info.force_execlist)
> + return -ECANCELED;
> +
> + action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> + action[len++] = seqno;
> + if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> + length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> + } else {
> + u64 orig_start = start;
> + u64 align;
> +
> + if (length < SZ_4K)
> + length = SZ_4K;
> +
> + /*
> + * We need to invalidate a higher granularity if
> start address
> + * is not aligned to length. When start is not
> aligned with
> + * length we need to find the length large enough to
> create an
> + * address mask covering the required range.
> + */
> + align = roundup_pow_of_two(length);
> + start = ALIGN_DOWN(start, align);
> + end = ALIGN(end, align);
> + length = align;
> + while (start + length < end) {
> + length <<= 1;
> + start = ALIGN_DOWN(orig_start, length);
> + }
> +
> + /*
> + * Minimum invalidation size for a 2MB page that the
> hardware
> + * expects is 16MB
> + */
> + if (length >= SZ_2M) {
> + length = max_t(u64, SZ_16M, length);
> + start = ALIGN_DOWN(orig_start, length);
> + }
> +
> + xe_gt_assert(gt, length >= SZ_4K);
> + xe_gt_assert(gt, is_power_of_2(length));
> + xe_gt_assert(gt, !(length & GENMASK(ilog2(SZ_16M) -
> 1,
> + ilog2(SZ_2M) +
> 1)));
> + xe_gt_assert(gt, IS_ALIGNED(start, length));
> +
> + action[len++] =
> MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
> + action[len++] = asid;
> + action[len++] = lower_32_bits(start);
> + action[len++] = upper_32_bits(start);
> + action[len++] = ilog2(length) - ilog2(SZ_4K);
> + }
> +
> + xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
> +
> + return send_tlb_inval(guc, action, len);
> +}
> +
> +static bool tlb_inval_initialized(struct xe_tlb_inval *tlb_inval)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> +
> + return xe_guc_ct_initialized(&guc->ct);
> +}
> +
> +static void tlb_inval_flush(struct xe_tlb_inval *tlb_inval)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> +
> + LNL_FLUSH_WORK(&guc->ct.g2h_worker);
> +}
> +
> +static long tlb_inval_timeout_delay(struct xe_tlb_inval *tlb_inval)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> +
> + /* this reflects what HW/GuC needs to process TLB inv request
> */
> + const long hw_tlb_timeout = HZ / 4;
> +
> + /* this estimates actual delay caused by the CTB transport */
> + long delay = xe_guc_ct_queue_proc_time_jiffies(&guc->ct);
> +
> + return hw_tlb_timeout + 2 * delay;
> +}
> +
> +static const struct xe_tlb_inval_ops guc_tlb_inval_ops = {
> + .all = send_tlb_inval_all,
> + .ggtt = send_tlb_inval_ggtt,
> + .ppgtt = send_tlb_inval_ppgtt,
> + .initialized = tlb_inval_initialized,
> + .flush = tlb_inval_flush,
> + .timeout_delay = tlb_inval_timeout_delay,
> +};
> +
> +/**
> + * xe_guc_tlb_inval_init_early() - Init GuC TLB invalidation early
> + * @guc: GuC object
> + * @tlb_inval: TLB invalidation client
> + *
> + * Inititialize GuC TLB invalidation by setting back pointer in TLB
> invalidation
> + * client to the GuC and setting GuC backend ops.
> + */
> +void xe_guc_tlb_inval_init_early(struct xe_guc *guc,
> + struct xe_tlb_inval *tlb_inval)
> +{
> + tlb_inval->private = guc;
> + tlb_inval->ops = &guc_tlb_inval_ops;
> +}
> +
> +/**
> + * xe_guc_tlb_inval_done_handler() - TLB invalidation done handler
> + * @guc: guc
> + * @msg: message indicating TLB invalidation done
> + * @len: length of message
> + *
> + * Parse seqno of TLB invalidation, wake any waiters for seqno, and
> signal any
> + * invalidation fences for seqno. Algorithm for this depends on
> seqno being
> + * received in-order and asserts this assumption.
> + *
> + * Return: 0 on success, -EPROTO for malformed messages.
> + */
> +int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32
> len)
> +{
> + struct xe_gt *gt = guc_to_gt(guc);
> +
> + if (unlikely(len != 1))
> + return -EPROTO;
> +
> + xe_tlb_inval_done_handler(>->tlb_inval, msg[0]);
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.h
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.h
> new file mode 100644
> index 000000000000..07d668b02e3d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_GUC_TLB_INVAL_H_
> +#define _XE_GUC_TLB_INVAL_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_guc;
> +struct xe_tlb_inval;
> +
> +void xe_guc_tlb_inval_init_early(struct xe_guc *guc,
> + struct xe_tlb_inval *tlb_inval);
> +
> +int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32
> len);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_tlb_inval.c
> index 5db7f26bce2e..c5d999b0d3fc 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
> @@ -12,50 +12,45 @@
> #include "xe_gt_printk.h"
> #include "xe_guc.h"
> #include "xe_guc_ct.h"
> +#include "xe_guc_tlb_inval.h"
> #include "xe_gt_stats.h"
> #include "xe_tlb_inval.h"
> #include "xe_mmio.h"
> #include "xe_pm.h"
> -#include "xe_sriov.h"
> +#include "xe_tlb_inval.h"
> #include "xe_trace.h"
> -#include "regs/xe_guc_regs.h"
> -
> -#define FENCE_STACK_BIT DMA_FENCE_FLAG_USER_BITS
>
> -/*
> - * TLB inval depends on pending commands in the CT queue and then
> the real
> - * invalidation time. Double up the time to process full CT queue
> - * just to be on the safe side.
> +/**
> + * DOC: Xe TLB invalidation
> + *
> + * Xe TLB invalidation is implemented in two layers. The first is
> the frontend
> + * API, which provides an interface for TLB invalidations to the
> driver code.
> + * The frontend handles seqno assignment, synchronization (fences),
> and the
> + * timeout mechanism. The frontend is implemented via an embedded
> structure
> + * xe_tlb_inval that includes a set of ops hooking into the backend.
> The backend
> + * interacts with the hardware (or firmware) to perform the actual
> invalidation.
> */
> -static long tlb_timeout_jiffies(struct xe_gt *gt)
> -{
> - /* this reflects what HW/GuC needs to process TLB inv request
> */
> - const long hw_tlb_timeout = HZ / 4;
>
> - /* this estimates actual delay caused by the CTB transport */
> - long delay = xe_guc_ct_queue_proc_time_jiffies(>-
> >uc.guc.ct);
> -
> - return hw_tlb_timeout + 2 * delay;
> -}
> +#define FENCE_STACK_BIT DMA_FENCE_FLAG_USER_BITS
>
> static void xe_tlb_inval_fence_fini(struct xe_tlb_inval_fence
> *fence)
> {
> - struct xe_gt *gt;
> -
> if (WARN_ON_ONCE(!fence->tlb_inval))
> return;
>
> - gt = fence->tlb_inval->private;
> - xe_pm_runtime_put(gt_to_xe(gt));
> + xe_pm_runtime_put(fence->tlb_inval->xe);
> fence->tlb_inval = NULL; /* fini() should be called once */
> }
>
> static void
> -__inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence
> *fence)
> +xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence)
> {
> bool stack = test_bit(FENCE_STACK_BIT, &fence->base.flags);
>
> - trace_xe_tlb_inval_fence_signal(xe, fence);
> + lockdep_assert_held(&fence->tlb_inval->pending_lock);
> +
> + list_del(&fence->link);
> + trace_xe_tlb_inval_fence_signal(fence->tlb_inval->xe, fence);
> xe_tlb_inval_fence_fini(fence);
> dma_fence_signal(&fence->base);
> if (!stack)
> @@ -63,57 +58,50 @@ __inval_fence_signal(struct xe_device *xe, struct
> xe_tlb_inval_fence *fence)
> }
>
> static void
> -inval_fence_signal(struct xe_device *xe, struct xe_tlb_inval_fence
> *fence)
> +xe_tlb_inval_fence_signal_unlocked(struct xe_tlb_inval_fence *fence)
> {
> - lockdep_assert_held(&fence->tlb_inval->pending_lock);
> -
> - list_del(&fence->link);
> - __inval_fence_signal(xe, fence);
> -}
> + struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
>
> -static void
> -inval_fence_signal_unlocked(struct xe_device *xe,
> - struct xe_tlb_inval_fence *fence)
> -{
> - spin_lock_irq(&fence->tlb_inval->pending_lock);
> - inval_fence_signal(xe, fence);
> - spin_unlock_irq(&fence->tlb_inval->pending_lock);
> + spin_lock_irq(&tlb_inval->pending_lock);
> + xe_tlb_inval_fence_signal(fence);
> + spin_unlock_irq(&tlb_inval->pending_lock);
> }
>
> -static void xe_gt_tlb_fence_timeout(struct work_struct *work)
> +static void xe_tlb_inval_fence_timeout(struct work_struct *work)
> {
> - struct xe_gt *gt = container_of(work, struct xe_gt,
> - tlb_inval.fence_tdr.work);
> - struct xe_device *xe = gt_to_xe(gt);
> + struct xe_tlb_inval *tlb_inval = container_of(work, struct
> xe_tlb_inval,
> +
> fence_tdr.work);
> + struct xe_device *xe = tlb_inval->xe;
> struct xe_tlb_inval_fence *fence, *next;
> + long timeout_delay = tlb_inval->ops-
> >timeout_delay(tlb_inval);
>
> - LNL_FLUSH_WORK(>->uc.guc.ct.g2h_worker);
> + tlb_inval->ops->flush(tlb_inval);
>
> - spin_lock_irq(>->tlb_inval.pending_lock);
> + spin_lock_irq(&tlb_inval->pending_lock);
> list_for_each_entry_safe(fence, next,
> - >->tlb_inval.pending_fences, link)
> {
> + &tlb_inval->pending_fences, link) {
> s64 since_inval_ms = ktime_ms_delta(ktime_get(),
> fence-
> >inval_time);
>
> - if (msecs_to_jiffies(since_inval_ms) <
> tlb_timeout_jiffies(gt))
> + if (msecs_to_jiffies(since_inval_ms) < timeout_delay)
> break;
>
> trace_xe_tlb_inval_fence_timeout(xe, fence);
> - xe_gt_err(gt, "TLB invalidation fence timeout,
> seqno=%d recv=%d",
> - fence->seqno, gt->tlb_inval.seqno_recv);
> + drm_err(&xe->drm,
> + "TLB invalidation fence timeout, seqno=%d
> recv=%d",
> + fence->seqno, tlb_inval->seqno_recv);
>
> fence->base.error = -ETIME;
> - inval_fence_signal(xe, fence);
> + xe_tlb_inval_fence_signal(fence);
> }
> - if (!list_empty(>->tlb_inval.pending_fences))
> - queue_delayed_work(system_wq,
> - >->tlb_inval.fence_tdr,
> - tlb_timeout_jiffies(gt));
> - spin_unlock_irq(>->tlb_inval.pending_lock);
> + if (!list_empty(&tlb_inval->pending_fences))
> + queue_delayed_work(system_wq, &tlb_inval->fence_tdr,
> + timeout_delay);
> + spin_unlock_irq(&tlb_inval->pending_lock);
> }
>
> /**
> - * xe_tlb_inval_init_early - Initialize TLB invalidation state
> + * xe_gt_tlb_inval_init_early() - Initialize TLB invalidation state
> * @gt: GT structure
> *
> * Initialize TLB invalidation state, purely software
> initialization, should
> @@ -123,13 +111,12 @@ static void xe_gt_tlb_fence_timeout(struct
> work_struct *work)
> */
> int xe_gt_tlb_inval_init_early(struct xe_gt *gt)
> {
> - gt->tlb_inval.private = gt;
> + gt->tlb_inval.xe = gt_to_xe(gt);
> gt->tlb_inval.seqno = 1;
> INIT_LIST_HEAD(>->tlb_inval.pending_fences);
> spin_lock_init(>->tlb_inval.pending_lock);
> spin_lock_init(>->tlb_inval.lock);
> - INIT_DELAYED_WORK(>->tlb_inval.fence_tdr,
> - xe_gt_tlb_fence_timeout);
> + INIT_DELAYED_WORK(>->tlb_inval.fence_tdr,
> xe_tlb_inval_fence_timeout);
>
> gt->tlb_inval.job_wq =
> drmm_alloc_ordered_workqueue(>_to_xe(gt)->drm, "gt-
> tbl-inval-job-wq",
> @@ -137,58 +124,62 @@ int xe_gt_tlb_inval_init_early(struct xe_gt
> *gt)
> if (IS_ERR(gt->tlb_inval.job_wq))
> return PTR_ERR(gt->tlb_inval.job_wq);
>
> + /* XXX: Blindly setting up backend to GuC */
> + xe_guc_tlb_inval_init_early(>->uc.guc, >->tlb_inval);
> +
> return 0;
> }
>
> /**
> - * xe_tlb_inval_reset - Initialize TLB invalidation reset
> + * xe_tlb_inval_reset() - TLB invalidation reset
> * @tlb_inval: TLB invalidation client
> *
> * Signal any pending invalidation fences, should be called during a
> GT reset
> */
> void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval)
> {
> - struct xe_gt *gt = tlb_inval->private;
> struct xe_tlb_inval_fence *fence, *next;
> int pending_seqno;
>
> /*
> - * we can get here before the CTs are even initialized if
> we're wedging
> - * very early, in which case there are not going to be any
> pending
> - * fences so we can bail immediately.
> + * we can get here before the backends are even initialized
> if we're
> + * wedging very early, in which case there are not going to
> be any
> + * pendind fences so we can bail immediately.
> */
> - if (!xe_guc_ct_initialized(>->uc.guc.ct))
> + if (!tlb_inval->ops->initialized(tlb_inval))
> return;
>
> /*
> - * CT channel is already disabled at this point. No new TLB
> requests can
> + * Backend is already disabled at this point. No new TLB
> requests can
> * appear.
> */
>
> - spin_lock_irq(>->tlb_inval.pending_lock);
> - cancel_delayed_work(>->tlb_inval.fence_tdr);
> + spin_lock_irq(&tlb_inval->pending_lock);
> + cancel_delayed_work(&tlb_inval->fence_tdr);
> /*
> * We might have various kworkers waiting for TLB flushes to
> complete
> * which are not tracked with an explicit TLB fence, however
> at this
> - * stage that will never happen since the CT is already
> disabled, so
> - * make sure we signal them here under the assumption that we
> have
> + * stage that will never happen since the backend is already
> disabled,
> + * so make sure we signal them here under the assumption that
> we have
> * completed a full GT reset.
> */
> - if (gt->tlb_inval.seqno == 1)
> + if (tlb_inval->seqno == 1)
> pending_seqno = TLB_INVALIDATION_SEQNO_MAX - 1;
> else
> - pending_seqno = gt->tlb_inval.seqno - 1;
> - WRITE_ONCE(gt->tlb_inval.seqno_recv, pending_seqno);
> + pending_seqno = tlb_inval->seqno - 1;
> + WRITE_ONCE(tlb_inval->seqno_recv, pending_seqno);
>
> list_for_each_entry_safe(fence, next,
> - >->tlb_inval.pending_fences, link)
> - inval_fence_signal(gt_to_xe(gt), fence);
> - spin_unlock_irq(>->tlb_inval.pending_lock);
> + &tlb_inval->pending_fences, link)
> + xe_tlb_inval_fence_signal(fence);
> + spin_unlock_irq(&tlb_inval->pending_lock);
> }
>
> -static bool tlb_inval_seqno_past(struct xe_gt *gt, int seqno)
> +static bool xe_tlb_inval_seqno_past(struct xe_tlb_inval *tlb_inval,
> int seqno)
> {
> - int seqno_recv = READ_ONCE(gt->tlb_inval.seqno_recv);
> + int seqno_recv = READ_ONCE(tlb_inval->seqno_recv);
> +
> + lockdep_assert_held(&tlb_inval->pending_lock);
>
> if (seqno - seqno_recv < -(TLB_INVALIDATION_SEQNO_MAX / 2))
> return false;
> @@ -199,41 +190,20 @@ static bool tlb_inval_seqno_past(struct xe_gt
> *gt, int seqno)
> return seqno_recv >= seqno;
> }
>
> -static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int
> len)
> -{
> - struct xe_gt *gt = guc_to_gt(guc);
> -
> - xe_gt_assert(gt, action[1]); /* Seqno */
> -
> - /*
> - * XXX: The seqno algorithm relies on TLB invalidation being
> processed
> - * in order which they currently are, if that changes the
> algorithm will
> - * need to be updated.
> - */
> -
> - xe_gt_stats_incr(gt, XE_GT_STATS_ID_TLB_INVAL, 1);
> -
> - return xe_guc_ct_send(&guc->ct, action, len,
> - G2H_LEN_DW_TLB_INVALIDATE, 1);
> -}
> -
> static void xe_tlb_inval_fence_prep(struct xe_tlb_inval_fence
> *fence)
> {
> struct xe_tlb_inval *tlb_inval = fence->tlb_inval;
> - struct xe_gt *gt = tlb_inval->private;
> - struct xe_device *xe = gt_to_xe(gt);
>
> fence->seqno = tlb_inval->seqno;
> - trace_xe_tlb_inval_fence_send(xe, fence);
> + trace_xe_tlb_inval_fence_send(tlb_inval->xe, fence);
>
> spin_lock_irq(&tlb_inval->pending_lock);
> fence->inval_time = ktime_get();
> list_add_tail(&fence->link, &tlb_inval->pending_fences);
>
> if (list_is_singular(&tlb_inval->pending_fences))
> - queue_delayed_work(system_wq,
> - &tlb_inval->fence_tdr,
> - tlb_timeout_jiffies(gt));
> + queue_delayed_work(system_wq, &tlb_inval->fence_tdr,
> + tlb_inval->ops-
> >timeout_delay(tlb_inval));
> spin_unlock_irq(&tlb_inval->pending_lock);
>
> tlb_inval->seqno = (tlb_inval->seqno + 1) %
> @@ -242,198 +212,61 @@ static void xe_tlb_inval_fence_prep(struct
> xe_tlb_inval_fence *fence)
> tlb_inval->seqno = 1;
> }
>
> -#define MAKE_INVAL_OP(type) ((type <<
> XE_GUC_TLB_INVAL_TYPE_SHIFT) | \
> - XE_GUC_TLB_INVAL_MODE_HEAVY <<
> XE_GUC_TLB_INVAL_MODE_SHIFT | \
> - XE_GUC_TLB_INVAL_FLUSH_CACHE)
> -
> -static int send_tlb_inval_ggtt(struct xe_gt *gt, int seqno)
> -{
> - u32 action[] = {
> - XE_GUC_ACTION_TLB_INVALIDATION,
> - seqno,
> - MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),
> - };
> -
> - return send_tlb_inval(>->uc.guc, action,
> ARRAY_SIZE(action));
> -}
> -
> -static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
> - struct xe_tlb_inval_fence *fence)
> -{
> - u32 action[] = {
> - XE_GUC_ACTION_TLB_INVALIDATION_ALL,
> - 0, /* seqno, replaced in send_tlb_inval */
> - MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
> - };
> - struct xe_gt *gt = tlb_inval->private;
> -
> - xe_gt_assert(gt, fence);
> -
> - return send_tlb_inval(>->uc.guc, action,
> ARRAY_SIZE(action));
> -}
> +#define xe_tlb_inval_issue(__tlb_inval, __fence, op, args...) \
> +({ \
> + int __ret; \
> + \
> + xe_assert((__tlb_inval)->xe, (__tlb_inval)->ops); \
> + xe_assert((__tlb_inval)->xe, (__fence)); \
> + \
> + xe_tlb_inval_fence_prep((__fence)); \
> + __ret = op((__tlb_inval), (__fence)->seqno, ##args); \
> + if (__ret < 0) \
> + xe_tlb_inval_fence_signal_unlocked((__fence)); \
> + \
> + __ret == -ECANCELED ? 0 : __ret; \
> +})
>
> /**
> - * xe_gt_tlb_invalidation_all - Invalidate all TLBs across PF and
> all VFs.
> - * @gt: the &xe_gt structure
> - * @fence: the &xe_tlb_inval_fence to be signaled on completion
> + * xe_tlb_inval_all() - Issue a TLB invalidation for all TLBs
> + * @tlb_inval: TLB invalidation client
> + * @fence: invalidation fence which will be signal on TLB
> invalidation
> + * completion
> *
> - * Send a request to invalidate all TLBs across PF and all VFs.
> + * Issue a TLB invalidation for all TLBs. Completion of TLB is
> asynchronous and
> + * caller can use the invalidation fence to wait for completion.
> *
> * Return: 0 on success, negative error code on error
> */
> int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
> struct xe_tlb_inval_fence *fence)
> {
> - struct xe_gt *gt = tlb_inval->private;
> - int err;
> -
> - err = send_tlb_inval_all(tlb_inval, fence);
> - if (err)
> - xe_gt_err(gt, "TLB invalidation request failed
> (%pe)", ERR_PTR(err));
> -
> - return err;
> -}
> -
> -/*
> - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> - * Note that roundup_pow_of_two() operates on unsigned long,
> - * not on u64.
> - */
> -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
> -
> -static int send_tlb_inval_ppgtt(struct xe_gt *gt, u64 start, u64
> end,
> - u32 asid, int seqno)
> -{
> -#define MAX_TLB_INVALIDATION_LEN 7
> - u32 action[MAX_TLB_INVALIDATION_LEN];
> - u64 length = end - start;
> - int len = 0;
> -
> - action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> - action[len++] = seqno;
> - if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> - action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> - } else {
> - u64 orig_start = start;
> - u64 align;
> -
> - if (length < SZ_4K)
> - length = SZ_4K;
> -
> - /*
> - * We need to invalidate a higher granularity if
> start address
> - * is not aligned to length. When start is not
> aligned with
> - * length we need to find the length large enough to
> create an
> - * address mask covering the required range.
> - */
> - align = roundup_pow_of_two(length);
> - start = ALIGN_DOWN(start, align);
> - end = ALIGN(end, align);
> - length = align;
> - while (start + length < end) {
> - length <<= 1;
> - start = ALIGN_DOWN(orig_start, length);
> - }
> -
> - /*
> - * Minimum invalidation size for a 2MB page that the
> hardware
> - * expects is 16MB
> - */
> - if (length >= SZ_2M) {
> - length = max_t(u64, SZ_16M, length);
> - start = ALIGN_DOWN(orig_start, length);
> - }
> -
> - xe_gt_assert(gt, length >= SZ_4K);
> - xe_gt_assert(gt, is_power_of_2(length));
> - xe_gt_assert(gt, !(length & GENMASK(ilog2(SZ_16M) -
> 1,
> - ilog2(SZ_2M) +
> 1)));
> - xe_gt_assert(gt, IS_ALIGNED(start, length));
> -
> - action[len++] =
> MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
> - action[len++] = asid;
> - action[len++] = lower_32_bits(start);
> - action[len++] = upper_32_bits(start);
> - action[len++] = ilog2(length) - ilog2(SZ_4K);
> - }
> -
> - xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
> -
> - return send_tlb_inval(>->uc.guc, action, len);
> -}
> -
> -static int __xe_tlb_inval_ggtt(struct xe_gt *gt,
> - struct xe_tlb_inval_fence *fence)
> -{
> - int ret;
> -
> - xe_tlb_inval_fence_prep(fence);
> -
> - ret = send_tlb_inval_ggtt(gt, fence->seqno);
> - if (ret < 0)
> - inval_fence_signal_unlocked(gt_to_xe(gt), fence);
> -
> - /*
> - * -ECANCELED indicates the CT is stopped for a GT reset. TLB
> caches
> - * should be nuked on a GT reset so this error can be
> ignored.
> - */
> - if (ret == -ECANCELED)
> - return 0;
> -
> - return ret;
> + return xe_tlb_inval_issue(tlb_inval, fence, tlb_inval->ops-
> >all);
> }
>
> /**
> - * xe_tlb_inval_ggtt - Issue a TLB invalidation on this GT for the
> GGTT
> + * xe_tlb_inval_ggtt() - Issue a TLB invalidation for the GGTT
> * @tlb_inval: TLB invalidation client
> *
> - * Issue a TLB invalidation for the GGTT. Completion of TLB
> invalidation is
> - * synchronous.
> + * Issue a TLB invalidation for the GGTT. Completion of TLB is
> asynchronous and
> + * caller can use the invalidation fence to wait for completion.
> *
> * Return: 0 on success, negative error code on error
> */
> int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval)
> {
> - struct xe_gt *gt = tlb_inval->private;
> - struct xe_device *xe = gt_to_xe(gt);
> - unsigned int fw_ref;
> -
> - if (xe_guc_ct_enabled(>->uc.guc.ct) &&
> - gt->uc.guc.submission_state.enabled) {
> - struct xe_tlb_inval_fence fence;
> - int ret;
> -
> - xe_tlb_inval_fence_init(tlb_inval, &fence, true);
> - ret = __xe_tlb_inval_ggtt(gt, &fence);
> - if (ret)
> - return ret;
> -
> - xe_tlb_inval_fence_wait(&fence);
> - } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe))
> {
> - struct xe_mmio *mmio = >->mmio;
> -
> - if (IS_SRIOV_VF(xe))
> - return 0;
> -
> - fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> - if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe)
> >= 20) {
> - xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
> -
> PVC_GUC_TLB_INV_DESC1_INVALIDAT
> E);
> - xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
> - PVC_GUC_TLB_INV_DESC0_VALID);
> - } else {
> - xe_mmio_write32(mmio, GUC_TLB_INV_CR,
> - GUC_TLB_INV_CR_INVALIDATE);
> - }
> - xe_force_wake_put(gt_to_fw(gt), fw_ref);
> - }
> + struct xe_tlb_inval_fence fence, *fence_ptr = &fence;
> + int ret;
>
> - return 0;
> + xe_tlb_inval_fence_init(tlb_inval, fence_ptr, true);
> + ret = xe_tlb_inval_issue(tlb_inval, fence_ptr, tlb_inval-
> >ops->ggtt);
> + xe_tlb_inval_fence_wait(fence_ptr);
> +
> + return ret;
> }
>
> /**
> - * xe_tlb_inval_range - Issue a TLB invalidation on this GT for an
> address range
> + * xe_tlb_inval_range() - Issue a TLB invalidation for an address
> range
> * @tlb_inval: TLB invalidation client
> * @fence: invalidation fence which will be signal on TLB
> invalidation
> * completion
> @@ -451,29 +284,12 @@ int xe_tlb_inval_range(struct xe_tlb_inval
> *tlb_inval,
> struct xe_tlb_inval_fence *fence, u64 start,
> u64 end,
> u32 asid)
> {
> - struct xe_gt *gt = tlb_inval->private;
> - struct xe_device *xe = gt_to_xe(gt);
> - int ret;
> -
> - xe_gt_assert(gt, fence);
> -
> - /* Execlists not supported */
> - if (xe->info.force_execlist) {
> - __inval_fence_signal(xe, fence);
> - return 0;
> - }
> -
> - xe_tlb_inval_fence_prep(fence);
> -
> - ret = send_tlb_inval_ppgtt(gt, start, end, asid, fence-
> >seqno);
> - if (ret < 0)
> - inval_fence_signal_unlocked(xe, fence);
> -
> - return ret;
> + return xe_tlb_inval_issue(tlb_inval, fence, tlb_inval->ops-
> >ppgtt,
> + start, end, asid);
> }
>
> /**
> - * xe_tlb_inval_vm - Issue a TLB invalidation on this GT for a VM
> + * xe_tlb_inval_vm() - Issue a TLB invalidation for a VM
> * @tlb_inval: TLB invalidation client
> * @vm: VM to invalidate
> *
> @@ -483,27 +299,22 @@ void xe_tlb_inval_vm(struct xe_tlb_inval
> *tlb_inval, struct xe_vm *vm)
> {
> struct xe_tlb_inval_fence fence;
> u64 range = 1ull << vm->xe->info.va_bits;
> - int ret;
>
> xe_tlb_inval_fence_init(tlb_inval, &fence, true);
> -
> - ret = xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm-
> >usm.asid);
> - if (ret < 0)
> - return;
> -
> + xe_tlb_inval_range(tlb_inval, &fence, 0, range, vm-
> >usm.asid);
> xe_tlb_inval_fence_wait(&fence);
> }
>
> /**
> - * xe_tlb_inval_done_handler - TLB invalidation done handler
> - * @gt: gt
> + * xe_tlb_inval_done_handler() - TLB invalidation done handler
> + * @tlb_inval: TLB invalidation client
> * @seqno: seqno of invalidation that is done
> *
> * Update recv seqno, signal any TLB invalidation fences, and
> restart TDR
> */
> -static void xe_tlb_inval_done_handler(struct xe_gt *gt, int seqno)
> +void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int
> seqno)
> {
> - struct xe_device *xe = gt_to_xe(gt);
> + struct xe_device *xe = tlb_inval->xe;
> struct xe_tlb_inval_fence *fence, *next;
> unsigned long flags;
>
> @@ -522,77 +333,53 @@ static void xe_tlb_inval_done_handler(struct
> xe_gt *gt, int seqno)
> * officially process the CT message like if racing against
> * process_g2h_msg().
> */
> - spin_lock_irqsave(>->tlb_inval.pending_lock, flags);
> - if (tlb_inval_seqno_past(gt, seqno)) {
> - spin_unlock_irqrestore(>->tlb_inval.pending_lock,
> flags);
> + spin_lock_irqsave(&tlb_inval->pending_lock, flags);
> + if (xe_tlb_inval_seqno_past(tlb_inval, seqno)) {
> + spin_unlock_irqrestore(&tlb_inval->pending_lock,
> flags);
> return;
> }
>
> - WRITE_ONCE(gt->tlb_inval.seqno_recv, seqno);
> + WRITE_ONCE(tlb_inval->seqno_recv, seqno);
>
> list_for_each_entry_safe(fence, next,
> - >->tlb_inval.pending_fences, link)
> {
> + &tlb_inval->pending_fences, link) {
> trace_xe_tlb_inval_fence_recv(xe, fence);
>
> - if (!tlb_inval_seqno_past(gt, fence->seqno))
> + if (!xe_tlb_inval_seqno_past(tlb_inval, fence-
> >seqno))
> break;
>
> - inval_fence_signal(xe, fence);
> + xe_tlb_inval_fence_signal(fence);
> }
>
> - if (!list_empty(>->tlb_inval.pending_fences))
> + if (!list_empty(&tlb_inval->pending_fences))
> mod_delayed_work(system_wq,
> - >->tlb_inval.fence_tdr,
> - tlb_timeout_jiffies(gt));
> + &tlb_inval->fence_tdr,
> + tlb_inval->ops-
> >timeout_delay(tlb_inval));
> else
> - cancel_delayed_work(>->tlb_inval.fence_tdr);
> + cancel_delayed_work(&tlb_inval->fence_tdr);
>
> - spin_unlock_irqrestore(>->tlb_inval.pending_lock, flags);
> -}
> -
> -/**
> - * xe_guc_tlb_inval_done_handler - TLB invalidation done handler
> - * @guc: guc
> - * @msg: message indicating TLB invalidation done
> - * @len: length of message
> - *
> - * Parse seqno of TLB invalidation, wake any waiters for seqno, and
> signal any
> - * invalidation fences for seqno. Algorithm for this depends on
> seqno being
> - * received in-order and asserts this assumption.
> - *
> - * Return: 0 on success, -EPROTO for malformed messages.
> - */
> -int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32
> len)
> -{
> - struct xe_gt *gt = guc_to_gt(guc);
> -
> - if (unlikely(len != 1))
> - return -EPROTO;
> -
> - xe_tlb_inval_done_handler(gt, msg[0]);
> -
> - return 0;
> + spin_unlock_irqrestore(&tlb_inval->pending_lock, flags);
> }
>
> static const char *
> -inval_fence_get_driver_name(struct dma_fence *dma_fence)
> +xe_inval_fence_get_driver_name(struct dma_fence *dma_fence)
> {
> return "xe";
> }
>
> static const char *
> -inval_fence_get_timeline_name(struct dma_fence *dma_fence)
> +xe_inval_fence_get_timeline_name(struct dma_fence *dma_fence)
> {
> - return "inval_fence";
> + return "tlb_inval_fence";
> }
>
> static const struct dma_fence_ops inval_fence_ops = {
> - .get_driver_name = inval_fence_get_driver_name,
> - .get_timeline_name = inval_fence_get_timeline_name,
> + .get_driver_name = xe_inval_fence_get_driver_name,
> + .get_timeline_name = xe_inval_fence_get_timeline_name,
> };
>
> /**
> - * xe_tlb_inval_fence_init - Initialize TLB invalidation fence
> + * xe_tlb_inval_fence_init() - Initialize TLB invalidation fence
> * @tlb_inval: TLB invalidation client
> * @fence: TLB invalidation fence to initialize
> * @stack: fence is stack variable
> @@ -605,15 +392,12 @@ void xe_tlb_inval_fence_init(struct
> xe_tlb_inval *tlb_inval,
> struct xe_tlb_inval_fence *fence,
> bool stack)
> {
> - struct xe_gt *gt = tlb_inval->private;
> -
> - xe_pm_runtime_get_noresume(gt_to_xe(gt));
> + xe_pm_runtime_get_noresume(tlb_inval->xe);
>
> - spin_lock_irq(>->tlb_inval.lock);
> - dma_fence_init(&fence->base, &inval_fence_ops,
> - >->tlb_inval.lock,
> + spin_lock_irq(&tlb_inval->lock);
> + dma_fence_init(&fence->base, &inval_fence_ops, &tlb_inval-
> >lock,
> dma_fence_context_alloc(1), 1);
> - spin_unlock_irq(>->tlb_inval.lock);
> + spin_unlock_irq(&tlb_inval->lock);
> INIT_LIST_HEAD(&fence->link);
> if (stack)
> set_bit(FENCE_STACK_BIT, &fence->base.flags);
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.h
> b/drivers/gpu/drm/xe/xe_tlb_inval.h
> index 7adee3f8c551..cdeafc8d4391 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval.h
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval.h
> @@ -18,24 +18,30 @@ struct xe_vma;
> int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
>
> void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval);
> -int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
> -void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm
> *vm);
> int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
> struct xe_tlb_inval_fence *fence);
> +int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
> +void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm
> *vm);
> int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
> struct xe_tlb_inval_fence *fence,
> u64 start, u64 end, u32 asid);
> -int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32
> len);
>
> void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
> struct xe_tlb_inval_fence *fence,
> bool stack);
> -void xe_tlb_inval_fence_signal(struct xe_tlb_inval_fence *fence);
>
> +/**
> + * xe_tlb_inval_fence_wait() - TLB invalidiation fence wait
> + * @fence: TLB invalidation fence to wait on
> + *
> + * Wait on a TLB invalidiation fence until it signals, non
> interruptable
> + */
> static inline void
> xe_tlb_inval_fence_wait(struct xe_tlb_inval_fence *fence)
> {
> dma_fence_wait(&fence->base, false);
> }
>
> +void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int
> seqno);
> +
> #endif /* _XE_TLB_INVAL_ */
> diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
> b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
> index 05b6adc929bb..03ff6d718fa6 100644
> --- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
> +++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
> @@ -9,10 +9,75 @@
> #include <linux/workqueue.h>
> #include <linux/dma-fence.h>
>
> -/** struct xe_tlb_inval - TLB invalidation client */
> +struct xe_tlb_inval;
> +
> +/** struct xe_tlb_inval_ops - TLB invalidation ops (backend) */
> +struct xe_tlb_inval_ops {
> + /**
> + * @all: Invalidate all TLBs
> + * @tlb_inval: TLB invalidation client
> + * @seqno: Seqno of TLB invalidation
> + *
> + * Return 0 on success, -ECANCELED if backend is mid-reset,
> error on
> + * failure
> + */
> + int (*all)(struct xe_tlb_inval *tlb_inval, u32 seqno);
> +
> + /**
> + * @ggtt: Invalidate global translation TLBs
> + * @tlb_inval: TLB invalidation client
> + * @seqno: Seqno of TLB invalidation
> + *
> + * Return 0 on success, -ECANCELED if backend is mid-reset,
> error on
> + * failure
> + */
> + int (*ggtt)(struct xe_tlb_inval *tlb_inval, u32 seqno);
> +
> + /**
> + * @ppttt: Invalidate per-process translation TLBs
Minor spelling issue in the doc here (ppttt vs ppgtt) - I'll clean up
here shortly.
Otherwise lgtm:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> + * @tlb_inval: TLB invalidation client
> + * @seqno: Seqno of TLB invalidation
> + * @start: Start address
> + * @end: End address
> + * @asid: Address space ID
> + *
> + * Return 0 on success, -ECANCELED if backend is mid-reset,
> error on
> + * failure
> + */
> + int (*ppgtt)(struct xe_tlb_inval *tlb_inval, u32 seqno, u64
> start,
> + u64 end, u32 asid);
> +
> + /**
> + * @initialized: Backend is initialized
> + * @tlb_inval: TLB invalidation client
> + *
> + * Return: True if back is initialized, False otherwise
> + */
> + bool (*initialized)(struct xe_tlb_inval *tlb_inval);
> +
> + /**
> + * @flush: Flush pending TLB invalidations
> + * @tlb_inval: TLB invalidation client
> + */
> + void (*flush)(struct xe_tlb_inval *tlb_inval);
> +
> + /**
> + * @timeout_delay: Timeout delay for TLB invalidation
> + * @tlb_inval: TLB invalidation client
> + *
> + * Return: Timeout delay for TLB invalidation in jiffies
> + */
> + long (*timeout_delay)(struct xe_tlb_inval *tlb_inval);
> +};
> +
> +/** struct xe_tlb_inval - TLB invalidation client (frontend) */
> struct xe_tlb_inval {
> /** @private: Backend private pointer */
> void *private;
> + /** @xe: Pointer to Xe device */
> + struct xe_device *xe;
> + /** @ops: TLB invalidation ops */
> + const struct xe_tlb_inval_ops *ops;
> /** @tlb_inval.seqno: TLB invalidation seqno, protected by CT
> lock */
> #define TLB_INVALIDATION_SEQNO_MAX 0x100000
> int seqno;
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ CI.checkpatch: warning for Add TLB invalidation abstraction (rev2)
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (7 preceding siblings ...)
2025-07-30 20:45 ` [PATCH 8/8] drm/xe: Split TLB invalidation code in frontend and backend stuartsummers
@ 2025-07-30 20:52 ` Patchwork
2025-07-30 20:53 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-07-30 20:52 UTC (permalink / raw)
To: stuartsummers; +Cc: intel-xe
== Series Details ==
Series: Add TLB invalidation abstraction (rev2)
URL : https://patchwork.freedesktop.org/series/152022/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c298eac5978c38dcc62a70c0d73c91765e7cc296
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit cc0a7a766e1eb3465bc58b86c32eff842ec5f1ba
Author: Matthew Brost <matthew.brost@intel.com>
Date: Wed Jul 30 20:45:14 2025 +0000
drm/xe: Split TLB invalidation code in frontend and backend
The frontend exposes an API to the driver to send invalidations, handles
sequence number assignment, synchronization (fences), and provides a
timeout mechanism. The backend issues the actual invalidation to the
hardware (or firmware).
The new layering easily allows issuing TLB invalidations to different
hardware or firmware interfaces.
Normalize some naming while here too.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
+ /mt/dim checkpatch bca98310921a3284d7c2f0bc96828f06b3eb7f3a drm-intel
b9ac9cf0691e drm/xe: Move explicit CT lock in TLB invalidation sequence
e2faeae2cc84 drm/xe: s/tlb_invalidation/tlb_inval
-:128: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#128:
rename from drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
total: 0 errors, 1 warnings, 0 checks, 1100 lines checked
74101fea3190 drm/xe: Add xe_tlb_inval structure
6d3521b48a85 drm/xe: Add xe_gt_tlb_invalidation_done_handler
b4544329fda2 drm/xe: Decouple TLB invalidations from GT
-:102: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#102:
deleted file mode 100644
total: 0 errors, 1 warnings, 0 checks, 1236 lines checked
05ad732e1892 drm/xe: Prep TLB invalidation fence before sending
45f016fe0434 drm/xe: Add helpers to send TLB invalidations
cc0a7a766e1e drm/xe: Split TLB invalidation code in frontend and backend
-:47: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#47:
new file mode 100644
-:649: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__tlb_inval' - possible side-effects?
#649: FILE: drivers/gpu/drm/xe/xe_tlb_inval.c:215:
+#define xe_tlb_inval_issue(__tlb_inval, __fence, op, args...) \
+({ \
+ int __ret; \
+ \
+ xe_assert((__tlb_inval)->xe, (__tlb_inval)->ops); \
+ xe_assert((__tlb_inval)->xe, (__fence)); \
+ \
+ xe_tlb_inval_fence_prep((__fence)); \
+ __ret = op((__tlb_inval), (__fence)->seqno, ##args); \
+ if (__ret < 0) \
+ xe_tlb_inval_fence_signal_unlocked((__fence)); \
+ \
+ __ret == -ECANCELED ? 0 : __ret; \
+})
-:649: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__fence' - possible side-effects?
#649: FILE: drivers/gpu/drm/xe/xe_tlb_inval.c:215:
+#define xe_tlb_inval_issue(__tlb_inval, __fence, op, args...) \
+({ \
+ int __ret; \
+ \
+ xe_assert((__tlb_inval)->xe, (__tlb_inval)->ops); \
+ xe_assert((__tlb_inval)->xe, (__fence)); \
+ \
+ xe_tlb_inval_fence_prep((__fence)); \
+ __ret = op((__tlb_inval), (__fence)->seqno, ##args); \
+ if (__ret < 0) \
+ xe_tlb_inval_fence_signal_unlocked((__fence)); \
+ \
+ __ret == -ECANCELED ? 0 : __ret; \
+})
total: 0 errors, 1 warnings, 2 checks, 1084 lines checked
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ CI.KUnit: success for Add TLB invalidation abstraction (rev2)
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (8 preceding siblings ...)
2025-07-30 20:52 ` ✗ CI.checkpatch: warning for Add TLB invalidation abstraction (rev2) Patchwork
@ 2025-07-30 20:53 ` Patchwork
2025-07-30 21:55 ` ✓ Xe.CI.BAT: " Patchwork
2025-07-30 22:59 ` ✗ Xe.CI.Full: failure " Patchwork
11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-07-30 20:53 UTC (permalink / raw)
To: stuartsummers; +Cc: intel-xe
== Series Details ==
Series: Add TLB invalidation abstraction (rev2)
URL : https://patchwork.freedesktop.org/series/152022/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:52:09] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:52:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:52:40] Starting KUnit Kernel (1/1)...
[20:52:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:52:40] ================== guc_buf (11 subtests) ===================
[20:52:40] [PASSED] test_smallest
[20:52:40] [PASSED] test_largest
[20:52:40] [PASSED] test_granular
[20:52:40] [PASSED] test_unique
[20:52:40] [PASSED] test_overlap
[20:52:40] [PASSED] test_reusable
[20:52:40] [PASSED] test_too_big
[20:52:40] [PASSED] test_flush
[20:52:40] [PASSED] test_lookup
[20:52:40] [PASSED] test_data
[20:52:40] [PASSED] test_class
[20:52:40] ===================== [PASSED] guc_buf =====================
[20:52:40] =================== guc_dbm (7 subtests) ===================
[20:52:40] [PASSED] test_empty
[20:52:40] [PASSED] test_default
[20:52:40] ======================== test_size ========================
[20:52:40] [PASSED] 4
[20:52:40] [PASSED] 8
[20:52:40] [PASSED] 32
[20:52:40] [PASSED] 256
[20:52:40] ==================== [PASSED] test_size ====================
[20:52:40] ======================= test_reuse ========================
[20:52:40] [PASSED] 4
[20:52:40] [PASSED] 8
[20:52:40] [PASSED] 32
[20:52:40] [PASSED] 256
[20:52:40] =================== [PASSED] test_reuse ====================
[20:52:40] =================== test_range_overlap ====================
[20:52:40] [PASSED] 4
[20:52:40] [PASSED] 8
[20:52:40] [PASSED] 32
[20:52:40] [PASSED] 256
[20:52:40] =============== [PASSED] test_range_overlap ================
[20:52:40] =================== test_range_compact ====================
[20:52:40] [PASSED] 4
[20:52:40] [PASSED] 8
[20:52:40] [PASSED] 32
[20:52:40] [PASSED] 256
[20:52:40] =============== [PASSED] test_range_compact ================
[20:52:40] ==================== test_range_spare =====================
[20:52:40] [PASSED] 4
[20:52:40] [PASSED] 8
[20:52:40] [PASSED] 32
[20:52:40] [PASSED] 256
[20:52:40] ================ [PASSED] test_range_spare =================
[20:52:40] ===================== [PASSED] guc_dbm =====================
[20:52:40] =================== guc_idm (6 subtests) ===================
[20:52:40] [PASSED] bad_init
[20:52:40] [PASSED] no_init
[20:52:40] [PASSED] init_fini
[20:52:40] [PASSED] check_used
[20:52:40] [PASSED] check_quota
[20:52:40] [PASSED] check_all
[20:52:40] ===================== [PASSED] guc_idm =====================
[20:52:40] ================== no_relay (3 subtests) ===================
[20:52:40] [PASSED] xe_drops_guc2pf_if_not_ready
[20:52:40] [PASSED] xe_drops_guc2vf_if_not_ready
[20:52:40] [PASSED] xe_rejects_send_if_not_ready
[20:52:40] ==================== [PASSED] no_relay =====================
[20:52:40] ================== pf_relay (14 subtests) ==================
[20:52:40] [PASSED] pf_rejects_guc2pf_too_short
[20:52:40] [PASSED] pf_rejects_guc2pf_too_long
[20:52:40] [PASSED] pf_rejects_guc2pf_no_payload
[20:52:40] [PASSED] pf_fails_no_payload
[20:52:40] [PASSED] pf_fails_bad_origin
[20:52:40] [PASSED] pf_fails_bad_type
[20:52:40] [PASSED] pf_txn_reports_error
[20:52:40] [PASSED] pf_txn_sends_pf2guc
[20:52:40] [PASSED] pf_sends_pf2guc
[20:52:40] [SKIPPED] pf_loopback_nop
[20:52:40] [SKIPPED] pf_loopback_echo
[20:52:40] [SKIPPED] pf_loopback_fail
[20:52:40] [SKIPPED] pf_loopback_busy
[20:52:40] [SKIPPED] pf_loopback_retry
[20:52:40] ==================== [PASSED] pf_relay =====================
[20:52:40] ================== vf_relay (3 subtests) ===================
[20:52:40] [PASSED] vf_rejects_guc2vf_too_short
[20:52:40] [PASSED] vf_rejects_guc2vf_too_long
[20:52:40] [PASSED] vf_rejects_guc2vf_no_payload
[20:52:40] ==================== [PASSED] vf_relay =====================
[20:52:40] ===================== lmtt (1 subtest) =====================
[20:52:40] ======================== test_ops =========================
[20:52:40] [PASSED] 2-level
[20:52:40] [PASSED] multi-level
[20:52:40] ==================== [PASSED] test_ops =====================
[20:52:40] ====================== [PASSED] lmtt =======================
[20:52:40] ================= pf_service (11 subtests) =================
[20:52:40] [PASSED] pf_negotiate_any
[20:52:40] [PASSED] pf_negotiate_base_match
[20:52:40] [PASSED] pf_negotiate_base_newer
[20:52:40] [PASSED] pf_negotiate_base_next
[20:52:40] [SKIPPED] pf_negotiate_base_older
[20:52:40] [PASSED] pf_negotiate_base_prev
[20:52:40] [PASSED] pf_negotiate_latest_match
[20:52:40] [PASSED] pf_negotiate_latest_newer
[20:52:40] [PASSED] pf_negotiate_latest_next
[20:52:40] [SKIPPED] pf_negotiate_latest_older
[20:52:40] [SKIPPED] pf_negotiate_latest_prev
[20:52:40] =================== [PASSED] pf_service ====================
[20:52:40] =================== xe_mocs (2 subtests) ===================
[20:52:40] ================ xe_live_mocs_kernel_kunit ================
[20:52:40] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:52:40] ================ xe_live_mocs_reset_kunit =================
[20:52:40] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:52:40] ==================== [SKIPPED] xe_mocs =====================
[20:52:40] ================= xe_migrate (2 subtests) ==================
[20:52:40] ================= xe_migrate_sanity_kunit =================
[20:52:40] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:52:40] ================== xe_validate_ccs_kunit ==================
[20:52:40] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:52:40] =================== [SKIPPED] xe_migrate ===================
[20:52:40] ================== xe_dma_buf (1 subtest) ==================
[20:52:40] ==================== xe_dma_buf_kunit =====================
[20:52:40] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:52:40] =================== [SKIPPED] xe_dma_buf ===================
[20:52:40] ================= xe_bo_shrink (1 subtest) =================
[20:52:40] =================== xe_bo_shrink_kunit ====================
[20:52:40] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:52:40] ================== [SKIPPED] xe_bo_shrink ==================
[20:52:40] ==================== xe_bo (2 subtests) ====================
[20:52:40] ================== xe_ccs_migrate_kunit ===================
[20:52:40] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:52:40] ==================== xe_bo_evict_kunit ====================
[20:52:40] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:52:40] ===================== [SKIPPED] xe_bo ======================
[20:52:40] ==================== args (11 subtests) ====================
[20:52:40] [PASSED] count_args_test
[20:52:40] [PASSED] call_args_example
[20:52:40] [PASSED] call_args_test
[20:52:40] [PASSED] drop_first_arg_example
[20:52:40] [PASSED] drop_first_arg_test
[20:52:40] [PASSED] first_arg_example
[20:52:40] [PASSED] first_arg_test
[20:52:40] [PASSED] last_arg_example
[20:52:40] [PASSED] last_arg_test
[20:52:40] [PASSED] pick_arg_example
[20:52:40] [PASSED] sep_comma_example
[20:52:40] ====================== [PASSED] args =======================
[20:52:40] =================== xe_pci (3 subtests) ====================
[20:52:40] ==================== check_graphics_ip ====================
[20:52:40] [PASSED] 12.70 Xe_LPG
[20:52:40] [PASSED] 12.71 Xe_LPG
[20:52:40] [PASSED] 12.74 Xe_LPG+
[20:52:40] [PASSED] 20.01 Xe2_HPG
[20:52:40] [PASSED] 20.02 Xe2_HPG
[20:52:40] [PASSED] 20.04 Xe2_LPG
[20:52:40] [PASSED] 30.00 Xe3_LPG
[20:52:40] [PASSED] 30.01 Xe3_LPG
[20:52:40] [PASSED] 30.03 Xe3_LPG
[20:52:40] ================ [PASSED] check_graphics_ip ================
[20:52:40] ===================== check_media_ip ======================
[20:52:40] [PASSED] 13.00 Xe_LPM+
[20:52:40] [PASSED] 13.01 Xe2_HPM
[20:52:40] [PASSED] 20.00 Xe2_LPM
[20:52:40] [PASSED] 30.00 Xe3_LPM
[20:52:40] [PASSED] 30.02 Xe3_LPM
[20:52:40] ================= [PASSED] check_media_ip ==================
[20:52:40] ================= check_platform_gt_count =================
[20:52:40] [PASSED] 0x9A60 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A68 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A70 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A40 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A49 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A59 (TIGERLAKE)
[20:52:40] [PASSED] 0x9A78 (TIGERLAKE)
[20:52:40] [PASSED] 0x9AC0 (TIGERLAKE)
[20:52:40] [PASSED] 0x9AC9 (TIGERLAKE)
[20:52:40] [PASSED] 0x9AD9 (TIGERLAKE)
[20:52:40] [PASSED] 0x9AF8 (TIGERLAKE)
[20:52:40] [PASSED] 0x4C80 (ROCKETLAKE)
[20:52:40] [PASSED] 0x4C8A (ROCKETLAKE)
[20:52:40] [PASSED] 0x4C8B (ROCKETLAKE)
[20:52:40] [PASSED] 0x4C8C (ROCKETLAKE)
[20:52:40] [PASSED] 0x4C90 (ROCKETLAKE)
[20:52:40] [PASSED] 0x4C9A (ROCKETLAKE)
[20:52:40] [PASSED] 0x4680 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4682 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4688 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x468A (ALDERLAKE_S)
[20:52:40] [PASSED] 0x468B (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4690 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4692 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4693 (ALDERLAKE_S)
[20:52:40] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46AA (ALDERLAKE_P)
[20:52:40] [PASSED] 0x462A (ALDERLAKE_P)
[20:52:40] [PASSED] 0x4626 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x4628 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:52:40] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:52:40] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:52:40] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:52:40] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:52:40] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:52:40] [PASSED] 0xA721 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA720 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:52:40] [PASSED] 0xA780 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA781 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA782 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA783 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA788 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA789 (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA78A (ALDERLAKE_S)
[20:52:40] [PASSED] 0xA78B (ALDERLAKE_S)
[20:52:40] [PASSED] 0x4905 (DG1)
[20:52:40] [PASSED] 0x4906 (DG1)
[20:52:40] [PASSED] 0x4907 (DG1)
[20:52:40] [PASSED] 0x4908 (DG1)
[20:52:40] [PASSED] 0x4909 (DG1)
[20:52:40] [PASSED] 0x56C0 (DG2)
[20:52:40] [PASSED] 0x56C2 (DG2)
[20:52:40] [PASSED] 0x56C1 (DG2)
[20:52:40] [PASSED] 0x7D51 (METEORLAKE)
[20:52:40] [PASSED] 0x7DD1 (METEORLAKE)
[20:52:40] [PASSED] 0x7D41 (METEORLAKE)
[20:52:40] [PASSED] 0x7D67 (METEORLAKE)
[20:52:40] [PASSED] 0xB640 (METEORLAKE)
[20:52:40] [PASSED] 0x56A0 (DG2)
[20:52:40] [PASSED] 0x56A1 (DG2)
[20:52:40] [PASSED] 0x56A2 (DG2)
[20:52:40] [PASSED] 0x56BE (DG2)
[20:52:40] [PASSED] 0x56BF (DG2)
[20:52:40] [PASSED] 0x5690 (DG2)
[20:52:40] [PASSED] 0x5691 (DG2)
[20:52:40] [PASSED] 0x5692 (DG2)
[20:52:40] [PASSED] 0x56A5 (DG2)
[20:52:40] [PASSED] 0x56A6 (DG2)
[20:52:40] [PASSED] 0x56B0 (DG2)
[20:52:40] [PASSED] 0x56B1 (DG2)
[20:52:40] [PASSED] 0x56BA (DG2)
[20:52:40] [PASSED] 0x56BB (DG2)
[20:52:40] [PASSED] 0x56BC (DG2)
[20:52:40] [PASSED] 0x56BD (DG2)
[20:52:40] [PASSED] 0x5693 (DG2)
[20:52:40] [PASSED] 0x5694 (DG2)
[20:52:40] [PASSED] 0x5695 (DG2)
[20:52:40] [PASSED] 0x56A3 (DG2)
[20:52:40] [PASSED] 0x56A4 (DG2)
[20:52:40] [PASSED] 0x56B2 (DG2)
[20:52:40] [PASSED] 0x56B3 (DG2)
[20:52:40] [PASSED] 0x5696 (DG2)
[20:52:40] [PASSED] 0x5697 (DG2)
[20:52:40] [PASSED] 0xB69 (PVC)
[20:52:40] [PASSED] 0xB6E (PVC)
[20:52:40] [PASSED] 0xBD4 (PVC)
[20:52:40] [PASSED] 0xBD5 (PVC)
[20:52:40] [PASSED] 0xBD6 (PVC)
[20:52:40] [PASSED] 0xBD7 (PVC)
[20:52:40] [PASSED] 0xBD8 (PVC)
[20:52:40] [PASSED] 0xBD9 (PVC)
[20:52:40] [PASSED] 0xBDA (PVC)
[20:52:40] [PASSED] 0xBDB (PVC)
[20:52:40] [PASSED] 0xBE0 (PVC)
[20:52:40] [PASSED] 0xBE1 (PVC)
[20:52:40] [PASSED] 0xBE5 (PVC)
[20:52:40] [PASSED] 0x7D40 (METEORLAKE)
[20:52:40] [PASSED] 0x7D45 (METEORLAKE)
[20:52:40] [PASSED] 0x7D55 (METEORLAKE)
[20:52:40] [PASSED] 0x7D60 (METEORLAKE)
[20:52:40] [PASSED] 0x7DD5 (METEORLAKE)
[20:52:40] [PASSED] 0x6420 (LUNARLAKE)
[20:52:40] [PASSED] 0x64A0 (LUNARLAKE)
[20:52:40] [PASSED] 0x64B0 (LUNARLAKE)
[20:52:40] [PASSED] 0xE202 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE209 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE20B (BATTLEMAGE)
[20:52:40] [PASSED] 0xE20C (BATTLEMAGE)
[20:52:40] [PASSED] 0xE20D (BATTLEMAGE)
[20:52:40] [PASSED] 0xE210 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE211 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE212 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE216 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE220 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE221 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE222 (BATTLEMAGE)
[20:52:40] [PASSED] 0xE223 (BATTLEMAGE)
[20:52:40] [PASSED] 0xB080 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB081 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB082 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB083 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB084 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB085 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB086 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB087 (PANTHERLAKE)
[20:52:40] [PASSED] 0xB08F (PANTHERLAKE)
[20:52:40] [PASSED] 0xB090 (PANTHERLAKE)
[20:52:41] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:52:41] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:52:41] [PASSED] 0xFD80 (PANTHERLAKE)
[20:52:41] [PASSED] 0xFD81 (PANTHERLAKE)
[20:52:41] ============= [PASSED] check_platform_gt_count =============
[20:52:41] ===================== [PASSED] xe_pci ======================
[20:52:41] =================== xe_rtp (2 subtests) ====================
[20:52:41] =============== xe_rtp_process_to_sr_tests ================
[20:52:41] [PASSED] coalesce-same-reg
[20:52:41] [PASSED] no-match-no-add
[20:52:41] [PASSED] match-or
[20:52:41] [PASSED] match-or-xfail
[20:52:41] [PASSED] no-match-no-add-multiple-rules
[20:52:41] [PASSED] two-regs-two-entries
[20:52:41] [PASSED] clr-one-set-other
[20:52:41] [PASSED] set-field
[20:52:41] [PASSED] conflict-duplicate
[20:52:41] [PASSED] conflict-not-disjoint
[20:52:41] [PASSED] conflict-reg-type
[20:52:41] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:52:41] ================== xe_rtp_process_tests ===================
[20:52:41] [PASSED] active1
[20:52:41] [PASSED] active2
[20:52:41] [PASSED] active-inactive
[20:52:41] [PASSED] inactive-active
[20:52:41] [PASSED] inactive-1st_or_active-inactive
[20:52:41] [PASSED] inactive-2nd_or_active-inactive
[20:52:41] [PASSED] inactive-last_or_active-inactive
[20:52:41] [PASSED] inactive-no_or_active-inactive
[20:52:41] ============== [PASSED] xe_rtp_process_tests ===============
[20:52:41] ===================== [PASSED] xe_rtp ======================
[20:52:41] ==================== xe_wa (1 subtest) =====================
[20:52:41] ======================== xe_wa_gt =========================
[20:52:41] [PASSED] TIGERLAKE (B0)
[20:52:41] [PASSED] DG1 (A0)
[20:52:41] [PASSED] DG1 (B0)
[20:52:41] [PASSED] ALDERLAKE_S (A0)
[20:52:41] [PASSED] ALDERLAKE_S (B0)
[20:52:41] [PASSED] ALDERLAKE_S (C0)
[20:52:41] [PASSED] ALDERLAKE_S (D0)
[20:52:41] [PASSED] ALDERLAKE_P (A0)
[20:52:41] [PASSED] ALDERLAKE_P (B0)
[20:52:41] [PASSED] ALDERLAKE_P (C0)
[20:52:41] [PASSED] ALDERLAKE_S_RPLS (D0)
[20:52:41] [PASSED] ALDERLAKE_P_RPLU (E0)
[20:52:41] [PASSED] DG2_G10 (C0)
[20:52:41] [PASSED] DG2_G11 (B1)
[20:52:41] [PASSED] DG2_G12 (A1)
[20:52:41] [PASSED] METEORLAKE (g:A0, m:A0)
[20:52:41] [PASSED] METEORLAKE (g:A0, m:A0)
[20:52:41] [PASSED] METEORLAKE (g:A0, m:A0)
[20:52:41] [PASSED] LUNARLAKE (g:A0, m:A0)
[20:52:41] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[20:52:41] [PASSED] BATTLEMAGE (g:A0, m:A1)
[20:52:41] ==================== [PASSED] xe_wa_gt =====================
[20:52:41] ====================== [PASSED] xe_wa ======================
[20:52:41] ============================================================
[20:52:41] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[20:52:41] Elapsed time: 31.610s total, 4.163s configuring, 27.081s building, 0.312s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:52:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:52:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:53:04] Starting KUnit Kernel (1/1)...
[20:53:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:53:04] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:53:04] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:53:04] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:53:04] =========== drm_validate_clone_mode (2 subtests) ===========
[20:53:04] ============== drm_test_check_in_clone_mode ===============
[20:53:04] [PASSED] in_clone_mode
[20:53:04] [PASSED] not_in_clone_mode
[20:53:04] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:53:04] =============== drm_test_check_valid_clones ===============
[20:53:04] [PASSED] not_in_clone_mode
[20:53:04] [PASSED] valid_clone
[20:53:04] [PASSED] invalid_clone
[20:53:04] =========== [PASSED] drm_test_check_valid_clones ===========
[20:53:04] ============= [PASSED] drm_validate_clone_mode =============
[20:53:04] ============= drm_validate_modeset (1 subtest) =============
[20:53:04] [PASSED] drm_test_check_connector_changed_modeset
[20:53:04] ============== [PASSED] drm_validate_modeset ===============
[20:53:04] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:53:04] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:53:04] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:53:04] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:53:04] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:53:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:53:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:53:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:53:04] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:53:04] ============== drm_bridge_alloc (2 subtests) ===============
[20:53:04] [PASSED] drm_test_drm_bridge_alloc_basic
[20:53:04] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:53:04] ================ [PASSED] drm_bridge_alloc =================
[20:53:04] ================== drm_buddy (7 subtests) ==================
[20:53:04] [PASSED] drm_test_buddy_alloc_limit
[20:53:04] [PASSED] drm_test_buddy_alloc_optimistic
[20:53:04] [PASSED] drm_test_buddy_alloc_pessimistic
[20:53:04] [PASSED] drm_test_buddy_alloc_pathological
[20:53:04] [PASSED] drm_test_buddy_alloc_contiguous
[20:53:04] [PASSED] drm_test_buddy_alloc_clear
[20:53:04] [PASSED] drm_test_buddy_alloc_range_bias
[20:53:04] ==================== [PASSED] drm_buddy ====================
[20:53:04] ============= drm_cmdline_parser (40 subtests) =============
[20:53:04] [PASSED] drm_test_cmdline_force_d_only
[20:53:04] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:53:04] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:53:04] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:53:04] [PASSED] drm_test_cmdline_force_e_only
[20:53:04] [PASSED] drm_test_cmdline_res
[20:53:04] [PASSED] drm_test_cmdline_res_vesa
[20:53:04] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:53:04] [PASSED] drm_test_cmdline_res_rblank
[20:53:04] [PASSED] drm_test_cmdline_res_bpp
[20:53:04] [PASSED] drm_test_cmdline_res_refresh
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:53:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:53:04] [PASSED] drm_test_cmdline_res_margins_force_on
[20:53:04] [PASSED] drm_test_cmdline_res_vesa_margins
[20:53:04] [PASSED] drm_test_cmdline_name
[20:53:04] [PASSED] drm_test_cmdline_name_bpp
[20:53:04] [PASSED] drm_test_cmdline_name_option
[20:53:04] [PASSED] drm_test_cmdline_name_bpp_option
[20:53:04] [PASSED] drm_test_cmdline_rotate_0
[20:53:04] [PASSED] drm_test_cmdline_rotate_90
[20:53:04] [PASSED] drm_test_cmdline_rotate_180
[20:53:04] [PASSED] drm_test_cmdline_rotate_270
[20:53:04] [PASSED] drm_test_cmdline_hmirror
[20:53:04] [PASSED] drm_test_cmdline_vmirror
[20:53:04] [PASSED] drm_test_cmdline_margin_options
[20:53:04] [PASSED] drm_test_cmdline_multiple_options
[20:53:04] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:53:04] [PASSED] drm_test_cmdline_extra_and_option
[20:53:04] [PASSED] drm_test_cmdline_freestanding_options
[20:53:04] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:53:04] [PASSED] drm_test_cmdline_panel_orientation
[20:53:04] ================ drm_test_cmdline_invalid =================
[20:53:04] [PASSED] margin_only
[20:53:04] [PASSED] interlace_only
[20:53:04] [PASSED] res_missing_x
[20:53:04] [PASSED] res_missing_y
[20:53:04] [PASSED] res_bad_y
[20:53:04] [PASSED] res_missing_y_bpp
[20:53:04] [PASSED] res_bad_bpp
[20:53:04] [PASSED] res_bad_refresh
[20:53:04] [PASSED] res_bpp_refresh_force_on_off
[20:53:04] [PASSED] res_invalid_mode
[20:53:04] [PASSED] res_bpp_wrong_place_mode
[20:53:04] [PASSED] name_bpp_refresh
[20:53:04] [PASSED] name_refresh
[20:53:04] [PASSED] name_refresh_wrong_mode
[20:53:04] [PASSED] name_refresh_invalid_mode
[20:53:04] [PASSED] rotate_multiple
[20:53:04] [PASSED] rotate_invalid_val
[20:53:04] [PASSED] rotate_truncated
[20:53:04] [PASSED] invalid_option
[20:53:04] [PASSED] invalid_tv_option
[20:53:04] [PASSED] truncated_tv_option
[20:53:04] ============ [PASSED] drm_test_cmdline_invalid =============
[20:53:04] =============== drm_test_cmdline_tv_options ===============
[20:53:04] [PASSED] NTSC
[20:53:04] [PASSED] NTSC_443
[20:53:04] [PASSED] NTSC_J
[20:53:04] [PASSED] PAL
[20:53:04] [PASSED] PAL_M
[20:53:04] [PASSED] PAL_N
[20:53:04] [PASSED] SECAM
[20:53:04] [PASSED] MONO_525
[20:53:04] [PASSED] MONO_625
[20:53:04] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:53:04] =============== [PASSED] drm_cmdline_parser ================
[20:53:04] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:53:04] [PASSED] drm_test_connector_hdmi_init_valid
[20:53:04] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:53:04] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:53:04] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:53:04] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:53:04] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:53:04] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:53:04] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:53:04] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:53:04] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:53:04] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:53:04] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:53:04] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:53:04] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:53:04] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:53:04] [PASSED] drm_test_connector_hdmi_init_null_product
[20:53:04] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:53:04] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:53:04] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:53:04] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:53:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:53:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:53:04] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:53:04] ========= drm_test_connector_hdmi_init_type_valid =========
[20:53:04] [PASSED] HDMI-A
[20:53:04] [PASSED] HDMI-B
[20:53:04] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:53:04] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:53:04] [PASSED] Unknown
[20:53:04] [PASSED] VGA
[20:53:04] [PASSED] DVI-I
[20:53:04] [PASSED] DVI-D
[20:53:04] [PASSED] DVI-A
[20:53:04] [PASSED] Composite
[20:53:04] [PASSED] SVIDEO
[20:53:04] [PASSED] LVDS
[20:53:04] [PASSED] Component
[20:53:04] [PASSED] DIN
[20:53:04] [PASSED] DP
[20:53:04] [PASSED] TV
[20:53:04] [PASSED] eDP
[20:53:04] [PASSED] Virtual
[20:53:04] [PASSED] DSI
[20:53:04] [PASSED] DPI
[20:53:04] [PASSED] Writeback
[20:53:04] [PASSED] SPI
[20:53:04] [PASSED] USB
[20:53:04] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:53:04] ============ [PASSED] drmm_connector_hdmi_init =============
[20:53:04] ============= drmm_connector_init (3 subtests) =============
[20:53:04] [PASSED] drm_test_drmm_connector_init
[20:53:04] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:53:04] ========= drm_test_drmm_connector_init_type_valid =========
[20:53:04] [PASSED] Unknown
[20:53:04] [PASSED] VGA
[20:53:04] [PASSED] DVI-I
[20:53:04] [PASSED] DVI-D
[20:53:04] [PASSED] DVI-A
[20:53:04] [PASSED] Composite
[20:53:04] [PASSED] SVIDEO
[20:53:04] [PASSED] LVDS
[20:53:04] [PASSED] Component
[20:53:04] [PASSED] DIN
[20:53:04] [PASSED] DP
[20:53:04] [PASSED] HDMI-A
[20:53:04] [PASSED] HDMI-B
[20:53:04] [PASSED] TV
[20:53:04] [PASSED] eDP
[20:53:04] [PASSED] Virtual
[20:53:04] [PASSED] DSI
[20:53:04] [PASSED] DPI
[20:53:04] [PASSED] Writeback
[20:53:04] [PASSED] SPI
[20:53:04] [PASSED] USB
[20:53:04] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:53:04] =============== [PASSED] drmm_connector_init ===============
[20:53:04] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_init
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:53:04] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:53:04] [PASSED] Unknown
[20:53:04] [PASSED] VGA
[20:53:04] [PASSED] DVI-I
[20:53:04] [PASSED] DVI-D
[20:53:04] [PASSED] DVI-A
[20:53:04] [PASSED] Composite
[20:53:04] [PASSED] SVIDEO
[20:53:04] [PASSED] LVDS
[20:53:04] [PASSED] Component
[20:53:04] [PASSED] DIN
[20:53:04] [PASSED] DP
[20:53:04] [PASSED] HDMI-A
[20:53:04] [PASSED] HDMI-B
[20:53:04] [PASSED] TV
[20:53:04] [PASSED] eDP
[20:53:04] [PASSED] Virtual
[20:53:04] [PASSED] DSI
[20:53:04] [PASSED] DPI
[20:53:04] [PASSED] Writeback
[20:53:04] [PASSED] SPI
[20:53:04] [PASSED] USB
[20:53:04] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:53:04] ======== drm_test_drm_connector_dynamic_init_name =========
[20:53:04] [PASSED] Unknown
[20:53:04] [PASSED] VGA
[20:53:04] [PASSED] DVI-I
[20:53:04] [PASSED] DVI-D
[20:53:04] [PASSED] DVI-A
[20:53:04] [PASSED] Composite
[20:53:04] [PASSED] SVIDEO
[20:53:04] [PASSED] LVDS
[20:53:04] [PASSED] Component
[20:53:04] [PASSED] DIN
[20:53:04] [PASSED] DP
[20:53:04] [PASSED] HDMI-A
[20:53:04] [PASSED] HDMI-B
[20:53:04] [PASSED] TV
[20:53:04] [PASSED] eDP
[20:53:04] [PASSED] Virtual
[20:53:04] [PASSED] DSI
[20:53:04] [PASSED] DPI
[20:53:04] [PASSED] Writeback
[20:53:04] [PASSED] SPI
[20:53:04] [PASSED] USB
[20:53:04] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:53:04] =========== [PASSED] drm_connector_dynamic_init ============
[20:53:04] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:53:04] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:53:04] ======= drm_connector_dynamic_register (7 subtests) ========
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:53:04] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:53:04] ========= [PASSED] drm_connector_dynamic_register ==========
[20:53:04] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:53:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:53:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:53:04] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:53:04] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:53:04] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:53:04] [PASSED] NTSC
[20:53:04] [PASSED] NTSC-443
[20:53:04] [PASSED] NTSC-J
[20:53:04] [PASSED] PAL
[20:53:04] [PASSED] PAL-M
[20:53:04] [PASSED] PAL-N
[20:53:04] [PASSED] SECAM
[20:53:04] [PASSED] Mono
[20:53:04] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:53:04] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:53:04] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:53:04] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:53:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:53:04] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:53:04] [PASSED] VIC 96
[20:53:04] [PASSED] VIC 97
[20:53:04] [PASSED] VIC 101
[20:53:04] [PASSED] VIC 102
[20:53:04] [PASSED] VIC 106
[20:53:04] [PASSED] VIC 107
[20:53:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:53:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:53:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:53:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:53:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:53:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:53:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:53:04] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:53:04] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:53:04] [PASSED] Automatic
[20:53:04] [PASSED] Full
[20:53:04] [PASSED] Limited 16:235
[20:53:04] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:53:04] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:53:04] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:53:04] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:53:04] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:53:04] [PASSED] RGB
[20:53:04] [PASSED] YUV 4:2:0
[20:53:04] [PASSED] YUV 4:2:2
[20:53:04] [PASSED] YUV 4:4:4
[20:53:04] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:53:04] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:53:04] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:53:04] ============= drm_damage_helper (21 subtests) ==============
[20:53:04] [PASSED] drm_test_damage_iter_no_damage
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:53:04] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:53:04] [PASSED] drm_test_damage_iter_simple_damage
[20:53:04] [PASSED] drm_test_damage_iter_single_damage
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:53:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:53:04] [PASSED] drm_test_damage_iter_damage
[20:53:04] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:53:04] [PASSED] drm_test_damage_iter_damage_one_outside
[20:53:04] [PASSED] drm_test_damage_iter_damage_src_moved
[20:53:04] [PASSED] drm_test_damage_iter_damage_not_visible
[20:53:04] ================ [PASSED] drm_damage_helper ================
[20:53:04] ============== drm_dp_mst_helper (3 subtests) ==============
[20:53:04] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:53:04] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:53:04] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:53:04] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:53:04] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:53:04] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:53:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:53:04] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:53:04] [PASSED] Link rate 2000000 lane count 4
[20:53:04] [PASSED] Link rate 2000000 lane count 2
[20:53:04] [PASSED] Link rate 2000000 lane count 1
[20:53:04] [PASSED] Link rate 1350000 lane count 4
[20:53:04] [PASSED] Link rate 1350000 lane count 2
[20:53:04] [PASSED] Link rate 1350000 lane count 1
[20:53:04] [PASSED] Link rate 1000000 lane count 4
[20:53:04] [PASSED] Link rate 1000000 lane count 2
[20:53:04] [PASSED] Link rate 1000000 lane count 1
[20:53:04] [PASSED] Link rate 810000 lane count 4
[20:53:04] [PASSED] Link rate 810000 lane count 2
[20:53:04] [PASSED] Link rate 810000 lane count 1
[20:53:04] [PASSED] Link rate 540000 lane count 4
[20:53:04] [PASSED] Link rate 540000 lane count 2
[20:53:04] [PASSED] Link rate 540000 lane count 1
[20:53:04] [PASSED] Link rate 270000 lane count 4
[20:53:04] [PASSED] Link rate 270000 lane count 2
[20:53:04] [PASSED] Link rate 270000 lane count 1
[20:53:04] [PASSED] Link rate 162000 lane count 4
[20:53:04] [PASSED] Link rate 162000 lane count 2
[20:53:04] [PASSED] Link rate 162000 lane count 1
[20:53:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:53:04] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:53:04] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:53:04] [PASSED] DP_POWER_UP_PHY with port number
[20:53:04] [PASSED] DP_POWER_DOWN_PHY with port number
[20:53:04] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:53:04] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:53:04] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:53:04] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:53:04] [PASSED] DP_QUERY_PAYLOAD with port number
[20:53:04] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:53:04] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:53:04] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:53:04] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:53:04] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:53:04] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:53:04] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:53:04] [PASSED] DP_REMOTE_I2C_READ with port number
[20:53:04] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:53:04] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:53:04] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:53:04] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:53:04] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:53:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:53:04] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:53:04] ================ [PASSED] drm_dp_mst_helper ================
[20:53:04] ================== drm_exec (7 subtests) ===================
[20:53:04] [PASSED] sanitycheck
[20:53:04] [PASSED] test_lock
[20:53:04] [PASSED] test_lock_unlock
[20:53:04] [PASSED] test_duplicates
[20:53:04] [PASSED] test_prepare
[20:53:04] [PASSED] test_prepare_array
[20:53:04] [PASSED] test_multiple_loops
[20:53:04] ==================== [PASSED] drm_exec =====================
[20:53:04] =========== drm_format_helper_test (17 subtests) ===========
[20:53:04] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:53:04] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:53:04] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:53:04] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:53:04] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:53:04] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:53:04] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:53:04] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:53:04] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:53:04] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:53:04] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:53:04] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:53:04] ==================== drm_test_fb_swab =====================
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ================ [PASSED] drm_test_fb_swab =================
[20:53:04] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:53:04] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:53:04] [PASSED] single_pixel_source_buffer
[20:53:04] [PASSED] single_pixel_clip_rectangle
[20:53:04] [PASSED] well_known_colors
[20:53:04] [PASSED] destination_pitch
[20:53:04] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:53:04] ================= drm_test_fb_clip_offset =================
[20:53:04] [PASSED] pass through
[20:53:04] [PASSED] horizontal offset
[20:53:04] [PASSED] vertical offset
[20:53:04] [PASSED] horizontal and vertical offset
[20:53:04] [PASSED] horizontal offset (custom pitch)
[20:53:04] [PASSED] vertical offset (custom pitch)
[20:53:04] [PASSED] horizontal and vertical offset (custom pitch)
[20:53:04] ============= [PASSED] drm_test_fb_clip_offset =============
[20:53:04] =================== drm_test_fb_memcpy ====================
[20:53:04] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:53:04] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:53:04] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:53:04] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:53:04] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:53:04] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:53:04] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:53:04] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:53:04] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:53:04] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:53:04] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:53:04] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:53:04] =============== [PASSED] drm_test_fb_memcpy ================
[20:53:04] ============= [PASSED] drm_format_helper_test ==============
[20:53:04] ================= drm_format (18 subtests) =================
[20:53:04] [PASSED] drm_test_format_block_width_invalid
[20:53:04] [PASSED] drm_test_format_block_width_one_plane
[20:53:04] [PASSED] drm_test_format_block_width_two_plane
[20:53:04] [PASSED] drm_test_format_block_width_three_plane
[20:53:04] [PASSED] drm_test_format_block_width_tiled
[20:53:04] [PASSED] drm_test_format_block_height_invalid
[20:53:04] [PASSED] drm_test_format_block_height_one_plane
[20:53:04] [PASSED] drm_test_format_block_height_two_plane
[20:53:04] [PASSED] drm_test_format_block_height_three_plane
[20:53:04] [PASSED] drm_test_format_block_height_tiled
[20:53:04] [PASSED] drm_test_format_min_pitch_invalid
[20:53:04] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:53:04] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:53:04] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:53:04] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:53:04] [PASSED] drm_test_format_min_pitch_two_plane
[20:53:04] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:53:04] [PASSED] drm_test_format_min_pitch_tiled
[20:53:04] =================== [PASSED] drm_format ====================
[20:53:04] ============== drm_framebuffer (10 subtests) ===============
[20:53:04] ========== drm_test_framebuffer_check_src_coords ==========
[20:53:04] [PASSED] Success: source fits into fb
[20:53:04] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:53:04] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:53:04] [PASSED] Fail: overflowing fb with source width
[20:53:04] [PASSED] Fail: overflowing fb with source height
[20:53:04] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:53:04] [PASSED] drm_test_framebuffer_cleanup
[20:53:04] =============== drm_test_framebuffer_create ===============
[20:53:04] [PASSED] ABGR8888 normal sizes
[20:53:04] [PASSED] ABGR8888 max sizes
[20:53:04] [PASSED] ABGR8888 pitch greater than min required
[20:53:04] [PASSED] ABGR8888 pitch less than min required
[20:53:04] [PASSED] ABGR8888 Invalid width
[20:53:04] [PASSED] ABGR8888 Invalid buffer handle
[20:53:04] [PASSED] No pixel format
[20:53:04] [PASSED] ABGR8888 Width 0
[20:53:04] [PASSED] ABGR8888 Height 0
[20:53:04] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:53:04] [PASSED] ABGR8888 Large buffer offset
[20:53:04] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:53:04] [PASSED] ABGR8888 Invalid flag
[20:53:04] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:53:04] [PASSED] ABGR8888 Valid buffer modifier
[20:53:04] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:53:04] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] NV12 Normal sizes
[20:53:04] [PASSED] NV12 Max sizes
[20:53:04] [PASSED] NV12 Invalid pitch
[20:53:04] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:53:04] [PASSED] NV12 different modifier per-plane
[20:53:04] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:53:04] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] NV12 Modifier for inexistent plane
[20:53:04] [PASSED] NV12 Handle for inexistent plane
[20:53:04] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:53:04] [PASSED] YVU420 Normal sizes
[20:53:04] [PASSED] YVU420 Max sizes
[20:53:04] [PASSED] YVU420 Invalid pitch
[20:53:04] [PASSED] YVU420 Different pitches
[20:53:04] [PASSED] YVU420 Different buffer offsets/pitches
[20:53:04] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:53:04] [PASSED] YVU420 Valid modifier
[20:53:04] [PASSED] YVU420 Different modifiers per plane
[20:53:04] [PASSED] YVU420 Modifier for inexistent plane
[20:53:04] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:53:04] [PASSED] X0L2 Normal sizes
[20:53:04] [PASSED] X0L2 Max sizes
[20:53:04] [PASSED] X0L2 Invalid pitch
[20:53:04] [PASSED] X0L2 Pitch greater than minimum required
[20:53:04] [PASSED] X0L2 Handle for inexistent plane
[20:53:04] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:53:04] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:53:04] [PASSED] X0L2 Valid modifier
[20:53:04] [PASSED] X0L2 Modifier for inexistent plane
[20:53:04] =========== [PASSED] drm_test_framebuffer_create ===========
[20:53:04] [PASSED] drm_test_framebuffer_free
[20:53:04] [PASSED] drm_test_framebuffer_init
[20:53:04] [PASSED] drm_test_framebuffer_init_bad_format
[20:53:04] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:53:04] [PASSED] drm_test_framebuffer_lookup
[20:53:04] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:53:04] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:53:04] ================= [PASSED] drm_framebuffer =================
[20:53:04] ================ drm_gem_shmem (8 subtests) ================
[20:53:04] [PASSED] drm_gem_shmem_test_obj_create
[20:53:04] [PASSED] drm_gem_shmem_test_obj_create_private
[20:53:04] [PASSED] drm_gem_shmem_test_pin_pages
[20:53:04] [PASSED] drm_gem_shmem_test_vmap
[20:53:04] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:53:04] [PASSED] drm_gem_shmem_test_get_sg_table
[20:53:04] [PASSED] drm_gem_shmem_test_madvise
[20:53:04] [PASSED] drm_gem_shmem_test_purge
[20:53:04] ================== [PASSED] drm_gem_shmem ==================
[20:53:04] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:53:04] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:53:04] [PASSED] Automatic
[20:53:04] [PASSED] Full
[20:53:04] [PASSED] Limited 16:235
[20:53:04] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:53:04] [PASSED] drm_test_check_disable_connector
[20:53:04] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:53:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:53:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:53:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:53:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:53:04] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:53:04] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:53:04] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:53:04] [PASSED] drm_test_check_output_bpc_dvi
[20:53:04] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:53:04] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:53:04] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:53:04] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:53:04] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:53:04] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:53:04] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:53:04] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:53:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:53:04] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:53:04] [PASSED] drm_test_check_broadcast_rgb_value
[20:53:04] [PASSED] drm_test_check_bpc_8_value
[20:53:04] [PASSED] drm_test_check_bpc_10_value
[20:53:04] [PASSED] drm_test_check_bpc_12_value
[20:53:04] [PASSED] drm_test_check_format_value
[20:53:04] [PASSED] drm_test_check_tmds_char_value
[20:53:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:53:04] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:53:04] [PASSED] drm_test_check_mode_valid
[20:53:04] [PASSED] drm_test_check_mode_valid_reject
[20:53:04] [PASSED] drm_test_check_mode_valid_reject_rate
[20:53:04] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:53:04] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:53:04] ================= drm_managed (2 subtests) =================
[20:53:04] [PASSED] drm_test_managed_release_action
[20:53:04] [PASSED] drm_test_managed_run_action
[20:53:04] =================== [PASSED] drm_managed ===================
[20:53:04] =================== drm_mm (6 subtests) ====================
[20:53:04] [PASSED] drm_test_mm_init
[20:53:04] [PASSED] drm_test_mm_debug
[20:53:04] [PASSED] drm_test_mm_align32
[20:53:04] [PASSED] drm_test_mm_align64
[20:53:04] [PASSED] drm_test_mm_lowest
[20:53:04] [PASSED] drm_test_mm_highest
[20:53:04] ===================== [PASSED] drm_mm ======================
[20:53:04] ============= drm_modes_analog_tv (5 subtests) =============
[20:53:04] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:53:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:53:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:53:04] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:53:04] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:53:04] =============== [PASSED] drm_modes_analog_tv ===============
[20:53:04] ============== drm_plane_helper (2 subtests) ===============
[20:53:04] =============== drm_test_check_plane_state ================
[20:53:04] [PASSED] clipping_simple
[20:53:04] [PASSED] clipping_rotate_reflect
[20:53:04] [PASSED] positioning_simple
[20:53:04] [PASSED] upscaling
[20:53:04] [PASSED] downscaling
[20:53:04] [PASSED] rounding1
[20:53:04] [PASSED] rounding2
[20:53:04] [PASSED] rounding3
[20:53:04] [PASSED] rounding4
[20:53:04] =========== [PASSED] drm_test_check_plane_state ============
[20:53:04] =========== drm_test_check_invalid_plane_state ============
[20:53:04] [PASSED] positioning_invalid
[20:53:04] [PASSED] upscaling_invalid
[20:53:04] [PASSED] downscaling_invalid
[20:53:04] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:53:04] ================ [PASSED] drm_plane_helper =================
[20:53:04] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:53:04] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:53:04] [PASSED] None
[20:53:04] [PASSED] PAL
[20:53:04] [PASSED] NTSC
[20:53:04] [PASSED] Both, NTSC Default
[20:53:04] [PASSED] Both, PAL Default
[20:53:04] [PASSED] Both, NTSC Default, with PAL on command-line
[20:53:04] [PASSED] Both, PAL Default, with NTSC on command-line
[20:53:04] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:53:04] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:53:04] ================== drm_rect (9 subtests) ===================
[20:53:04] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:53:04] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:53:04] [PASSED] drm_test_rect_clip_scaled_clipped
[20:53:04] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:53:04] ================= drm_test_rect_intersect =================
[20:53:04] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:53:04] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:53:04] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:53:04] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:53:04] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:53:04] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:53:04] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:53:04] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:53:04] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:53:04] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:53:04] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:53:04] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:53:04] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:53:04] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:53:04] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:53:04] ============= [PASSED] drm_test_rect_intersect =============
[20:53:04] ================ drm_test_rect_calc_hscale ================
[20:53:04] [PASSED] normal use
[20:53:04] [PASSED] out of max range
[20:53:04] [PASSED] out of min range
[20:53:04] [PASSED] zero dst
[20:53:04] [PASSED] negative src
[20:53:04] [PASSED] negative dst
[20:53:04] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:53:04] ================ drm_test_rect_calc_vscale ================
[20:53:04] [PASSED] normal use
[20:53:04] [PASSED] out of max range
[20:53:04] [PASSED] out of min range
[20:53:04] [PASSED] zero dst
[20:53:04] [PASSED] negative src
[20:53:04] [PASSED] negative dst
[20:53:04] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:53:04] ================== drm_test_rect_rotate ===================
[20:53:04] [PASSED] reflect-x
[20:53:04] [PASSED] reflect-y
[20:53:04] [PASSED] rotate-0
[20:53:04] [PASSED] rotate-90
[20:53:04] [PASSED] rotate-180
[20:53:04] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[20:53:04] ============== [PASSED] drm_test_rect_rotate ===============
[20:53:04] ================ drm_test_rect_rotate_inv =================
[20:53:04] [PASSED] reflect-x
[20:53:04] [PASSED] reflect-y
[20:53:04] [PASSED] rotate-0
[20:53:04] [PASSED] rotate-90
[20:53:04] [PASSED] rotate-180
[20:53:04] [PASSED] rotate-270
[20:53:04] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:53:04] ==================== [PASSED] drm_rect =====================
[20:53:04] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:53:04] ============ drm_test_sysfb_build_fourcc_list =============
[20:53:04] [PASSED] no native formats
[20:53:04] [PASSED] XRGB8888 as native format
[20:53:04] [PASSED] remove duplicates
[20:53:04] [PASSED] convert alpha formats
[20:53:04] [PASSED] random formats
[20:53:04] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:53:04] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:53:04] ============================================================
[20:53:04] Testing complete. Ran 616 tests: passed: 616
[20:53:04] Elapsed time: 23.274s total, 1.631s configuring, 21.473s building, 0.147s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:53:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:53:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:53:13] Starting KUnit Kernel (1/1)...
[20:53:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:53:13] ================= ttm_device (5 subtests) ==================
[20:53:13] [PASSED] ttm_device_init_basic
[20:53:13] [PASSED] ttm_device_init_multiple
[20:53:13] [PASSED] ttm_device_fini_basic
[20:53:13] [PASSED] ttm_device_init_no_vma_man
[20:53:13] ================== ttm_device_init_pools ==================
[20:53:13] [PASSED] No DMA allocations, no DMA32 required
[20:53:13] [PASSED] DMA allocations, DMA32 required
[20:53:13] [PASSED] No DMA allocations, DMA32 required
[20:53:13] [PASSED] DMA allocations, no DMA32 required
[20:53:13] ============== [PASSED] ttm_device_init_pools ==============
[20:53:13] =================== [PASSED] ttm_device ====================
[20:53:13] ================== ttm_pool (8 subtests) ===================
[20:53:13] ================== ttm_pool_alloc_basic ===================
[20:53:13] [PASSED] One page
[20:53:13] [PASSED] More than one page
[20:53:13] [PASSED] Above the allocation limit
[20:53:13] [PASSED] One page, with coherent DMA mappings enabled
[20:53:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:53:13] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:53:13] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:53:13] [PASSED] One page
[20:53:13] [PASSED] More than one page
[20:53:13] [PASSED] Above the allocation limit
[20:53:13] [PASSED] One page, with coherent DMA mappings enabled
[20:53:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:53:13] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:53:13] [PASSED] ttm_pool_alloc_order_caching_match
[20:53:13] [PASSED] ttm_pool_alloc_caching_mismatch
[20:53:13] [PASSED] ttm_pool_alloc_order_mismatch
[20:53:13] [PASSED] ttm_pool_free_dma_alloc
[20:53:13] [PASSED] ttm_pool_free_no_dma_alloc
[20:53:13] [PASSED] ttm_pool_fini_basic
[20:53:13] ==================== [PASSED] ttm_pool =====================
[20:53:13] ================ ttm_resource (8 subtests) =================
[20:53:13] ================= ttm_resource_init_basic =================
[20:53:13] [PASSED] Init resource in TTM_PL_SYSTEM
[20:53:13] [PASSED] Init resource in TTM_PL_VRAM
[20:53:13] [PASSED] Init resource in a private placement
[20:53:13] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:53:13] ============= [PASSED] ttm_resource_init_basic =============
[20:53:13] [PASSED] ttm_resource_init_pinned
[20:53:13] [PASSED] ttm_resource_fini_basic
[20:53:13] [PASSED] ttm_resource_manager_init_basic
[20:53:13] [PASSED] ttm_resource_manager_usage_basic
[20:53:13] [PASSED] ttm_resource_manager_set_used_basic
[20:53:13] [PASSED] ttm_sys_man_alloc_basic
[20:53:13] [PASSED] ttm_sys_man_free_basic
[20:53:13] ================== [PASSED] ttm_resource ===================
[20:53:13] =================== ttm_tt (15 subtests) ===================
[20:53:13] ==================== ttm_tt_init_basic ====================
[20:53:13] [PASSED] Page-aligned size
[20:53:13] [PASSED] Extra pages requested
[20:53:13] ================ [PASSED] ttm_tt_init_basic ================
[20:53:13] [PASSED] ttm_tt_init_misaligned
[20:53:13] [PASSED] ttm_tt_fini_basic
[20:53:13] [PASSED] ttm_tt_fini_sg
[20:53:13] [PASSED] ttm_tt_fini_shmem
[20:53:13] [PASSED] ttm_tt_create_basic
[20:53:13] [PASSED] ttm_tt_create_invalid_bo_type
[20:53:13] [PASSED] ttm_tt_create_ttm_exists
[20:53:13] [PASSED] ttm_tt_create_failed
[20:53:13] [PASSED] ttm_tt_destroy_basic
[20:53:13] [PASSED] ttm_tt_populate_null_ttm
[20:53:13] [PASSED] ttm_tt_populate_populated_ttm
[20:53:13] [PASSED] ttm_tt_unpopulate_basic
[20:53:13] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:53:13] [PASSED] ttm_tt_swapin_basic
[20:53:13] ===================== [PASSED] ttm_tt ======================
[20:53:13] =================== ttm_bo (14 subtests) ===================
[20:53:13] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:53:13] [PASSED] Cannot be interrupted and sleeps
[20:53:13] [PASSED] Cannot be interrupted, locks straight away
[20:53:13] [PASSED] Can be interrupted, sleeps
[20:53:13] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:53:13] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:53:13] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:53:13] [PASSED] ttm_bo_reserve_double_resv
[20:53:13] [PASSED] ttm_bo_reserve_interrupted
[20:53:13] [PASSED] ttm_bo_reserve_deadlock
[20:53:13] [PASSED] ttm_bo_unreserve_basic
[20:53:13] [PASSED] ttm_bo_unreserve_pinned
[20:53:13] [PASSED] ttm_bo_unreserve_bulk
[20:53:13] [PASSED] ttm_bo_put_basic
[20:53:13] [PASSED] ttm_bo_put_shared_resv
[20:53:13] [PASSED] ttm_bo_pin_basic
[20:53:13] [PASSED] ttm_bo_pin_unpin_resource
[20:53:13] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:53:13] ===================== [PASSED] ttm_bo ======================
[20:53:13] ============== ttm_bo_validate (21 subtests) ===============
[20:53:13] ============== ttm_bo_init_reserved_sys_man ===============
[20:53:13] [PASSED] Buffer object for userspace
[20:53:13] [PASSED] Kernel buffer object
[20:53:13] [PASSED] Shared buffer object
[20:53:13] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:53:13] ============== ttm_bo_init_reserved_mock_man ==============
[20:53:13] [PASSED] Buffer object for userspace
[20:53:13] [PASSED] Kernel buffer object
[20:53:13] [PASSED] Shared buffer object
[20:53:13] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:53:13] [PASSED] ttm_bo_init_reserved_resv
[20:53:13] ================== ttm_bo_validate_basic ==================
[20:53:13] [PASSED] Buffer object for userspace
[20:53:13] [PASSED] Kernel buffer object
[20:53:13] [PASSED] Shared buffer object
[20:53:13] ============== [PASSED] ttm_bo_validate_basic ==============
[20:53:13] [PASSED] ttm_bo_validate_invalid_placement
[20:53:13] ============= ttm_bo_validate_same_placement ==============
[20:53:13] [PASSED] System manager
[20:53:13] [PASSED] VRAM manager
[20:53:13] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:53:13] [PASSED] ttm_bo_validate_failed_alloc
[20:53:13] [PASSED] ttm_bo_validate_pinned
[20:53:13] [PASSED] ttm_bo_validate_busy_placement
[20:53:13] ================ ttm_bo_validate_multihop =================
[20:53:13] [PASSED] Buffer object for userspace
[20:53:13] [PASSED] Kernel buffer object
[20:53:13] [PASSED] Shared buffer object
[20:53:13] ============ [PASSED] ttm_bo_validate_multihop =============
[20:53:13] ========== ttm_bo_validate_no_placement_signaled ==========
[20:53:13] [PASSED] Buffer object in system domain, no page vector
[20:53:13] [PASSED] Buffer object in system domain with an existing page vector
[20:53:13] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:53:13] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:53:13] [PASSED] Buffer object for userspace
[20:53:13] [PASSED] Kernel buffer object
[20:53:13] [PASSED] Shared buffer object
[20:53:13] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:53:13] [PASSED] ttm_bo_validate_move_fence_signaled
[20:53:13] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:53:13] [PASSED] Waits for GPU
[20:53:13] [PASSED] Tries to lock straight away
[20:53:13] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:53:13] [PASSED] ttm_bo_validate_happy_evict
[20:53:13] [PASSED] ttm_bo_validate_all_pinned_evict
[20:53:13] [PASSED] ttm_bo_validate_allowed_only_evict
[20:53:13] [PASSED] ttm_bo_validate_deleted_evict
[20:53:13] [PASSED] ttm_bo_validate_busy_domain_evict
[20:53:13] [PASSED] ttm_bo_validate_evict_gutting
[20:53:13] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:53:13] ================= [PASSED] ttm_bo_validate =================
[20:53:13] ============================================================
[20:53:13] Testing complete. Ran 101 tests: passed: 101
[20:53:13] Elapsed time: 9.421s total, 1.611s configuring, 7.594s building, 0.176s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Xe.CI.BAT: success for Add TLB invalidation abstraction (rev2)
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (9 preceding siblings ...)
2025-07-30 20:53 ` ✓ CI.KUnit: success " Patchwork
@ 2025-07-30 21:55 ` Patchwork
2025-07-30 22:59 ` ✗ Xe.CI.Full: failure " Patchwork
11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-07-30 21:55 UTC (permalink / raw)
To: stuartsummers; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1686 bytes --]
== Series Details ==
Series: Add TLB invalidation abstraction (rev2)
URL : https://patchwork.freedesktop.org/series/152022/
State : success
== Summary ==
CI Bug Log - changes from xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796_BAT -> xe-pw-152022v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): bat-adlp-vm
Known issues
------------
Here are the changes found in xe-pw-152022v2_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlp-7: [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* IGT: IGT_8478 -> IGT_8479
* Linux: xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796 -> xe-pw-152022v2
IGT_8478: 3e7c2bd685397f852853878aef4d9c1e4889a28b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8479: 5fea7ca6493415ce108231b0ff29f02d293f9aa6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796: e1805ad9a7175457902ae453ea67b76194e7d796
xe-pw-152022v2: 152022v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/index.html
[-- Attachment #2: Type: text/html, Size: 2265 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Xe.CI.Full: failure for Add TLB invalidation abstraction (rev2)
2025-07-30 20:45 [PATCH 0/8] Add TLB invalidation abstraction stuartsummers
` (10 preceding siblings ...)
2025-07-30 21:55 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-07-30 22:59 ` Patchwork
11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-07-30 22:59 UTC (permalink / raw)
To: stuartsummers; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 121090 bytes --]
== Series Details ==
Series: Add TLB invalidation abstraction (rev2)
URL : https://patchwork.freedesktop.org/series/152022/
State : failure
== Summary ==
CI Bug Log - changes from xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796_FULL -> xe-pw-152022v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152022v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152022v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152022v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg2-set2: [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-432/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@xe_exec_basic@multigpu-once-rebind:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-464/igt@xe_exec_basic@multigpu-once-rebind.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
- shard-lnl: [PASS][4] -> [ABORT][5] +2 other tests abort
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-lnl-2/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-4/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
#### Warnings ####
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-ro-dontunmap-eocheck:
- shard-bmg: [SKIP][6] ([Intel XE#4945]) -> [INCOMPLETE][7]
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-ro-dontunmap-eocheck.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-ro-dontunmap-eocheck.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-lnl: [ABORT][8] ([Intel XE#4757]) -> [INCOMPLETE][9]
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-lnl-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
- shard-adlp: [TIMEOUT][10] ([Intel XE#5531]) -> [INCOMPLETE][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
- shard-bmg: [ABORT][12] ([Intel XE#5530]) -> [INCOMPLETE][13]
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
Known issues
------------
Here are the changes found in xe-pw-152022v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@hotreplug:
- shard-bmg: [PASS][14] -> [SKIP][15] ([Intel XE#4963]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@core_hotunplug@hotreplug.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@core_hotunplug@hotreplug.html
* igt@fbdev@nullptr:
- shard-bmg: [PASS][16] -> [SKIP][17] ([Intel XE#2134]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@fbdev@nullptr.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@fbdev@nullptr.html
* igt@intel_hwmon@hwmon-read:
- shard-bmg: [PASS][18] -> [SKIP][19] ([Intel XE#5177])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-3/igt@intel_hwmon@hwmon-read.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@intel_hwmon@hwmon-read.html
* igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
- shard-adlp: [PASS][20] -> [FAIL][21] ([Intel XE#3884]) +1 other test fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-4/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#316])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#1407])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][24] ([Intel XE#1124]) +5 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- shard-bmg: [PASS][25] -> [SKIP][26] ([Intel XE#4947]) +22 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_big_fb@linear-16bpp-rotate-180.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_big_fb@linear-16bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-adlp: NOTRUN -> [SKIP][27] ([Intel XE#316]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [PASS][28] -> [DMESG-FAIL][29] ([Intel XE#4543]) +9 other tests dmesg-fail
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#1124]) +2 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: NOTRUN -> [DMESG-FAIL][31] ([Intel XE#4543]) +2 other tests dmesg-fail
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#1124]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-adlp: NOTRUN -> [SKIP][33] ([Intel XE#607])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
- shard-dg2-set2: NOTRUN -> [SKIP][34] ([Intel XE#607])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#1477])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-2/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#1124])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#2191])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#2191])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#2191]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-4/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#367]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#455] / [Intel XE#787]) +24 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#2887]) +5 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-4/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#787]) +20 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-4/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2887]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][46] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: [PASS][47] -> [INCOMPLETE][48] ([Intel XE#3862]) +1 other test incomplete
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][49] ([Intel XE#2907])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#2907])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#787]) +118 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][52] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
* igt@kms_cdclk@mode-transition@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#4417]) +3 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-adlp: NOTRUN -> [SKIP][54] ([Intel XE#373]) +6 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-4/igt@kms_chamelium_audio@hdmi-audio-edid.html
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#373]) +6 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-7/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#4950]) +5 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_hpd@dp-hpd-after-hibernate:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2252])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_chamelium_hpd@dp-hpd-after-hibernate.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][58] ([Intel XE#373]) +8 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_content_protection@mei-interface:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#1468])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][60] ([Intel XE#1178]) +2 other tests fail
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@type1:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#2341])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_content_protection@type1.html
- shard-lnl: NOTRUN -> [SKIP][62] ([Intel XE#3278])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-5/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][63] ([Intel XE#1188])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_content_protection@uevent@pipe-a-dp-2.html
- shard-bmg: NOTRUN -> [FAIL][64] ([Intel XE#1188])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-adlp: NOTRUN -> [SKIP][65] ([Intel XE#308])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1424])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [PASS][67] -> [SKIP][68] ([Intel XE#2291]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-adlp: NOTRUN -> [SKIP][69] ([Intel XE#309])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-dg2-set2: [PASS][70] -> [INCOMPLETE][71] ([Intel XE#3226])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-436/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#323])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#323])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-adlp: NOTRUN -> [SKIP][74] ([Intel XE#323])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#1340])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#4494] / [i915#3804])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-434/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][77] -> [SKIP][78] ([Intel XE#4354])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_dp_link_training@non-uhbr-sst.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-adlp: NOTRUN -> [SKIP][79] ([Intel XE#776])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_fbcon_fbt@psr-suspend.html
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#776])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-436/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: [PASS][81] -> [SKIP][82] ([Intel XE#2316])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-lnl: NOTRUN -> [SKIP][83] ([Intel XE#1421]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-8/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-adlp: NOTRUN -> [SKIP][84] ([Intel XE#310]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][85] -> [SKIP][86] ([Intel XE#4950]) +81 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_flip@2x-nonexisting-fb.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2316])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
- shard-adlp: [PASS][88] -> [DMESG-WARN][89] ([Intel XE#4543]) +10 other tests dmesg-warn
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-9/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
* igt@kms_flip@bo-too-big-interruptible@a-edp1:
- shard-lnl: NOTRUN -> [TIMEOUT][90] ([Intel XE#1504]) +1 other test timeout
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_flip@bo-too-big-interruptible@a-edp1.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-dg2-set2: [PASS][91] -> [FAIL][92] ([Intel XE#3098]) +1 other test fail
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-435/igt@kms_flip@dpms-vs-vblank-race.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-464/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][93] -> [FAIL][94] ([Intel XE#301]) +1 other test fail
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend:
- shard-adlp: [PASS][95] -> [DMESG-WARN][96] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-9/igt@kms_flip@flip-vs-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][97] -> [DMESG-WARN][98] ([Intel XE#2953] / [Intel XE#4173]) +9 other tests dmesg-warn
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-8/igt@kms_flip@flip-vs-suspend-interruptible.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-interruptible@b-hdmi-a1:
- shard-adlp: NOTRUN -> [DMESG-WARN][99] ([Intel XE#4543]) +1 other test dmesg-warn
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#2293] / [Intel XE#2380])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#2293]) +5 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][102] ([Intel XE#651]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#651]) +6 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][104] ([Intel XE#651]) +2 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2311]) +2 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][106] ([Intel XE#656]) +12 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-bmg: NOTRUN -> [SKIP][107] ([Intel XE#5390]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][108] ([Intel XE#656]) +7 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary:
- shard-bmg: NOTRUN -> [SKIP][109] ([Intel XE#4947]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][110] ([Intel XE#653]) +3 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
- shard-dg2-set2: NOTRUN -> [SKIP][111] ([Intel XE#653]) +11 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][112] ([Intel XE#2313])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#2352])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#4090])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#2925])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
- shard-lnl: NOTRUN -> [SKIP][116] ([Intel XE#2925])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_plane_multiple@tiling-4:
- shard-adlp: NOTRUN -> [SKIP][117] ([Intel XE#5020])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-1/igt@kms_plane_multiple@tiling-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][118] ([Intel XE#2763]) +3 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a.html
* igt@kms_pm_backlight@basic-brightness:
- shard-dg2-set2: NOTRUN -> [SKIP][119] ([Intel XE#870])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-434/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc5-dpms-negative:
- shard-lnl: NOTRUN -> [SKIP][120] ([Intel XE#1131])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-2/igt@kms_pm_dc@dc5-dpms-negative.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-bmg: NOTRUN -> [SKIP][121] ([Intel XE#4962])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_rpm@drm-resources-equal.html
- shard-adlp: [PASS][122] -> [ABORT][123] ([Intel XE#5545])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-4/igt@kms_pm_rpm@drm-resources-equal.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_pm_rpm@system-suspend-modeset:
- shard-bmg: [PASS][124] -> [SKIP][125] ([Intel XE#4962])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@kms_pm_rpm@system-suspend-modeset.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
- shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#2893])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][127] ([Intel XE#4608])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][128] ([Intel XE#1489]) +3 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-adlp: NOTRUN -> [SKIP][129] ([Intel XE#1489]) +5 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@fbc-pr-dpms:
- shard-lnl: NOTRUN -> [SKIP][131] ([Intel XE#1406]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-7/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@psr-cursor-plane-onoff:
- shard-adlp: NOTRUN -> [SKIP][132] ([Intel XE#2850] / [Intel XE#929]) +4 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_psr@psr-cursor-plane-onoff.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-adlp: NOTRUN -> [SKIP][133] ([Intel XE#1127])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-adlp: NOTRUN -> [SKIP][134] ([Intel XE#3414])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_rotation_crc@primary-rotation-270.html
- shard-dg2-set2: NOTRUN -> [SKIP][135] ([Intel XE#3414]) +1 other test skip
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_rotation_crc@primary-rotation-270.html
- shard-lnl: NOTRUN -> [SKIP][136] ([Intel XE#3414] / [Intel XE#3904])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
- shard-lnl: NOTRUN -> [FAIL][137] ([Intel XE#4689])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2-set2: NOTRUN -> [SKIP][138] ([Intel XE#1127])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-adlp: NOTRUN -> [SKIP][139] ([Intel XE#362])
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-4/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: NOTRUN -> [FAIL][140] ([Intel XE#1729])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern.html
- shard-lnl: NOTRUN -> [SKIP][141] ([Intel XE#362])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-suspend:
- shard-adlp: NOTRUN -> [SKIP][142] ([Intel XE#455]) +6 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-2/igt@kms_vrr@flip-suspend.html
- shard-dg2-set2: NOTRUN -> [SKIP][143] ([Intel XE#455]) +4 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@lobf:
- shard-adlp: NOTRUN -> [SKIP][144] ([Intel XE#2168])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@kms_vrr@lobf.html
- shard-dg2-set2: NOTRUN -> [SKIP][145] ([Intel XE#2168])
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@kms_vrr@lobf.html
- shard-lnl: NOTRUN -> [SKIP][146] ([Intel XE#1499])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@kms_vrr@lobf.html
* igt@xe_compute@ccs-mode-compute-kernel:
- shard-adlp: NOTRUN -> [SKIP][147] ([Intel XE#1447] / [Intel XE#5596])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@xe_compute@ccs-mode-compute-kernel.html
* igt@xe_configfs@survivability-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][148] ([Intel XE#5249])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@xe_configfs@survivability-mode.html
- shard-lnl: NOTRUN -> [SKIP][149] ([Intel XE#5249])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@xe_configfs@survivability-mode.html
- shard-adlp: NOTRUN -> [SKIP][150] ([Intel XE#5249])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@xe_configfs@survivability-mode.html
* igt@xe_copy_basic@mem-copy-linear-0x369:
- shard-adlp: NOTRUN -> [SKIP][151] ([Intel XE#1123])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@xe_copy_basic@mem-copy-linear-0x369.html
* igt@xe_eudebug@vma-ufence-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][152] ([Intel XE#4837]) +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-434/igt@xe_eudebug@vma-ufence-faultable.html
- shard-lnl: NOTRUN -> [SKIP][153] ([Intel XE#4837]) +2 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-5/igt@xe_eudebug@vma-ufence-faultable.html
* igt@xe_eudebug_online@interrupt-other:
- shard-adlp: NOTRUN -> [SKIP][154] ([Intel XE#4837] / [Intel XE#5565]) +4 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-6/igt@xe_eudebug_online@interrupt-other.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-adlp: NOTRUN -> [SKIP][155] ([Intel XE#4519])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-small-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][156] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-1/igt@xe_evict@evict-small-multi-vm.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][157] ([Intel XE#2322])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
- shard-adlp: NOTRUN -> [SKIP][158] ([Intel XE#1392] / [Intel XE#5575]) +1 other test skip
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-dg2-set2: [PASS][159] -> [SKIP][160] ([Intel XE#1392]) +4 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-464/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][161] ([Intel XE#1392]) +1 other test skip
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue:
- shard-dg2-set2: NOTRUN -> [SKIP][162] ([Intel XE#288]) +11 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue.html
* igt@xe_exec_fault_mode@many-userptr-invalidate-race-prefetch:
- shard-adlp: NOTRUN -> [SKIP][163] ([Intel XE#288] / [Intel XE#5561]) +9 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-6/igt@xe_exec_fault_mode@many-userptr-invalidate-race-prefetch.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-bmg: [PASS][164] -> [INCOMPLETE][165] ([Intel XE#2594])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-bmg: NOTRUN -> [SKIP][166] ([Intel XE#4837]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset:
- shard-bmg: [PASS][167] -> [SKIP][168] ([Intel XE#4945]) +474 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html
* igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset:
- shard-adlp: NOTRUN -> [SKIP][169] ([Intel XE#4915] / [Intel XE#5560]) +81 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset.html
* igt@xe_exec_system_allocator@process-many-mmap-free-race-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][170] ([Intel XE#4915]) +88 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-433/igt@xe_exec_system_allocator@process-many-mmap-free-race-nomemset.html
* igt@xe_exec_system_allocator@process-many-stride-mmap-huge:
- shard-lnl: NOTRUN -> [SKIP][171] ([Intel XE#4943]) +4 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-2/igt@xe_exec_system_allocator@process-many-stride-mmap-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race:
- shard-bmg: NOTRUN -> [SKIP][172] ([Intel XE#4945]) +9 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][173] ([Intel XE#5531])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_oa@non-privileged-map-oa-buffer:
- shard-dg2-set2: NOTRUN -> [SKIP][174] ([Intel XE#3573]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@xe_oa@non-privileged-map-oa-buffer.html
* igt@xe_oa@privileged-forked-access-vaddr:
- shard-adlp: NOTRUN -> [SKIP][175] ([Intel XE#3573]) +3 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-9/igt@xe_oa@privileged-forked-access-vaddr.html
* igt@xe_pat@pat-index-xehpc:
- shard-dg2-set2: NOTRUN -> [SKIP][176] ([Intel XE#2838] / [Intel XE#979])
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
- shard-adlp: NOTRUN -> [SKIP][177] ([Intel XE#4733] / [Intel XE#5594]) +2 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
- shard-dg2-set2: NOTRUN -> [SKIP][178] ([Intel XE#4733]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
* igt@xe_query@multigpu-query-engines:
- shard-dg2-set2: NOTRUN -> [SKIP][179] ([Intel XE#944]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-466/igt@xe_query@multigpu-query-engines.html
* igt@xe_query@multigpu-query-gt-list:
- shard-adlp: NOTRUN -> [SKIP][180] ([Intel XE#944])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@xe_query@multigpu-query-gt-list.html
- shard-lnl: NOTRUN -> [SKIP][181] ([Intel XE#944])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-3/igt@xe_query@multigpu-query-gt-list.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-bmg: [SKIP][182] ([Intel XE#4963]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@core_hotunplug@unbind-rebind.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@core_hotunplug@unbind-rebind.html
* igt@fbdev@pan:
- shard-bmg: [SKIP][184] ([Intel XE#2134]) -> [PASS][185] +1 other test pass
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@fbdev@pan.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@fbdev@pan.html
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [SKIP][186] -> [PASS][187] +1 other test pass
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@intel_hwmon@hwmon-write.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@legacy-format:
- shard-adlp: [DMESG-WARN][188] -> [PASS][189] +1 other test pass
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-4/igt@kms_addfb_basic@legacy-format.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_addfb_basic@legacy-format.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-bmg: [SKIP][190] ([Intel XE#4947]) -> [PASS][191] +17 other tests pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-adlp: [DMESG-FAIL][192] ([Intel XE#4543]) -> [PASS][193] +9 other tests pass
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][194] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][196] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: [SKIP][198] ([Intel XE#2291]) -> [PASS][199] +3 other tests pass
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][200] ([Intel XE#4633]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [SKIP][202] ([Intel XE#4302]) -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-bmg: [SKIP][204] ([Intel XE#2316]) -> [PASS][205] +2 other tests pass
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-adlp: [DMESG-WARN][206] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][207]
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][208] ([Intel XE#4543]) -> [PASS][209] +16 other tests pass
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-3/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: [INCOMPLETE][210] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_hdr@static-toggle-dpms:
- shard-bmg: [SKIP][212] ([Intel XE#1503]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_hdr@static-toggle-dpms.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [SKIP][214] ([Intel XE#3012]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers:
- shard-bmg: [SKIP][216] ([Intel XE#4950]) -> [PASS][217] +73 other tests pass
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
* igt@kms_pm_dc@dc6-dpms:
- shard-adlp: [FAIL][218] ([Intel XE#718]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-1/igt@kms_pm_dc@dc6-dpms.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: [FAIL][220] ([Intel XE#718]) -> [PASS][221] +2 other tests pass
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-1/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-bmg: [SKIP][222] ([Intel XE#4962]) -> [PASS][223] +1 other test pass
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [SKIP][224] ([Intel XE#1499]) -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_vrr@negative-basic.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_vrr@negative-basic.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue:
- shard-dg2-set2: [SKIP][226] ([Intel XE#1392]) -> [PASS][227] +3 other tests pass
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-463/igt@xe_exec_basic@multigpu-once-bindexecqueue.html
* igt@xe_exec_system_allocator@process-many-new-nomemset:
- shard-bmg: [SKIP][228] ([Intel XE#4945]) -> [PASS][229] +402 other tests pass
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_exec_system_allocator@process-many-new-nomemset.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@xe_exec_system_allocator@process-many-new-nomemset.html
* igt@xe_live_ktest@xe_bo:
- shard-bmg: [SKIP][230] ([Intel XE#2229]) -> [PASS][231] +1 other test pass
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_live_ktest@xe_bo.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@xe_live_ktest@xe_bo.html
* igt@xe_module_load@reload-no-display:
- shard-bmg: [FAIL][232] ([Intel XE#5679]) -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_module_load@reload-no-display.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@xe_module_load@reload-no-display.html
* igt@xe_pm@s2idle-basic-exec:
- shard-adlp: [DMESG-WARN][234] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][235] +8 other tests pass
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-9/igt@xe_pm@s2idle-basic-exec.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-8/igt@xe_pm@s2idle-basic-exec.html
* igt@xe_pm@s3-d3hot-basic-exec:
- shard-adlp: [ABORT][236] ([Intel XE#5545]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-adlp-2/igt@xe_pm@s3-d3hot-basic-exec.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-adlp-1/igt@xe_pm@s3-d3hot-basic-exec.html
#### Warnings ####
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-bmg: [SKIP][238] ([Intel XE#4950]) -> [SKIP][239] ([Intel XE#2370]) +1 other test skip
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-bmg: [SKIP][240] ([Intel XE#4947]) -> [SKIP][241] ([Intel XE#2327]) +4 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_big_fb@linear-32bpp-rotate-90.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-bmg: [SKIP][242] ([Intel XE#2327]) -> [SKIP][243] ([Intel XE#4947]) +2 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-bmg: [SKIP][244] ([Intel XE#4947]) -> [SKIP][245] ([Intel XE#1124]) +6 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: [SKIP][246] ([Intel XE#4947]) -> [SKIP][247] ([Intel XE#607])
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: [SKIP][248] ([Intel XE#1124]) -> [SKIP][249] ([Intel XE#4947]) +9 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: [SKIP][250] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][251] ([Intel XE#4950])
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: [SKIP][252] ([Intel XE#4950]) -> [SKIP][253] ([Intel XE#2314] / [Intel XE#2894])
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-bmg: [SKIP][254] ([Intel XE#4950]) -> [SKIP][255] ([Intel XE#367]) +2 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-3840x2160p:
- shard-bmg: [SKIP][256] ([Intel XE#367]) -> [SKIP][257] ([Intel XE#4950]) +3 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: [SKIP][258] ([Intel XE#4947]) -> [SKIP][259] ([Intel XE#2887]) +15 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][260] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][261] ([Intel XE#4947]) +1 other test skip
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][262] ([Intel XE#4947]) -> [SKIP][263] ([Intel XE#2652] / [Intel XE#787])
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: [SKIP][264] ([Intel XE#4947]) -> [SKIP][265] ([Intel XE#3432]) +1 other test skip
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-bmg: [SKIP][266] ([Intel XE#3432]) -> [SKIP][267] ([Intel XE#4947])
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: [SKIP][268] ([Intel XE#2887]) -> [SKIP][269] ([Intel XE#4947]) +16 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][270] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][271] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-bmg: [SKIP][272] ([Intel XE#2724]) -> [SKIP][273] ([Intel XE#4947])
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_cdclk@mode-transition.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: [SKIP][274] ([Intel XE#4950]) -> [SKIP][275] ([Intel XE#2252]) +9 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-resolution-list.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-bmg: [SKIP][276] ([Intel XE#2252]) -> [SKIP][277] ([Intel XE#4950]) +8 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_chamelium_frames@vga-frame-dump.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: [SKIP][278] ([Intel XE#4950]) -> [SKIP][279] ([Intel XE#2390])
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_content_protection@dp-mst-type-1.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [FAIL][280] ([Intel XE#1178]) -> [SKIP][281] ([Intel XE#4950])
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_content_protection@lic-type-0.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-bmg: [SKIP][282] ([Intel XE#4950]) -> [SKIP][283] ([Intel XE#2341])
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_content_protection@mei-interface.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][284] ([Intel XE#2341]) -> [FAIL][285] ([Intel XE#1188])
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_content_protection@uevent.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-bmg: [SKIP][286] ([Intel XE#4950]) -> [SKIP][287] ([Intel XE#2320]) +2 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_cursor_crc@cursor-onscreen-32x32.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-bmg: [SKIP][288] ([Intel XE#4950]) -> [SKIP][289] ([Intel XE#2321])
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-bmg: [SKIP][290] ([Intel XE#2320]) -> [SKIP][291] ([Intel XE#4950]) +7 other tests skip
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_cursor_crc@cursor-random-32x32.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-bmg: [SKIP][292] ([Intel XE#2321]) -> [SKIP][293] ([Intel XE#4950])
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-512x512.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-bmg: [SKIP][294] ([Intel XE#4950]) -> [SKIP][295] ([Intel XE#2286])
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
- shard-bmg: [SKIP][296] ([Intel XE#4947]) -> [SKIP][297] ([Intel XE#5428])
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-bmg: [SKIP][298] ([Intel XE#1508]) -> [SKIP][299] ([Intel XE#4947])
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-bmg: [SKIP][300] ([Intel XE#4950]) -> [SKIP][301] ([Intel XE#1340])
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-bmg: [SKIP][302] ([Intel XE#2244]) -> [SKIP][303] ([Intel XE#4947]) +2 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-bmg: [SKIP][304] ([Intel XE#4947]) -> [SKIP][305] ([Intel XE#2244])
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-bmg: [SKIP][306] ([Intel XE#4422]) -> [SKIP][307] ([Intel XE#4945])
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-bmg: [SKIP][308] ([Intel XE#4947]) -> [SKIP][309] ([Intel XE#5425]) +1 other test skip
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_fbcon_fbt@fbc-suspend.html
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-bmg: [SKIP][310] ([Intel XE#4947]) -> [SKIP][311] ([Intel XE#776])
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_fbcon_fbt@psr-suspend.html
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@dp-mst:
- shard-bmg: [SKIP][312] ([Intel XE#4950]) -> [SKIP][313] ([Intel XE#2375])
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_feature_discovery@dp-mst.html
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-bmg: [SKIP][314] ([Intel XE#2374]) -> [SKIP][315] ([Intel XE#4950])
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_feature_discovery@psr2.html
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [SKIP][316] ([Intel XE#4950]) -> [SKIP][317] ([Intel XE#2316]) +2 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [SKIP][318] ([Intel XE#2316]) -> [SKIP][319] ([Intel XE#4950]) +1 other test skip
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
- shard-bmg: [SKIP][320] ([Intel XE#4947]) -> [SKIP][321] ([Intel XE#2293] / [Intel XE#2380]) +4 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-bmg: [SKIP][322] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][323] ([Intel XE#4947]) +5 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][324] ([Intel XE#2312]) -> [SKIP][325] ([Intel XE#4947]) +4 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][326] ([Intel XE#2311]) -> [SKIP][327] ([Intel XE#2312]) +4 other tests skip
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][328] ([Intel XE#4947]) -> [SKIP][329] ([Intel XE#2311]) +23 other tests skip
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: [SKIP][330] ([Intel XE#2312]) -> [SKIP][331] ([Intel XE#2311]) +5 other tests skip
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move:
- shard-bmg: [SKIP][332] ([Intel XE#4947]) -> [SKIP][333] ([Intel XE#2312]) +4 other tests skip
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
- shard-bmg: [SKIP][334] ([Intel XE#2311]) -> [SKIP][335] ([Intel XE#4947]) +30 other tests skip
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][336] ([Intel XE#5390]) -> [SKIP][337] ([Intel XE#4947]) +16 other tests skip
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][338] ([Intel XE#2312]) -> [SKIP][339] ([Intel XE#5390]) +3 other tests skip
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][340] ([Intel XE#4947]) -> [SKIP][341] ([Intel XE#5390]) +11 other tests skip
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][342] ([Intel XE#5390]) -> [SKIP][343] ([Intel XE#2312]) +4 other tests skip
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-bmg: [SKIP][344] ([Intel XE#4947]) -> [SKIP][345] ([Intel XE#2352])
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][346] ([Intel XE#4947]) -> [SKIP][347] ([Intel XE#2313]) +26 other tests skip
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
- shard-bmg: [SKIP][348] ([Intel XE#2313]) -> [SKIP][349] ([Intel XE#2312]) +7 other tests skip
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
[349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][350] ([Intel XE#2312]) -> [SKIP][351] ([Intel XE#2313]) +4 other tests skip
[350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][352] ([Intel XE#2313]) -> [SKIP][353] ([Intel XE#4947]) +32 other tests skip
[352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][354] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][355] ([Intel XE#4950])
[354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
[355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [SKIP][356] ([Intel XE#1503]) -> [SKIP][357] ([Intel XE#4950])
[356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_hdr@static-toggle.html
[357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-bmg: [SKIP][358] ([Intel XE#4947]) -> [SKIP][359] ([Intel XE#2934])
[358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_joiner@basic-force-ultra-joiner.html
[359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: [SKIP][360] ([Intel XE#4947]) -> [SKIP][361] ([Intel XE#2927])
[360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: [SKIP][362] ([Intel XE#4950]) -> [SKIP][363] ([Intel XE#2501])
[362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: [SKIP][364] ([Intel XE#4950]) -> [SKIP][365] ([Intel XE#5021])
[364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
[365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-bmg: [SKIP][366] ([Intel XE#5021]) -> [SKIP][367] ([Intel XE#4596])
[366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-yf.html
[367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_plane_multiple@tiling-y:
- shard-bmg: [SKIP][368] ([Intel XE#5020]) -> [SKIP][369] ([Intel XE#4950])
[368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_plane_multiple@tiling-y.html
[369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
- shard-bmg: [SKIP][370] ([Intel XE#2763]) -> [SKIP][371] ([Intel XE#4950]) +1 other test skip
[370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
[371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
- shard-bmg: [SKIP][372] ([Intel XE#4950]) -> [SKIP][373] ([Intel XE#2763])
[372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
[373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: [SKIP][374] ([Intel XE#4947]) -> [SKIP][375] ([Intel XE#2938])
[374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_pm_backlight@brightness-with-dpms.html
[375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade:
- shard-bmg: [SKIP][376] ([Intel XE#4947]) -> [SKIP][377] ([Intel XE#870])
[376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_pm_backlight@fade.html
[377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_pm_backlight@fade.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-bmg: [SKIP][378] ([Intel XE#870]) -> [SKIP][379] ([Intel XE#4947])
[378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_pm_backlight@fade-with-dpms.html
[379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: [SKIP][380] ([Intel XE#2392]) -> [SKIP][381] ([Intel XE#4947])
[380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_pm_dc@dc6-psr.html
[381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@deep-pkgc:
- shard-bmg: [SKIP][382] ([Intel XE#2505]) -> [SKIP][383] ([Intel XE#4947])
[382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@kms_pm_dc@deep-pkgc.html
[383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-bmg: [SKIP][384] ([Intel XE#4947]) -> [SKIP][385] ([Intel XE#2499])
[384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_pm_lpsp@kms-lpsp.html
[385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: [SKIP][386] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) -> [SKIP][387] ([Intel XE#4962])
[386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_pm_rpm@modeset-lpsp.html
[387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: [SKIP][388] ([Intel XE#1489]) -> [SKIP][389] ([Intel XE#4947]) +7 other tests skip
[388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-bmg: [SKIP][390] ([Intel XE#4947]) -> [SKIP][391] ([Intel XE#1489]) +5 other tests skip
[390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
[391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-bmg: [SKIP][392] ([Intel XE#2387]) -> [SKIP][393] ([Intel XE#4947]) +2 other tests skip
[392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@kms_psr2_su@page_flip-p010.html
[393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@pr-suspend:
- shard-bmg: [SKIP][394] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][395] ([Intel XE#4947]) +14 other tests skip
[394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_psr@pr-suspend.html
[395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_psr@pr-suspend.html
* igt@kms_psr@psr-primary-page-flip:
- shard-bmg: [SKIP][396] ([Intel XE#4947]) -> [SKIP][397] ([Intel XE#2234] / [Intel XE#2850]) +12 other tests skip
[396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_psr@psr-primary-page-flip.html
[397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-3/igt@kms_psr@psr-primary-page-flip.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-bmg: [SKIP][398] ([Intel XE#2414]) -> [SKIP][399] ([Intel XE#4947])
[398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: [SKIP][400] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][401] ([Intel XE#4950]) +2 other tests skip
[400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@kms_rotation_crc@bad-pixel-format.html
[401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: [SKIP][402] ([Intel XE#4950]) -> [SKIP][403] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_rotation_crc@primary-rotation-90.html
[403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-bmg: [SKIP][404] ([Intel XE#4950]) -> [SKIP][405] ([Intel XE#2330])
[404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
[405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][406] ([Intel XE#4950]) -> [SKIP][407] ([Intel XE#2509])
[406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-suspend:
- shard-bmg: [SKIP][408] ([Intel XE#4950]) -> [SKIP][409] ([Intel XE#1499])
[408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_vrr@flip-suspend.html
[409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@lobf:
- shard-bmg: [SKIP][410] ([Intel XE#4950]) -> [SKIP][411] ([Intel XE#2168])
[410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@kms_vrr@lobf.html
[411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@kms_vrr@lobf.html
* igt@kms_vrr@max-min:
- shard-bmg: [SKIP][412] ([Intel XE#1499]) -> [SKIP][413] ([Intel XE#4950]) +2 other tests skip
[412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-6/igt@kms_vrr@max-min.html
[413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@kms_vrr@max-min.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-bmg: [SKIP][414] ([Intel XE#4950]) -> [SKIP][415] ([Intel XE#1091] / [Intel XE#2849]) +1 other test skip
[414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@sriov_basic@enable-vfs-autoprobe-off.html
[415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-8/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@xe_eudebug_online@breakpoint-many-sessions-tiles:
- shard-bmg: [SKIP][416] ([Intel XE#4837]) -> [SKIP][417] ([Intel XE#4945]) +15 other tests skip
[416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
[417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: [SKIP][418] ([Intel XE#4945]) -> [SKIP][419] ([Intel XE#4837]) +14 other tests skip
[418]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_eudebug_online@stopped-thread.html
[419]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-bmg: [SKIP][420] ([Intel XE#4945]) -> [SKIP][421] ([Intel XE#4518])
[420]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_eudebug_sriov@deny-sriov.html
[421]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
- shard-bmg: [SKIP][422] ([Intel XE#2322]) -> [SKIP][423] ([Intel XE#4945]) +9 other tests skip
[422]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
[423]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
* igt@xe_exec_basic@multigpu-no-exec-rebind:
- shard-bmg: [SKIP][424] ([Intel XE#4945]) -> [SKIP][425] ([Intel XE#2322]) +8 other tests skip
[424]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-rebind.html
[425]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-rebind.html
* igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset:
- shard-bmg: [SKIP][426] ([Intel XE#4943]) -> [SKIP][427] ([Intel XE#4945]) +23 other tests skip
[426]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-4/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html
[427]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge:
- shard-bmg: [SKIP][428] ([Intel XE#4945]) -> [SKIP][429] ([Intel XE#4943]) +23 other tests skip
[428]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge.html
[429]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-lnl: [ABORT][430] ([Intel XE#5466]) -> [ABORT][431] ([Intel XE#4917] / [Intel XE#5466])
[430]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-lnl-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[431]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-lnl-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
- shard-bmg: [SKIP][432] ([Intel XE#4945]) -> [INCOMPLETE][433] ([Intel XE#5466])
[432]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[433]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_oa@oa-tlb-invalidate:
- shard-bmg: [SKIP][434] ([Intel XE#4945]) -> [SKIP][435] ([Intel XE#2248])
[434]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_oa@oa-tlb-invalidate.html
[435]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@xe_oa@oa-tlb-invalidate.html
* igt@xe_pat@pat-index-xehpc:
- shard-bmg: [SKIP][436] ([Intel XE#4945]) -> [SKIP][437] ([Intel XE#1420])
[436]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_pat@pat-index-xehpc.html
[437]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-basic-exec:
- shard-bmg: [SKIP][438] ([Intel XE#2284]) -> [SKIP][439] ([Intel XE#4945])
[438]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@xe_pm@d3cold-basic-exec.html
[439]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_pm@d3cold-basic-exec.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-bmg: [SKIP][440] ([Intel XE#4945]) -> [SKIP][441] ([Intel XE#2284]) +1 other test skip
[440]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_pm@s3-d3cold-basic-exec.html
[441]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pmu@fn-engine-activity-load:
- shard-bmg: [SKIP][442] ([Intel XE#4650]) -> [SKIP][443] ([Intel XE#4945])
[442]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-7/igt@xe_pmu@fn-engine-activity-load.html
[443]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_pmu@fn-engine-activity-load.html
* igt@xe_pxp@display-pxp-fb:
- shard-bmg: [SKIP][444] ([Intel XE#4945]) -> [SKIP][445] ([Intel XE#4733]) +2 other tests skip
[444]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_pxp@display-pxp-fb.html
[445]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-6/igt@xe_pxp@display-pxp-fb.html
* igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
- shard-bmg: [SKIP][446] ([Intel XE#4733]) -> [SKIP][447] ([Intel XE#4945]) +2 other tests skip
[446]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html
[447]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-cs-cycles:
- shard-bmg: [SKIP][448] ([Intel XE#4945]) -> [SKIP][449] ([Intel XE#944]) +1 other test skip
[448]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_query@multigpu-query-cs-cycles.html
[449]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-7/igt@xe_query@multigpu-query-cs-cycles.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-bmg: [SKIP][450] ([Intel XE#944]) -> [SKIP][451] ([Intel XE#4945]) +1 other test skip
[450]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-3/igt@xe_query@multigpu-query-mem-usage.html
[451]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-bmg: [SKIP][452] ([Intel XE#4945]) -> [SKIP][453] ([Intel XE#4130])
[452]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
[453]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-4/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
* igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs:
- shard-bmg: [SKIP][454] ([Intel XE#4130]) -> [SKIP][455] ([Intel XE#4945]) +1 other test skip
[454]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-2/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html
[455]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html
* igt@xe_sriov_flr@flr-twice:
- shard-bmg: [SKIP][456] ([Intel XE#4273]) -> [SKIP][457] ([Intel XE#4945])
[456]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-8/igt@xe_sriov_flr@flr-twice.html
[457]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_sriov_flr@flr-twice.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-bmg: [SKIP][458] ([Intel XE#4351]) -> [SKIP][459] ([Intel XE#4945])
[458]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-1/igt@xe_sriov_scheduling@equal-throughput.html
[459]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-5/igt@xe_sriov_scheduling@equal-throughput.html
* igt@xe_sriov_scheduling@nonpreempt-engine-resets:
- shard-bmg: [SKIP][460] ([Intel XE#4945]) -> [SKIP][461] ([Intel XE#4351])
[460]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796/shard-bmg-5/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
[461]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/shard-bmg-2/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
[Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
[Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
[Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
[Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
[Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
[Intel XE#4519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4519
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
[Intel XE#4689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4689
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4757]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4757
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
[Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
[Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
[Intel XE#4962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4962
[Intel XE#4963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4963
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5249
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5425
[Intel XE#5428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5428
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5531]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5531
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5560
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5596
[Intel XE#5679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5679
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
Build changes
-------------
* IGT: IGT_8478 -> IGT_8479
* Linux: xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796 -> xe-pw-152022v2
IGT_8478: 3e7c2bd685397f852853878aef4d9c1e4889a28b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8479: 5fea7ca6493415ce108231b0ff29f02d293f9aa6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3489-e1805ad9a7175457902ae453ea67b76194e7d796: e1805ad9a7175457902ae453ea67b76194e7d796
xe-pw-152022v2: 152022v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152022v2/index.html
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