Re: [PATCH V2 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Matthew Auld <matthew.auld@intel.com>]

On 19/02/2026 11:37, Tejas Upadhyay wrote:
> When set, the L2 flush optimization feature will control
> whether L2 is in Persistent or Transient mode through
> monitoring of media activity.
> 
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
> 
> Also, restrict userptr, svm and dmabuf mappings to be
> either 2WAY or XA+1WAY
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_guc.c        | 3 +++
>   drivers/gpu/drm/xe/xe_guc_fwif.h   | 1 +
>   drivers/gpu/drm/xe/xe_vm.c         | 7 +++++++
>   drivers/gpu/drm/xe/xe_vm_madvise.c | 4 ++++
>   4 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index cbbb4d665b8f..97c33c3dd520 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>   	if (xe_guc_using_main_gamctrl_queues(guc))
>   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>   
> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> +
>   	return flags;
>   }
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index a33ea288b907..39ff7b3e960b 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>   
>   #define GUC_CTL_DEBUG			3
>   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index c06fd250e037..091825a34138 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3474,6 +3474,13 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> +				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> +				  /* dmabuf */
> +				  op == DRM_XE_VM_BIND_OP_MAP ||

This is not really dma-buf, but rather all BOs. You likely need to add 
something in xe_vm_bind_ioctl_validate_bo(), checking for dma-buf. See 
the coh checks, for example.

> +				  /* svm */
> +				  op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)) &&
> +				 (pat_index != 19 || coh_mode != XE_COH_2WAY)) ||
>   		    XE_IOCTL_DBG(xe, comp_en &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 1a1ad8c07d49..e68ee5b092d6 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -304,6 +304,10 @@ static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madv
>   		if (XE_WARN_ON(coh_mode > XE_COH_2WAY))
>   			return false;
>   
> +		if (XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> +				 (pat_index != 19 || coh_mode != XE_COH_2WAY)))

I think you need to make this conditional on what the vma(s) are 
mapping? So dma-buf, userptr, svm and normal BOs?

> +			return false;
> +
>   		if (XE_IOCTL_DBG(xe, args->pat_index.pad))
>   			return false;
>