Re: [PATCH v2] drm/i915/display: Ensure a non-zero safe window from PTL onwards

["Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>]

On 7/22/2026 11:54 AM, Ankit Nautiyal wrote:
>  From PTL onwards, the set context latency can be in the vactive region,
> letting the safe window start some lines before the vblank start. The DSB
> waits on this safe window instead of vblank (bits [15:14] select the safe
> window signal from the DPT unit to start the DMA engine).
> 
> With modes that have a smaller vblank region, the computed guardband is
> clamped to the vblank length, making the undelayed and delayed vblank
> coincide. If the SCL is also 0, the 'safe window' becomes effectively 0,
> and the DSB configured to wait for it gets stalled, since the hardware
> never signals the safe window, leading to:
> 
>    *ERROR* [CRTC:159:pipe A] flip_done timed out
>    *ERROR* [CRTC:159:pipe A] DSB 0 timed out waiting for idle
> 
> Keep the set context latency at a minimum of 1 to avoid this.
> 
> v2: Fix the bit numbers and correct the commit message. (Chaitanya)
> 

It still looks *safe* to me ;) the commit message is good now.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> Fixes: 4a68c7516c57 ("drm/i915/dsb: Use safe window path when VRR TG is used")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Assisted-by: GitHub-Copilot:Claude-Opus-4.8
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 38763a6802c5..0822a2194c7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2459,6 +2459,19 @@ static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
>   	set_context_latency = max(set_context_latency,
>   				  intel_psr_min_set_context_latency(crtc_state));
>   
> +	/*
> +	 * From PTL onwards, the set context latency can be in the vactive
> +	 * region, letting the safe window start some lines before the vblank
> +	 * start. With modes that have a smaller vblank region, the computed
> +	 * guardband is clamped to the vblank length, making the undelayed and
> +	 * delayed vblank coincide. If the SCL is also 0, the 'safe window'
> +	 * becomes effectively 0, and the DSB configured to wait for it gets
> +	 * stalled, since the hardware never signals the safe window. Keep the
> +	 * set context latency at a minimum of 1 to avoid this.
> +	 */
> +	if (DISPLAY_VER(display) >= 30)
> +		set_context_latency = max(1, set_context_latency);
> +
>   	return set_context_latency;
>   }
>