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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH7PR11MB8252.namprd11.prod.outlook.com (2603:10b6:510:1aa::14) by MW3PR11MB4684.namprd11.prod.outlook.com (2603:10b6:303:5d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.6; Fri, 16 Jan 2026 08:56:32 +0000 Received: from PH7PR11MB8252.namprd11.prod.outlook.com ([fe80::9f66:9d6f:3199:78b2]) by PH7PR11MB8252.namprd11.prod.outlook.com ([fe80::9f66:9d6f:3199:78b2%4]) with mapi id 15.20.9520.005; Fri, 16 Jan 2026 08:56:31 +0000 Message-ID: <0c2516b7-bd75-49f4-b77a-183cf020262c@intel.com> Date: Fri, 16 Jan 2026 14:26:22 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset To: Daniele Ceraolo Spurio , CC: , , , , , , , , , References: <20260114130015.3917770-4-sk.anirban@intel.com> <20260114130015.3917770-6-sk.anirban@intel.com> <35fae126-1b3d-4cf0-9240-b1456c9ae37d@intel.com> Content-Language: en-US From: "Anirban, Sk" In-Reply-To: <35fae126-1b3d-4cf0-9240-b1456c9ae37d@intel.com> Content-Type: text/plain; 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Without this, reset >> can be issued while SRAM handler is copying WOPCM to SRAM, >> causing GuC HW to get stuck. >> >> Signed-off-by: Sk Anirban >> --- >>   drivers/gpu/drm/xe/regs/xe_guc_regs.h |  8 ++++++ >>   drivers/gpu/drm/xe/xe_guc.c           | 37 ++++++++++++++++++++++++++- >>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  9 +++++++ >>   3 files changed, 53 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h >> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h >> index 87984713dd12..2f38fd231083 100644 >> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h >> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h >> @@ -40,6 +40,9 @@ >>   #define   GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76) >>   #define   GS_MIA_IN_RESET            REG_BIT(0) >>   +#define GUC_HASH_BOOT_CHECK            XE_REG(0xc010) >> +#define   GUC_BOOT_HASH_CHK            REG_BIT(31) > > The naming here is a bit confusing, because the register and the field > have basically the same name with the word order changed. AFAICS bit > 31 has a different name in the specs, so maybe match that? Sure, I will change the name in next rev. > >> + >>   #define GUC_HEADER_INFO                XE_REG(0xc014) >>     #define GUC_WOPCM_SIZE                XE_REG(0xc050) >> @@ -83,7 +86,12 @@ >>   #define   GUC_WOPCM_OFFSET_MASK            REG_GENMASK(31, >> GUC_WOPCM_OFFSET_SHIFT) >>   #define   HUC_LOADING_AGENT_GUC            REG_BIT(1) >>   #define   GUC_WOPCM_OFFSET_VALID        REG_BIT(0) >> + >> +#define GUC_SRAM_STATUS                XE_REG(0xc398) >> +#define   GUC_SRAM_HANDLING_MASK        REG_GENMASK(8, 7) >> + >>   #define GUC_MAX_IDLE_COUNT            XE_REG(0xc3e4) >> +#define   GUC_IDLE_FLOW_DISABLE            REG_BIT(31) >>   #define GUC_PMTIMESTAMP_LO            XE_REG(0xc3e8) >>   #define GUC_PMTIMESTAMP_HI            XE_REG(0xc3ec) >>   diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c >> index 44360437beeb..b5ec08a16aaf 100644 >> --- a/drivers/gpu/drm/xe/xe_guc.c >> +++ b/drivers/gpu/drm/xe/xe_guc.c >> @@ -900,6 +900,35 @@ int xe_guc_post_load_init(struct xe_guc *guc) >>       return xe_guc_submit_enable(guc); >>   } >>   +/* >> + * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only >> reset by ensuring >> + * SRAM save/restore operations are complete before reset. >> + */ >> +static int guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc) >> +{ >> +    struct xe_gt *gt = guc_to_gt(guc); >> +    u32 boot_hash_chk, guc_status, sram_status; >> + >> +    guc_status = xe_mmio_read32(>->mmio, GUC_STATUS); >> +    if (REG_FIELD_GET(GS_UKERNEL_MASK, guc_status) != >> XE_GUC_LOAD_STATUS_READY) > > Why are we skipping this if the status is different than > XE_GUC_LOAD_STATUS_READY? > During an SRAM save/restore the status can be different from that. Thanks for pointing this out. As discussed, I will check only when MIA_RESET is set; otherwise, we will proceed with the WA. > >> +        return 0; >> + >> +    boot_hash_chk = xe_mmio_read32(>->mmio, GUC_HASH_BOOT_CHECK); >> +    if (!(boot_hash_chk & GUC_BOOT_HASH_CHK)) >> +        return 0; >> + >> +    xe_mmio_rmw32(>->mmio, GUC_MAX_IDLE_COUNT, 0, >> GUC_IDLE_FLOW_DISABLE); > > We should re-enable this after the reset, otherwise the GT won't power > off. I observed that after the guc reset the bit is getting cleared, so we do not need to re-enable it on the top of that. > >> + >> +    sram_status = xe_mmio_read32(>->mmio, GUC_SRAM_STATUS); > > The WA says that we need to poll this register until the status > changes, not just read it once. sure, I had a talk with Hema and a timeout of 5ms should work fine. I am implementing that and in case of timeout also it will for for guc reset. > > Daniele Thanks, Anirban > >> +    if (sram_status & GUC_SRAM_HANDLING_MASK) { >> +        xe_gt_err(gt, "SRAM handling not complete (GUC_SRAM_STATUS: >> 0x%x)\n", >> +              sram_status); >> +        return -EIO; >> +    } >> + >> +    return 0; >> +} >> + >>   int xe_guc_reset(struct xe_guc *guc) >>   { >>       struct xe_gt *gt = guc_to_gt(guc); >> @@ -909,6 +938,12 @@ int xe_guc_reset(struct xe_guc *guc) >>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); >>   +    if (XE_GT_WA(gt, 14025883347)) { >> +        ret = guc_prevent_fw_dma_failure_on_reset(guc); >> +        if (ret) >> +            goto err_out; >> +    } >> + >>       if (IS_SRIOV_VF(gt_to_xe(gt))) >>           return xe_gt_sriov_vf_bootstrap(gt); >>   @@ -931,7 +966,7 @@ int xe_guc_reset(struct xe_guc *guc) >>       return 0; >>     err_out: >> - >> +    xe_gt_err(gt, "custom GuC reset failed with %pe\n", ERR_PTR(ret)); >>       return ret; >>   } >>   diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules >> b/drivers/gpu/drm/xe/xe_wa_oob.rules >> index 5cd7fa6d2a5c..ff2efc7a68cc 100644 >> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules >> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules >> @@ -73,3 +73,12 @@ >>   15015404425_disable    PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER) >>   16026007364    MEDIA_VERSION(3000) >>   14020316580    MEDIA_VERSION(1301) >> + >> +14025883347    MEDIA_VERSION(1301) >> +        MEDIA_VERSION(2000) >> +        MEDIA_VERSION(3000) >> +        MEDIA_VERSION(3002) >> +        MEDIA_VERSION(3500) >> +        MEDIA_VERSION(3503) >> +        GRAPHICS_VERSION_RANGE(3000, 3001) >> +        GRAPHICS_VERSION_RANGE(3003, 3005) >