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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by MW3PR11MB4588.namprd11.prod.outlook.com (2603:10b6:303:54::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.11; Thu, 5 Dec 2024 04:49:38 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.8230.010; Thu, 5 Dec 2024 04:49:38 +0000 Message-ID: <0d150b3f-b43e-4113-b52a-1e0e984f558b@intel.com> Date: Thu, 5 Dec 2024 10:19:32 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/6] drm/i915/vrr: Compute vrr.vsync_{start, end} during full modeset To: Mitul Golani , CC: , , References: <20241202024540.2578856-1-mitulkumar.ajitkumar.golani@intel.com> <20241202024540.2578856-3-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20241202024540.2578856-3-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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[Ville] > --v3: > - Create separate patch for crtc_state_dump [Ankit]. > > --v4: > - Update commit message and header [Ankit]. > > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 25 ++++++++++-------------- > 1 file changed, 10 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index b386e62d1664..c395af419ce3 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -236,7 +236,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > } > > - if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) { > + if (HAS_AS_SDP(display)) { > crtc_state->vrr.vsync_start = > (crtc_state->hw.adjusted_mode.crtc_vtotal - > crtc_state->hw.adjusted_mode.vsync_start); > @@ -316,6 +316,12 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) > trans_vrr_ctl(crtc_state)); > intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), > crtc_state->vrr.flipline - 1); > + > + if (HAS_AS_SDP(display)) > + intel_de_write(display, > + TRANS_VRR_VSYNC(display, cpu_transcoder), > + VRR_VSYNC_END(crtc_state->vrr.vsync_end) | > + VRR_VSYNC_START(crtc_state->vrr.vsync_start)); > } > > void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) > @@ -352,12 +358,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), > TRANS_PUSH_EN); > > - if (HAS_AS_SDP(display)) > - intel_de_write(display, > - TRANS_VRR_VSYNC(display, cpu_transcoder), > - VRR_VSYNC_END(crtc_state->vrr.vsync_end) | > - VRR_VSYNC_START(crtc_state->vrr.vsync_start)); > - > if (crtc_state->cmrr.enable) { > intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), > VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | > @@ -382,10 +382,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > TRANS_VRR_STATUS(display, cpu_transcoder), > VRR_STATUS_VRR_EN_LIVE, 1000); > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); > - > - if (HAS_AS_SDP(display)) > - intel_de_write(display, > - TRANS_VRR_VSYNC(display, cpu_transcoder), 0); > } > > void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > @@ -425,10 +421,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; > crtc_state->vrr.vmin = intel_de_read(display, > TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; > - } > - > - if (crtc_state->vrr.enable) { > - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > > if (HAS_AS_SDP(display)) { > trans_vrr_vsync = > @@ -440,4 +432,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync); > } > } > + > + if (crtc_state->vrr.enable) > + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > }