[PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB

[PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB

[Mitul Golani]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (10):
  drm/i915/display: Add source param for dc balance
  drm/i915/display: Add VRR DC balance registers
  drm/i915/vrr: Add DC Balance params to crtc_state
  drm/i915/vrr: Add state dump for DC Balance params
  drm/i915/vrr: Add compute config for DC Balance params
  drm/i915/vrr: Write DC balance params to hw registers
  drm/i915/vrr: Add function to check if DC Balance Possible
  drm/i915/display: Add function to configure PIPEDMC_EVT_CTL
  drm/i915/vrr: Enable Adaptive sync counter bit
  drm/i915/vrr: Enable DC Balance

Ville Syrjälä (8):
  drm/i915/vrr: Refactor vmin/vmax stuff
  drm/i915/display: Add pipe dmc registers and bits for DC Balance
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Restructure VRR enablement bit
  drm/i915/vrr: Pause DC Balancing for DSB commits

 .../drm/i915/display/intel_crtc_state_dump.c  |   8 +
 drivers/gpu/drm/i915/display/intel_display.c  |  26 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  35 +++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   7 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  51 ++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 ++-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 240 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  45 ++++
 12 files changed, 449 insertions(+), 40 deletions(-)

-- 
2.48.1

[PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Refactor vmin/vmax functions for better computation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++++++++++-------------
 1 file changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3eed37f271b0..dd8fe4b49690 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -146,37 +146,41 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
 }
 
-int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	/* Min vblank actually determined by flipline */
 	if (DISPLAY_VER(display) >= 13)
-		return intel_vrr_vmin_flipline(crtc_state);
+		return vmin_vmax;
 	else
-		return intel_vrr_vmin_flipline(crtc_state) +
-			intel_vrr_real_vblank_delay(crtc_state);
+		return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
 }
 
-int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+				  int vmin_vmax)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	return intel_vrr_vtotal(crtc_state, vmin_vmax) -
+			intel_vrr_vblank_exit_length(crtc_state);
+}
 
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_state->vrr.vmax;
-	else
-		return crtc_state->vrr.vmax +
-			intel_vrr_real_vblank_delay(crtc_state);
+int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state));
+}
+
+int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
 }
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state));
 }
 
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
 }
 
 static bool
@@ -257,14 +261,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 static
 int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-	int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
-
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_vtotal;
-	else
-		return crtc_vtotal -
-			intel_vrr_real_vblank_delay(crtc_state);
+	return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
 }
 
 static
-- 
2.48.1

[PATCH v7 02/18] drm/i915/display: Add source param for dc balance

[Mitul Golani]

Add source param for dc balance enablement further.

--v2:
- Arrange in alphabetic order. (Ankit)
- Update name. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 0ac5484c0043..201a22d71bf0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -196,6 +196,7 @@ struct intel_display_platforms {
 					  ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \
 					 HAS_DSC(__display))
 #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
+#define HAS_VRR_DC_BALANCE(__display)	(DISPLAY_VER(__display) >= 30)
 #define INTEL_NUM_PIPES(__display)	(hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
 #define OVERLAY_NEEDS_PHYSICAL(__display)	(DISPLAY_INFO(__display)->overlay_needs_physical)
 #define SUPPORTS_TV(__display)		(DISPLAY_INFO(__display)->supports_tv)
-- 
2.48.1

[PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add pipe dmc registers and  access bits for DC Balance params
configuration and enablement.

--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)

--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.

Co-authored-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 6f406315dd65..66cc92cc3f50 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -394,4 +394,55 @@ enum pipedmc_event_id {
 #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
 #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
 
+#define _PIPEDMC_DCB_CTL_A			0x5f1a0
+#define _PIPEDMC_DCB_CTL_B			0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+							   _PIPEDMC_DCB_CTL_B)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A			0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B			0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+							   _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A			0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B			0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+							   _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A		0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B		0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+							   _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A		0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B		0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+							   _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A		0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B		0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+							   _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A			0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B			0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+							   _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A			0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B			0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+							   _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A			0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B			0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+							   _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A			0x5f040
+#define _PIPEDMC_EVT_CTL_3_B			0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+							   _PIPEDMC_EVT_CTL_3_B)
+
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.48.1

[PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers

[Mitul Golani]

Add VRR register offsets and bits to access DC Balance configuration.

--v2:
- Separate register definitions. (Ankit)
- Remove usage of dev_priv. (Jani, Nikula)

--v3:
- Convert register address offset, from capital to small. (Ankit)
- Move mask bits near to register offsets. (Ankit)

--v4:
- Use _MMIO_TRANS wherever possible. (Jani)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..c5cba5879f40 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,50 @@
 
 #include "intel_display_reg_defs.h"
 
+/* VRR registers */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_FLIPLINE_A		0x60418
+#define _TRANS_VRR_DCB_FLIPLINE_B		0x61418
+#define TRANS_VRR_DCB_FLIPLINE(trans)		_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_FLIPLINE_A, \
+							    _TRANS_VRR_DCB_FLIPLINE_B)
+#define VRR_DCB_FLIPLINE_MASK			REG_GENMASK(19, 0)
+#define VRR_DCB_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_VMAX_A			0x60414
+#define _TRANS_VRR_DCB_VMAX_B			0x61414
+#define TRANS_VRR_DCB_VMAX(trans)		_MMIO_TRANS(trans, \
+							     _TRANS_VRR_DCB_VMAX_A, \
+							     _TRANS_VRR_DCB_VMAX_B)
+#define VRR_DCB_VMAX_MASK			REG_GENMASK(19, 0)
+#define VRR_DCB_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS(trans, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define ADAPTIVE_SYNC_COUNTER_EN		REG_BIT(31)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
@@ -20,6 +64,7 @@
 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
+#define   VRR_CTL_DCB_ADJ_ENABLE		REG_BIT(28)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
 
-- 
2.48.1

[PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

--v2:
- Correct Author details.

--v3:
- Separate register details from this  patch.

--v4:
- Add mask macros.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 50 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index dd8fe4b49690..d7bc35b07bab 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -769,3 +769,53 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

[PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state

[Mitul Golani]

Add DC Balance params to crtc_state, also add state checker
params for related properties.

--v3:
- Seggregate crtc_state params with this patch. (Ankit)

--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  7 ++++++
 .../drm/i915/display/intel_display_types.h    |  7 ++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 22 +++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de8bf292897c..939366ecea85 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5429,6 +5429,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 30c7315fc25e..e5461900c15b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1316,6 +1316,13 @@ struct intel_crtc_state {
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
+		struct {
+			bool enable;
+			u16 vmin, vmax;
+			u16 guardband, slope;
+			u16 max_increase, max_decrease;
+			u16 vblank_target;
+		} dc_balance;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d7bc35b07bab..4016da70ece2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_dmc_regs.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
 
@@ -699,6 +700,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
 	u32 trans_vrr_ctl, trans_vrr_vsync;
 	bool vrr_enable;
 
@@ -761,6 +764,25 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->vrr.enable = vrr_enable;
 
+	if (HAS_VRR_DC_BALANCE(display)) {
+		crtc_state->vrr.dc_balance.vmin =
+			intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ?
+			intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0;
+		crtc_state->vrr.dc_balance.vmax =
+			intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ?
+			intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0;
+		crtc_state->vrr.dc_balance.guardband =
+			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
+		crtc_state->vrr.dc_balance.max_increase =
+			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
+		crtc_state->vrr.dc_balance.max_decrease =
+			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
+		crtc_state->vrr.dc_balance.slope =
+			intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
+		crtc_state->vrr.dc_balance.vblank_target =
+			intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
+	}
+
 	/*
 	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
 	 * Since CMRR is currently disabled, set this flag for VRR for now.
-- 
2.48.1

[PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params

[Mitul Golani]

Add state dump for dc balance params to track DC Balance
crtc state config.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..7a3d97df24c0 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -304,6 +304,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
 		   intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
 		   intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
+	drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d Vblank target: %d\n",
+		   str_yes_no(pipe_config->vrr.dc_balance.enable),
+		   pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+		   pipe_config->vrr.dc_balance.guardband,
+		   pipe_config->vrr.dc_balance.slope,
+		   pipe_config->vrr.dc_balance.max_increase,
+		   pipe_config->vrr.dc_balance.max_decrease,
+		   pipe_config->vrr.dc_balance.vblank_target);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v7 08/18] drm/i915/vrr: Add compute config for DC Balance params

[Mitul Golani]

Compute DC Balance parameters and tunable params based on
experiments.

--v2:
- Document tunable params. (Ankit)

--v3:
- Add line spaces to compute config. (Ankit)
- Remove redundancy checks.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4016da70ece2..07cd7cb38b97 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -16,6 +16,13 @@
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
+/*
+ * Tunable parameters for DC Balance correction.
+ * These are captured based on experimentations.
+ */
+#define DCB_CORRECTION_SENSITIVITY	30
+#define DCB_CORRECTION_AGGRESSIVENESS	1000
+#define DCB_BLANK_TARGET		50
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
@@ -409,6 +416,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.vsync_end);
 	}
+
+	if (crtc_state->vrr.dc_balance.enable) {
+		crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+		crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.max_increase =
+			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.max_decrease =
+			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.guardband =
+			DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
+				     DCB_CORRECTION_SENSITIVITY, 100);
+		crtc_state->vrr.dc_balance.slope =
+			DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
+				     crtc_state->vrr.dc_balance.guardband);
+		crtc_state->vrr.dc_balance.vblank_target =
+			DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
+				     DCB_BLANK_TARGET, 100);
+	}
 }
 
 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
-- 
2.48.1

[PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers

[Mitul Golani]

Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 43 ++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 07cd7cb38b97..ce23bcab1033 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -622,6 +622,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
 
 	if (!crtc_state->vrr.enable)
 		return;
@@ -648,16 +650,57 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
 		}
 	}
+
+	if (crtc_state->vrr.dc_balance.enable) {
+		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+			       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+		intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+			       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+			       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+		intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+			       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+		intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+			       crtc_state->vrr.dc_balance.vmin - 1);
+		intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+			       crtc_state->vrr.dc_balance.vmax - 1);
+		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+			       crtc_state->vrr.dc_balance.max_increase);
+		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+			       crtc_state->vrr.dc_balance.max_decrease);
+		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+			       crtc_state->vrr.dc_balance.guardband);
+		intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+			       crtc_state->vrr.dc_balance.slope);
+		intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+			       crtc_state->vrr.dc_balance.vblank_target);
+	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
 
 	if (!old_crtc_state->vrr.enable)
 		return;
 
+	if (old_crtc_state->vrr.dc_balance.enable) {
+		intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+		intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+		intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+		intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+		intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+	}
+
 	if (!intel_vrr_always_use_vrr_tg(display)) {
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       trans_vrr_ctl(old_crtc_state));
-- 
2.48.1

[PATCH v7 10/18] drm/i915: Extract vrr_vblank_start()

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Initialise delayed vblank position for evasion logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 70ba7aa26bf4..d544e274bcfa 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
 }
 
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_vrr_is_push_sent(crtc_state))
+		return intel_vrr_vmin_vblank_start(crtc_state);
+	else
+		return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
 			     struct intel_vblank_evade_ctx *evade)
@@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
 			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
 
-		if (intel_vrr_is_push_sent(crtc_state))
-			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-		else
-			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+		evade->vblank_start = vrr_vblank_start(crtc_state);
 
 		vblank_delay = intel_vrr_vblank_delay(crtc_state);
 	} else {
-- 
2.48.1

[PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 31 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 53d8ae3a70e9..ec624dc1987e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -721,7 +721,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 	if (crtc_state->has_psr)
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
-	if (pre_commit_is_vrr_active(state, crtc)) {
+	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		int vmin_vblank_start, vmax_vblank_start;
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+		if (vmin_vblank_start >= 0) {
+			end = vmin_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+		if (vmax_vblank_start >= 0) {
+			end = vmax_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+		end = vmin_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+		end = vmax_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+	} else if (pre_commit_is_vrr_active(state, crtc)) {
 		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index d544e274bcfa..685768124852 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 
 static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	if (intel_vrr_is_push_sent(crtc_state))
-		return intel_vrr_vmin_vblank_start(crtc_state);
+	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+	int vblank_start;
+
+	if (!crtc_state->vrr.dc_balance.enable) {
+		if (is_push_sent)
+			return intel_vrr_vmin_vblank_start(crtc_state);
+		else
+			return intel_vrr_vmax_vblank_start(crtc_state);
+	}
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
 	else
-		return intel_vrr_vmax_vblank_start(crtc_state);
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+	if (vblank_start >= 0)
+		return vblank_start;
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+	else
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+	return vblank_start;
 }
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
-- 
2.48.1

[PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add function to control DC balance enable/disable bit via DSB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  5 +++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 4572e87d9bfa..1726c0ab18c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1607,3 +1607,21 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
 			crtc->base.base.id, crtc->base.name, tmp);
 }
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 7820fa5aed3e..d45d51bedb87 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -8,11 +8,14 @@
 
 #include <linux/types.h>
 
+
 enum pipe;
+struct intel_crtc;
 struct drm_printer;
 struct intel_crtc_state;
 struct intel_display;
 struct intel_dmc_snapshot;
+struct intel_dsb;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
@@ -36,5 +39,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
 void assert_main_dmc_loaded(struct intel_display *display);
 
 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
 
 #endif /* __INTEL_DMC_H__ */
-- 
2.48.1

[PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Restructure bits for VRR enablement.

--v2:
- Separate multiple enablement from one patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 29 ++++++++++++------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ce23bcab1033..91d4fa0d2bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -624,6 +624,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 ctl;
 
 	if (!crtc_state->vrr.enable)
 		return;
@@ -638,19 +639,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 		       TRANS_PUSH_EN);
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_vrr_set_db_point_and_transmission_line(crtc_state);
-
-		if (crtc_state->cmrr.enable) {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
-				       trans_vrr_ctl(crtc_state));
-		} else {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
-		}
-	}
-
 	if (crtc_state->vrr.dc_balance.enable) {
 		intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
 			       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
@@ -675,6 +663,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
 			       crtc_state->vrr.dc_balance.vblank_target);
 	}
+
+	ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+	if (crtc_state->cmrr.enable)
+		ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -683,10 +677,17 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 ctl;
 
 	if (!old_crtc_state->vrr.enable)
 		return;
 
+	ctl = trans_vrr_ctl(old_crtc_state);
+	if (intel_vrr_always_use_vrr_tg(display))
+		ctl |= VRR_CTL_VRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
 	if (old_crtc_state->vrr.dc_balance.enable) {
 		intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
 		intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
@@ -702,8 +703,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	}
 
 	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-			       trans_vrr_ctl(old_crtc_state));
 		intel_de_wait_for_clear(display,
 					TRANS_VRR_STATUS(display, cpu_transcoder),
 					VRR_STATUS_VRR_EN_LIVE, 1000);
-- 
2.48.1

[PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)

--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c     |  7 +++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 939366ecea85..d1f6ff4bfc99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7231,6 +7231,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	}
 
 	if (new_crtc_state->use_dsb) {
+		if (new_crtc_state->vrr.dc_balance.enable) {
+			/*
+			 * Pause the DMC DC balancing for the remainder of
+			 * the commit so that vmin/vmax won't change after
+			 * we've baked them into the DSB vblank evasion
+			 * commands.
+			 *
+			 * FIXME maybe need a small delay here to make sure
+			 * DMC has finished updating the values? Or we need
+			 * a better DMC<->driver protocol that gives is real
+			 * guarantees about that...
+			 */
+			intel_pipedmc_dcb_disable(NULL, crtc);
+		}
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7276,6 +7291,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
+
+		if (new_crtc_state->vrr.dc_balance.enable)
+			intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
+
 		intel_dsb_interrupt(new_crtc_state->dsb_commit);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 91d4fa0d2bf3..98d305d02f35 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dmc_regs.h"
 #include "intel_vrr.h"
@@ -668,6 +669,9 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->cmrr.enable)
 		ctl |= VRR_CTL_CMRR_ENABLE;
 
+	if (crtc_state->vrr.dc_balance.enable)
+		intel_pipedmc_dcb_enable(NULL, crtc);
+
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 }
 
@@ -682,6 +686,9 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->vrr.enable)
 		return;
 
+	if (old_crtc_state->vrr.dc_balance.enable)
+		intel_pipedmc_dcb_disable(NULL, crtc);
+
 	ctl = trans_vrr_ctl(old_crtc_state);
 	if (intel_vrr_always_use_vrr_tg(display))
 		ctl |= VRR_CTL_VRR_ENABLE;
-- 
2.48.1

[PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible

[Mitul Golani]

Add function to check if DC Balance possibile on
requested PIPE and also validate along with DISPLAY_VER
check.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 98d305d02f35..8d7d19b86376 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -256,6 +256,22 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
+static
+int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	/*
+	 * FIXME: Currently Firmware supports DC Balancing on PIPE A
+	 * and PIPE B. Account those limitation while computing DC
+	 * Balance parameters.
+	 */
+	return (HAS_VRR_DC_BALANCE(display) &&
+		((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
 static
 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 {
-- 
2.48.1

[PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL

[Mitul Golani]

Configure PIPEDMC_EVT_CTL_3 register with required event flags.

--v2:
- Initialize with redundant flags. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c |  8 ++++++--
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1726c0ab18c2..3b81a7b48035 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -810,6 +810,23 @@ void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
 		     PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0);
 }
 
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+					     enum pipe pipe, bool enable)
+{
+	u32 val = REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+				 DMC_EVT_CTL_TYPE_EDGE_0_1);
+
+	if (enable)
+		val |= DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
+			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+				       PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER);
+	else
+		val |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+				      DMC_EVENT_FALSE);
+
+	intel_de_write(display, PIPEDMC_EVT_CTL_3(pipe), val);
+}
+
 /**
  * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG
  * C-state exit
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index d45d51bedb87..032f3e3072ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -24,6 +24,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
 			  bool block);
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+					     enum pipe pipe, bool enable);
 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
 							    enum pipe pipe, bool enable);
 void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8d7d19b86376..5eb4a7e97291 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -685,8 +685,10 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->cmrr.enable)
 		ctl |= VRR_CTL_CMRR_ENABLE;
 
-	if (crtc_state->vrr.dc_balance.enable)
+	if (crtc_state->vrr.dc_balance.enable) {
+		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
 		intel_pipedmc_dcb_enable(NULL, crtc);
+	}
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 }
@@ -702,8 +704,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->vrr.enable)
 		return;
 
-	if (old_crtc_state->vrr.dc_balance.enable)
+	if (old_crtc_state->vrr.dc_balance.enable) {
 		intel_pipedmc_dcb_disable(NULL, crtc);
+		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
+	}
 
 	ctl = trans_vrr_ctl(old_crtc_state);
 	if (intel_vrr_always_use_vrr_tg(display))
-- 
2.48.1

[PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit

[Mitul Golani]

Add enable/disable frame counters for DC Balance odd and even
frame count calculation.

--v2:
Update commit message

--v3:
- Driver should not control adjustment enable bit, as that
is already being controlled by firmware. Release bit from
driver computation.
- Commit message update.

--v4:
- Configure PIPEDMC_EVT_CTL enable/disable call.

--v5:
- Add Adaptive sync counter enable.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5eb4a7e97291..d5359a96054b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -686,6 +686,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		ctl |= VRR_CTL_CMRR_ENABLE;
 
 	if (crtc_state->vrr.dc_balance.enable) {
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+			       ADAPTIVE_SYNC_COUNTER_EN);
 		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
 		intel_pipedmc_dcb_enable(NULL, crtc);
 	}
@@ -707,6 +709,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (old_crtc_state->vrr.dc_balance.enable) {
 		intel_pipedmc_dcb_disable(NULL, crtc);
 		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
 	}
 
 	ctl = trans_vrr_ctl(old_crtc_state);
-- 
2.48.1

[PATCH v7 18/18] drm/i915/vrr: Enable DC Balance

[Mitul Golani]

Enable DC Balance from vrr compute config and related hw flag.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d5359a96054b..e48a795a8c18 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -277,6 +277,9 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->vrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+	if (intel_vrr_dc_balance_possible(crtc_state))
+		crtc_state->vrr.dc_balance.enable = true;
 }
 
 /*
@@ -686,6 +689,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		ctl |= VRR_CTL_CMRR_ENABLE;
 
 	if (crtc_state->vrr.dc_balance.enable) {
+		ctl |= VRR_CTL_DCB_ADJ_ENABLE;
 		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 			       ADAPTIVE_SYNC_COUNTER_EN);
 		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
-- 
2.48.1

Re: [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers

[Jani Nikula]

On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add VRR register offsets and bits to access DC Balance configuration.
>
> --v2:
> - Separate register definitions. (Ankit)
> - Remove usage of dev_priv. (Jani, Nikula)
>
> --v3:
> - Convert register address offset, from capital to small. (Ankit)
> - Move mask bits near to register offsets. (Ankit)
>
> --v4:
> - Use _MMIO_TRANS wherever possible. (Jani)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

I just took the time to clean this file up. See commit 880e07d53849
("drm/i915/vrr: fix register file style"). Please follow the style.

> ---
>  drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index ba9b9215dc11..c5cba5879f40 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -8,6 +8,50 @@
>  
>  #include "intel_display_reg_defs.h"
>  
> +/* VRR registers */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS(trans, \
> +							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
> +							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
> +							       (flipline))
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS(trans, \
> +							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
> +							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
> +#define VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
> +
> +#define _TRANS_VRR_DCB_FLIPLINE_A		0x60418
> +#define _TRANS_VRR_DCB_FLIPLINE_B		0x61418
> +#define TRANS_VRR_DCB_FLIPLINE(trans)		_MMIO_TRANS(trans, \
> +							    _TRANS_VRR_DCB_FLIPLINE_A, \
> +							    _TRANS_VRR_DCB_FLIPLINE_B)
> +#define VRR_DCB_FLIPLINE_MASK			REG_GENMASK(19, 0)
> +#define VRR_DCB_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
> +							       (flipline))
> +
> +#define _TRANS_VRR_DCB_VMAX_A			0x60414
> +#define _TRANS_VRR_DCB_VMAX_B			0x61414
> +#define TRANS_VRR_DCB_VMAX(trans)		_MMIO_TRANS(trans, \
> +							     _TRANS_VRR_DCB_VMAX_A, \
> +							     _TRANS_VRR_DCB_VMAX_B)
> +#define VRR_DCB_VMAX_MASK			REG_GENMASK(19, 0)
> +#define VRR_DCB_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
> +
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS(trans, \
> +							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
> +							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
> +#define ADAPTIVE_SYNC_COUNTER_EN		REG_BIT(31)
> +
>  #define _TRANS_VRR_CTL_A			0x60420
>  #define _TRANS_VRR_CTL_B			0x61420
>  #define _TRANS_VRR_CTL_C			0x62420
> @@ -20,6 +64,7 @@
>  #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
>  #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
>  #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
> +#define   VRR_CTL_DCB_ADJ_ENABLE		REG_BIT(28)

Highest to lowest bit.

>  #define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
>  #define   XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))

-- 
Jani Nikula, Intel

Re: [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state

[Jani Nikula]

On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add DC Balance params to crtc_state, also add state checker
> params for related properties.
>
> --v3:
> - Seggregate crtc_state params with this patch. (Ankit)
>
> --v4:
> - Update commit message and header. (Ankit)
> - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  7 ++++++
>  .../drm/i915/display/intel_display_types.h    |  7 ++++++
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 22 +++++++++++++++++++
>  3 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index de8bf292897c..939366ecea85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5429,6 +5429,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>  		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>  		PIPE_CONF_CHECK_BOOL(cmrr.enable);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
>  	}
>  
>  	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 30c7315fc25e..e5461900c15b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1316,6 +1316,13 @@ struct intel_crtc_state {
>  		u8 pipeline_full;
>  		u16 flipline, vmin, vmax, guardband;
>  		u32 vsync_end, vsync_start;
> +		struct {
> +			bool enable;
> +			u16 vmin, vmax;
> +			u16 guardband, slope;
> +			u16 max_increase, max_decrease;
> +			u16 vblank_target;
> +		} dc_balance;
>  	} vrr;
>  
>  	/* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d7bc35b07bab..4016da70ece2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
> +#include "intel_dmc_regs.h"

Please keep the includes sorted.

>  #include "intel_vrr.h"
>  #include "intel_vrr_regs.h"
>  
> @@ -699,6 +700,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
>  	u32 trans_vrr_ctl, trans_vrr_vsync;
>  	bool vrr_enable;
>  
> @@ -761,6 +764,25 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	else
>  		crtc_state->vrr.enable = vrr_enable;
>  
> +	if (HAS_VRR_DC_BALANCE(display)) {
> +		crtc_state->vrr.dc_balance.vmin =
> +			intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ?
> +			intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0;
> +		crtc_state->vrr.dc_balance.vmax =
> +			intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ?
> +			intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0;
> +		crtc_state->vrr.dc_balance.guardband =
> +			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
> +		crtc_state->vrr.dc_balance.max_increase =
> +			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
> +		crtc_state->vrr.dc_balance.max_decrease =
> +			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
> +		crtc_state->vrr.dc_balance.slope =
> +			intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
> +		crtc_state->vrr.dc_balance.vblank_target =
> +			intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
> +	}
> +
>  	/*
>  	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
>  	 * Since CMRR is currently disabled, set this flag for VRR for now.

-- 
Jani Nikula, Intel

Re: [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Jani Nikula]

On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add function to control DC balance enable/disable bit via DSB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dmc.h |  5 +++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 4572e87d9bfa..1726c0ab18c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1607,3 +1607,21 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
>  		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
>  			crtc->base.base.id, crtc->base.name, tmp);
>  }
> +
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
> +			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
> +}
> +
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 7820fa5aed3e..d45d51bedb87 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -8,11 +8,14 @@
>  
>  #include <linux/types.h>
>  
> +

Please run checkpatch before sending.

>  enum pipe;
> +struct intel_crtc;
>  struct drm_printer;
>  struct intel_crtc_state;
>  struct intel_display;
>  struct intel_dmc_snapshot;
> +struct intel_dsb;
>  
>  void intel_dmc_init(struct intel_display *display);
>  void intel_dmc_load_program(struct intel_display *display);
> @@ -36,5 +39,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
>  void assert_main_dmc_loaded(struct intel_display *display);
>  
>  void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
>  
>  #endif /* __INTEL_DMC_H__ */

-- 
Jani Nikula, Intel

✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB (rev8)

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev8)
URL   : https://patchwork.freedesktop.org/series/148025/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit a2dc34c14d03b87d125259fab33998b8c83d7550
Author: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Date:   Tue Jun 24 13:19:48 2025 +0530

    drm/i915/vrr: Enable DC Balance
    
    Enable DC Balance from vrr compute config and related hw flag.
    
    Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+ /mt/dim checkpatch fb5dada21e3cfa26179ca58e1d7c26cdad217201 drm-intel
7ed94d9a43c8 drm/i915/vrr: Refactor vmin/vmax stuff
a512eeaacd08 drm/i915/display: Add source param for dc balance
b5eca743cfd0 drm/i915/display: Add pipe dmc registers and bits for DC Balance
-:25: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-authored-by:
#25: 
Co-authored-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

total: 0 errors, 1 warnings, 0 checks, 55 lines checked
fad6a8f79ede drm/i915/display: Add VRR DC balance registers
4566a559ce73 drm/i915/vrr: Add functions to read out vmin/vmax stuff
348d5dec3a32 drm/i915/vrr: Add DC Balance params to crtc_state
f9014d5426d0 drm/i915/vrr: Add state dump for DC Balance params
93f42d962c67 drm/i915/vrr: Add compute config for DC Balance params
46d909ba4d17 drm/i915/vrr: Write DC balance params to hw registers
21ab1f87cbe8 drm/i915: Extract vrr_vblank_start()
f7ca6359b427 drm/i915/vrr: Implement vblank evasion with DC balancing
d28f0ebc72fc drm/i915/dsb: Add pipedmc dc balance enable/disable
-:49: CHECK:LINE_SPACING: Please don't use multiple blank lines
#49: FILE: drivers/gpu/drm/i915/display/intel_dmc.h:11:
 
+

total: 0 errors, 0 warnings, 1 checks, 42 lines checked
0ea9b21246ab drm/i915/vrr: Restructure VRR enablement bit
2725e846662f drm/i915/vrr: Pause DC Balancing for DSB commits
1772e7183319 drm/i915/vrr: Add function to check if DC Balance Possible
841802d1c29f drm/i915/display: Add function to configure PIPEDMC_EVT_CTL
cb0b86009ef2 drm/i915/vrr: Enable Adaptive sync counter bit
a2dc34c14d03 drm/i915/vrr: Enable DC Balance

✓ CI.KUnit: success for Enable/Disable DC balance along with VRR DSB (rev8)

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev8)
URL   : https://patchwork.freedesktop.org/series/148025/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:50:38] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:50:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:51:10] Starting KUnit Kernel (1/1)...
[10:51:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:51:10] ================== guc_buf (11 subtests) ===================
[10:51:10] [PASSED] test_smallest
[10:51:10] [PASSED] test_largest
[10:51:10] [PASSED] test_granular
[10:51:10] [PASSED] test_unique
[10:51:10] [PASSED] test_overlap
[10:51:10] [PASSED] test_reusable
[10:51:10] [PASSED] test_too_big
[10:51:10] [PASSED] test_flush
[10:51:10] [PASSED] test_lookup
[10:51:10] [PASSED] test_data
[10:51:10] [PASSED] test_class
[10:51:10] ===================== [PASSED] guc_buf =====================
[10:51:10] =================== guc_dbm (7 subtests) ===================
[10:51:10] [PASSED] test_empty
[10:51:10] [PASSED] test_default
[10:51:10] ======================== test_size  ========================
[10:51:10] [PASSED] 4
[10:51:10] [PASSED] 8
[10:51:10] [PASSED] 32
[10:51:10] [PASSED] 256
[10:51:10] ==================== [PASSED] test_size ====================
[10:51:10] ======================= test_reuse  ========================
[10:51:10] [PASSED] 4
[10:51:10] [PASSED] 8
[10:51:10] [PASSED] 32
[10:51:10] [PASSED] 256
[10:51:10] =================== [PASSED] test_reuse ====================
[10:51:10] =================== test_range_overlap  ====================
[10:51:10] [PASSED] 4
[10:51:10] [PASSED] 8
[10:51:10] [PASSED] 32
[10:51:10] [PASSED] 256
[10:51:10] =============== [PASSED] test_range_overlap ================
[10:51:10] =================== test_range_compact  ====================
[10:51:10] [PASSED] 4
[10:51:10] [PASSED] 8
[10:51:10] [PASSED] 32
[10:51:10] [PASSED] 256
[10:51:10] =============== [PASSED] test_range_compact ================
[10:51:10] ==================== test_range_spare  =====================
[10:51:10] [PASSED] 4
[10:51:10] [PASSED] 8
[10:51:10] [PASSED] 32
[10:51:10] [PASSED] 256
[10:51:10] ================ [PASSED] test_range_spare =================
[10:51:10] ===================== [PASSED] guc_dbm =====================
[10:51:10] =================== guc_idm (6 subtests) ===================
[10:51:10] [PASSED] bad_init
[10:51:10] [PASSED] no_init
[10:51:10] [PASSED] init_fini
[10:51:10] [PASSED] check_used
[10:51:10] [PASSED] check_quota
[10:51:10] [PASSED] check_all
[10:51:10] ===================== [PASSED] guc_idm =====================
[10:51:10] ================== no_relay (3 subtests) ===================
[10:51:10] [PASSED] xe_drops_guc2pf_if_not_ready
[10:51:10] [PASSED] xe_drops_guc2vf_if_not_ready
[10:51:10] [PASSED] xe_rejects_send_if_not_ready
[10:51:10] ==================== [PASSED] no_relay =====================
[10:51:10] ================== pf_relay (14 subtests) ==================
[10:51:10] [PASSED] pf_rejects_guc2pf_too_short
[10:51:10] [PASSED] pf_rejects_guc2pf_too_long
[10:51:10] [PASSED] pf_rejects_guc2pf_no_payload
[10:51:10] [PASSED] pf_fails_no_payload
[10:51:10] [PASSED] pf_fails_bad_origin
[10:51:10] [PASSED] pf_fails_bad_type
[10:51:10] [PASSED] pf_txn_reports_error
[10:51:10] [PASSED] pf_txn_sends_pf2guc
[10:51:10] [PASSED] pf_sends_pf2guc
[10:51:10] [SKIPPED] pf_loopback_nop
[10:51:10] [SKIPPED] pf_loopback_echo
[10:51:10] [SKIPPED] pf_loopback_fail
[10:51:10] [SKIPPED] pf_loopback_busy
[10:51:10] [SKIPPED] pf_loopback_retry
[10:51:10] ==================== [PASSED] pf_relay =====================
[10:51:10] ================== vf_relay (3 subtests) ===================
[10:51:10] [PASSED] vf_rejects_guc2vf_too_short
[10:51:10] [PASSED] vf_rejects_guc2vf_too_long
[10:51:10] [PASSED] vf_rejects_guc2vf_no_payload
[10:51:10] ==================== [PASSED] vf_relay =====================
[10:51:10] ================= pf_service (11 subtests) =================
[10:51:10] [PASSED] pf_negotiate_any
[10:51:10] [PASSED] pf_negotiate_base_match
[10:51:10] [PASSED] pf_negotiate_base_newer
[10:51:10] [PASSED] pf_negotiate_base_next
[10:51:10] [SKIPPED] pf_negotiate_base_older
[10:51:10] [PASSED] pf_negotiate_base_prev
[10:51:10] [PASSED] pf_negotiate_latest_match
[10:51:10] [PASSED] pf_negotiate_latest_newer
[10:51:10] [PASSED] pf_negotiate_latest_next
[10:51:10] [SKIPPED] pf_negotiate_latest_older
[10:51:10] [SKIPPED] pf_negotiate_latest_prev
[10:51:10] =================== [PASSED] pf_service ====================
[10:51:10] ===================== lmtt (1 subtest) =====================
[10:51:10] ======================== test_ops  =========================
[10:51:10] [PASSED] 2-level
[10:51:10] [PASSED] multi-level
[10:51:10] ==================== [PASSED] test_ops =====================
[10:51:10] ====================== [PASSED] lmtt =======================
[10:51:10] =================== xe_mocs (2 subtests) ===================
[10:51:10] ================ xe_live_mocs_kernel_kunit  ================
[10:51:10] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:51:10] ================ xe_live_mocs_reset_kunit  =================
[10:51:10] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:51:10] ==================== [SKIPPED] xe_mocs =====================
[10:51:10] ================= xe_migrate (2 subtests) ==================
[10:51:10] ================= xe_migrate_sanity_kunit  =================
[10:51:10] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:51:10] ================== xe_validate_ccs_kunit  ==================
[10:51:10] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:51:10] =================== [SKIPPED] xe_migrate ===================
[10:51:10] ================== xe_dma_buf (1 subtest) ==================
[10:51:10] ==================== xe_dma_buf_kunit  =====================
[10:51:10] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:51:10] =================== [SKIPPED] xe_dma_buf ===================
[10:51:10] ================= xe_bo_shrink (1 subtest) =================
[10:51:10] =================== xe_bo_shrink_kunit  ====================
[10:51:10] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:51:10] ================== [SKIPPED] xe_bo_shrink ==================
[10:51:10] ==================== xe_bo (2 subtests) ====================
[10:51:10] ================== xe_ccs_migrate_kunit  ===================
[10:51:10] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:51:10] ==================== xe_bo_evict_kunit  ====================
[10:51:10] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:51:10] ===================== [SKIPPED] xe_bo ======================
[10:51:10] ==================== args (11 subtests) ====================
[10:51:10] [PASSED] count_args_test
[10:51:10] [PASSED] call_args_example
[10:51:10] [PASSED] call_args_test
[10:51:10] [PASSED] drop_first_arg_example
[10:51:10] [PASSED] drop_first_arg_test
[10:51:10] [PASSED] first_arg_example
[10:51:10] [PASSED] first_arg_test
[10:51:10] [PASSED] last_arg_example
[10:51:10] [PASSED] last_arg_test
[10:51:10] [PASSED] pick_arg_example
[10:51:10] [PASSED] sep_comma_example
[10:51:10] ====================== [PASSED] args =======================
[10:51:10] =================== xe_pci (2 subtests) ====================
[10:51:10] ==================== check_graphics_ip  ====================
[10:51:10] [PASSED] 12.70 Xe_LPG
[10:51:10] [PASSED] 12.71 Xe_LPG
[10:51:10] [PASSED] 12.74 Xe_LPG+
[10:51:10] [PASSED] 20.01 Xe2_HPG
[10:51:10] [PASSED] 20.02 Xe2_HPG
[10:51:10] [PASSED] 20.04 Xe2_LPG
[10:51:10] [PASSED] 30.00 Xe3_LPG
[10:51:10] [PASSED] 30.01 Xe3_LPG
[10:51:10] [PASSED] 30.03 Xe3_LPG
[10:51:10] ================ [PASSED] check_graphics_ip ================
[10:51:10] ===================== check_media_ip  ======================
[10:51:10] [PASSED] 13.00 Xe_LPM+
[10:51:10] [PASSED] 13.01 Xe2_HPM
[10:51:10] [PASSED] 20.00 Xe2_LPM
[10:51:10] [PASSED] 30.00 Xe3_LPM
[10:51:10] [PASSED] 30.02 Xe3_LPM
stty: 'standard input': Inappropriate ioctl for device
[10:51:10] ================= [PASSED] check_media_ip ==================
[10:51:10] ===================== [PASSED] xe_pci ======================
[10:51:10] =================== xe_rtp (2 subtests) ====================
[10:51:10] =============== xe_rtp_process_to_sr_tests  ================
[10:51:10] [PASSED] coalesce-same-reg
[10:51:10] [PASSED] no-match-no-add
[10:51:10] [PASSED] match-or
[10:51:10] [PASSED] match-or-xfail
[10:51:10] [PASSED] no-match-no-add-multiple-rules
[10:51:10] [PASSED] two-regs-two-entries
[10:51:10] [PASSED] clr-one-set-other
[10:51:10] [PASSED] set-field
[10:51:10] [PASSED] conflict-duplicate
[10:51:10] [PASSED] conflict-not-disjoint
[10:51:10] [PASSED] conflict-reg-type
[10:51:10] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:51:10] ================== xe_rtp_process_tests  ===================
[10:51:10] [PASSED] active1
[10:51:10] [PASSED] active2
[10:51:10] [PASSED] active-inactive
[10:51:10] [PASSED] inactive-active
[10:51:10] [PASSED] inactive-1st_or_active-inactive
[10:51:10] [PASSED] inactive-2nd_or_active-inactive
[10:51:10] [PASSED] inactive-last_or_active-inactive
[10:51:10] [PASSED] inactive-no_or_active-inactive
[10:51:10] ============== [PASSED] xe_rtp_process_tests ===============
[10:51:10] ===================== [PASSED] xe_rtp ======================
[10:51:10] ==================== xe_wa (1 subtest) =====================
[10:51:10] ======================== xe_wa_gt  =========================
[10:51:10] [PASSED] TIGERLAKE (B0)
[10:51:10] [PASSED] DG1 (A0)
[10:51:10] [PASSED] DG1 (B0)
[10:51:10] [PASSED] ALDERLAKE_S (A0)
[10:51:10] [PASSED] ALDERLAKE_S (B0)
[10:51:10] [PASSED] ALDERLAKE_S (C0)
[10:51:10] [PASSED] ALDERLAKE_S (D0)
[10:51:10] [PASSED] ALDERLAKE_P (A0)
[10:51:10] [PASSED] ALDERLAKE_P (B0)
[10:51:10] [PASSED] ALDERLAKE_P (C0)
[10:51:10] [PASSED] ALDERLAKE_S_RPLS (D0)
[10:51:10] [PASSED] ALDERLAKE_P_RPLU (E0)
[10:51:10] [PASSED] DG2_G10 (C0)
[10:51:10] [PASSED] DG2_G11 (B1)
[10:51:10] [PASSED] DG2_G12 (A1)
[10:51:10] [PASSED] METEORLAKE (g:A0, m:A0)
[10:51:10] [PASSED] METEORLAKE (g:A0, m:A0)
[10:51:10] [PASSED] METEORLAKE (g:A0, m:A0)
[10:51:10] [PASSED] LUNARLAKE (g:A0, m:A0)
[10:51:10] [PASSED] LUNARLAKE (g:B0, m:A0)
[10:51:10] [PASSED] BATTLEMAGE (g:A0, m:A1)
[10:51:10] ==================== [PASSED] xe_wa_gt =====================
[10:51:10] ====================== [PASSED] xe_wa ======================
[10:51:10] ============================================================
[10:51:10] Testing complete. Ran 145 tests: passed: 129, skipped: 16
[10:51:10] Elapsed time: 31.649s total, 4.186s configuring, 27.197s building, 0.245s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:51:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:51:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:51:33] Starting KUnit Kernel (1/1)...
[10:51:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:51:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:51:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:51:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:51:33] =========== drm_validate_clone_mode (2 subtests) ===========
[10:51:33] ============== drm_test_check_in_clone_mode  ===============
[10:51:33] [PASSED] in_clone_mode
[10:51:33] [PASSED] not_in_clone_mode
[10:51:33] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:51:33] =============== drm_test_check_valid_clones  ===============
[10:51:33] [PASSED] not_in_clone_mode
[10:51:33] [PASSED] valid_clone
[10:51:33] [PASSED] invalid_clone
[10:51:33] =========== [PASSED] drm_test_check_valid_clones ===========
[10:51:33] ============= [PASSED] drm_validate_clone_mode =============
[10:51:33] ============= drm_validate_modeset (1 subtest) =============
[10:51:33] [PASSED] drm_test_check_connector_changed_modeset
[10:51:33] ============== [PASSED] drm_validate_modeset ===============
[10:51:33] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:51:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:51:33] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:51:33] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:51:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:51:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:51:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:51:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:51:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:51:33] ============== drm_bridge_alloc (2 subtests) ===============
[10:51:33] [PASSED] drm_test_drm_bridge_alloc_basic
[10:51:33] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:51:33] ================ [PASSED] drm_bridge_alloc =================
[10:51:33] ================== drm_buddy (7 subtests) ==================
[10:51:33] [PASSED] drm_test_buddy_alloc_limit
[10:51:33] [PASSED] drm_test_buddy_alloc_optimistic
[10:51:33] [PASSED] drm_test_buddy_alloc_pessimistic
[10:51:33] [PASSED] drm_test_buddy_alloc_pathological
[10:51:33] [PASSED] drm_test_buddy_alloc_contiguous
[10:51:33] [PASSED] drm_test_buddy_alloc_clear
[10:51:33] [PASSED] drm_test_buddy_alloc_range_bias
[10:51:33] ==================== [PASSED] drm_buddy ====================
[10:51:33] ============= drm_cmdline_parser (40 subtests) =============
[10:51:33] [PASSED] drm_test_cmdline_force_d_only
[10:51:33] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:51:33] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:51:33] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:51:33] [PASSED] drm_test_cmdline_force_e_only
[10:51:33] [PASSED] drm_test_cmdline_res
[10:51:33] [PASSED] drm_test_cmdline_res_vesa
[10:51:33] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:51:33] [PASSED] drm_test_cmdline_res_rblank
[10:51:33] [PASSED] drm_test_cmdline_res_bpp
[10:51:33] [PASSED] drm_test_cmdline_res_refresh
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:51:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:51:33] [PASSED] drm_test_cmdline_res_margins_force_on
[10:51:33] [PASSED] drm_test_cmdline_res_vesa_margins
[10:51:33] [PASSED] drm_test_cmdline_name
[10:51:33] [PASSED] drm_test_cmdline_name_bpp
[10:51:33] [PASSED] drm_test_cmdline_name_option
[10:51:33] [PASSED] drm_test_cmdline_name_bpp_option
[10:51:33] [PASSED] drm_test_cmdline_rotate_0
[10:51:33] [PASSED] drm_test_cmdline_rotate_90
[10:51:33] [PASSED] drm_test_cmdline_rotate_180
[10:51:33] [PASSED] drm_test_cmdline_rotate_270
[10:51:33] [PASSED] drm_test_cmdline_hmirror
[10:51:33] [PASSED] drm_test_cmdline_vmirror
[10:51:33] [PASSED] drm_test_cmdline_margin_options
[10:51:33] [PASSED] drm_test_cmdline_multiple_options
[10:51:33] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:51:33] [PASSED] drm_test_cmdline_extra_and_option
[10:51:33] [PASSED] drm_test_cmdline_freestanding_options
[10:51:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:51:33] [PASSED] drm_test_cmdline_panel_orientation
[10:51:33] ================ drm_test_cmdline_invalid  =================
[10:51:33] [PASSED] margin_only
[10:51:33] [PASSED] interlace_only
[10:51:33] [PASSED] res_missing_x
[10:51:33] [PASSED] res_missing_y
[10:51:33] [PASSED] res_bad_y
[10:51:33] [PASSED] res_missing_y_bpp
[10:51:33] [PASSED] res_bad_bpp
[10:51:33] [PASSED] res_bad_refresh
[10:51:33] [PASSED] res_bpp_refresh_force_on_off
[10:51:33] [PASSED] res_invalid_mode
[10:51:33] [PASSED] res_bpp_wrong_place_mode
[10:51:33] [PASSED] name_bpp_refresh
[10:51:33] [PASSED] name_refresh
[10:51:33] [PASSED] name_refresh_wrong_mode
[10:51:33] [PASSED] name_refresh_invalid_mode
[10:51:33] [PASSED] rotate_multiple
[10:51:33] [PASSED] rotate_invalid_val
[10:51:33] [PASSED] rotate_truncated
[10:51:33] [PASSED] invalid_option
[10:51:33] [PASSED] invalid_tv_option
[10:51:33] [PASSED] truncated_tv_option
[10:51:33] ============ [PASSED] drm_test_cmdline_invalid =============
[10:51:33] =============== drm_test_cmdline_tv_options  ===============
[10:51:33] [PASSED] NTSC
[10:51:33] [PASSED] NTSC_443
[10:51:33] [PASSED] NTSC_J
[10:51:33] [PASSED] PAL
[10:51:33] [PASSED] PAL_M
[10:51:33] [PASSED] PAL_N
[10:51:33] [PASSED] SECAM
[10:51:33] [PASSED] MONO_525
[10:51:33] [PASSED] MONO_625
[10:51:33] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:51:33] =============== [PASSED] drm_cmdline_parser ================
[10:51:33] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:51:33] [PASSED] drm_test_connector_hdmi_init_valid
[10:51:33] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:51:33] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:51:33] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:51:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:51:33] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:51:33] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:51:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:51:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:51:33] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:51:33] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:51:33] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:51:33] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:51:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:51:33] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:51:33] [PASSED] drm_test_connector_hdmi_init_null_product
[10:51:33] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:51:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:51:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:51:33] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:51:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:51:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:51:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:51:33] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:51:33] [PASSED] HDMI-A
[10:51:33] [PASSED] HDMI-B
[10:51:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:51:33] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:51:33] [PASSED] Unknown
[10:51:33] [PASSED] VGA
[10:51:33] [PASSED] DVI-I
[10:51:33] [PASSED] DVI-D
[10:51:33] [PASSED] DVI-A
[10:51:33] [PASSED] Composite
[10:51:33] [PASSED] SVIDEO
[10:51:33] [PASSED] LVDS
[10:51:33] [PASSED] Component
[10:51:33] [PASSED] DIN
[10:51:33] [PASSED] DP
[10:51:33] [PASSED] TV
[10:51:33] [PASSED] eDP
[10:51:33] [PASSED] Virtual
[10:51:33] [PASSED] DSI
[10:51:33] [PASSED] DPI
[10:51:33] [PASSED] Writeback
[10:51:33] [PASSED] SPI
[10:51:33] [PASSED] USB
[10:51:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:51:33] ============ [PASSED] drmm_connector_hdmi_init =============
[10:51:33] ============= drmm_connector_init (3 subtests) =============
[10:51:33] [PASSED] drm_test_drmm_connector_init
[10:51:33] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:51:33] ========= drm_test_drmm_connector_init_type_valid  =========
[10:51:33] [PASSED] Unknown
[10:51:33] [PASSED] VGA
[10:51:33] [PASSED] DVI-I
[10:51:33] [PASSED] DVI-D
[10:51:33] [PASSED] DVI-A
[10:51:33] [PASSED] Composite
[10:51:33] [PASSED] SVIDEO
[10:51:33] [PASSED] LVDS
[10:51:33] [PASSED] Component
[10:51:33] [PASSED] DIN
[10:51:33] [PASSED] DP
[10:51:33] [PASSED] HDMI-A
[10:51:33] [PASSED] HDMI-B
[10:51:33] [PASSED] TV
[10:51:33] [PASSED] eDP
[10:51:33] [PASSED] Virtual
[10:51:33] [PASSED] DSI
[10:51:33] [PASSED] DPI
[10:51:33] [PASSED] Writeback
[10:51:33] [PASSED] SPI
[10:51:33] [PASSED] USB
[10:51:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:51:33] =============== [PASSED] drmm_connector_init ===============
[10:51:33] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_init
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:51:33] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:51:33] [PASSED] Unknown
[10:51:33] [PASSED] VGA
[10:51:33] [PASSED] DVI-I
[10:51:33] [PASSED] DVI-D
[10:51:33] [PASSED] DVI-A
[10:51:33] [PASSED] Composite
[10:51:33] [PASSED] SVIDEO
[10:51:33] [PASSED] LVDS
[10:51:33] [PASSED] Component
[10:51:33] [PASSED] DIN
[10:51:33] [PASSED] DP
[10:51:33] [PASSED] HDMI-A
[10:51:33] [PASSED] HDMI-B
[10:51:33] [PASSED] TV
[10:51:33] [PASSED] eDP
[10:51:33] [PASSED] Virtual
[10:51:33] [PASSED] DSI
[10:51:33] [PASSED] DPI
[10:51:33] [PASSED] Writeback
[10:51:33] [PASSED] SPI
[10:51:33] [PASSED] USB
[10:51:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:51:33] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:51:33] [PASSED] Unknown
[10:51:33] [PASSED] VGA
[10:51:33] [PASSED] DVI-I
[10:51:33] [PASSED] DVI-D
[10:51:33] [PASSED] DVI-A
[10:51:33] [PASSED] Composite
[10:51:33] [PASSED] SVIDEO
[10:51:33] [PASSED] LVDS
[10:51:33] [PASSED] Component
[10:51:33] [PASSED] DIN
[10:51:33] [PASSED] DP
[10:51:33] [PASSED] HDMI-A
[10:51:33] [PASSED] HDMI-B
[10:51:33] [PASSED] TV
[10:51:33] [PASSED] eDP
[10:51:33] [PASSED] Virtual
[10:51:33] [PASSED] DSI
[10:51:33] [PASSED] DPI
[10:51:33] [PASSED] Writeback
[10:51:33] [PASSED] SPI
[10:51:33] [PASSED] USB
[10:51:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:51:33] =========== [PASSED] drm_connector_dynamic_init ============
[10:51:33] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:51:33] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:51:33] ======= drm_connector_dynamic_register (7 subtests) ========
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:51:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:51:33] ========= [PASSED] drm_connector_dynamic_register ==========
[10:51:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:51:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:51:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:51:33] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:51:33] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:51:33] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:51:33] [PASSED] NTSC
[10:51:33] [PASSED] NTSC-443
[10:51:33] [PASSED] NTSC-J
[10:51:33] [PASSED] PAL
[10:51:33] [PASSED] PAL-M
[10:51:33] [PASSED] PAL-N
[10:51:33] [PASSED] SECAM
[10:51:33] [PASSED] Mono
[10:51:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:51:33] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:51:33] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:51:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:51:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:51:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:51:33] [PASSED] VIC 96
[10:51:33] [PASSED] VIC 97
[10:51:33] [PASSED] VIC 101
[10:51:33] [PASSED] VIC 102
[10:51:33] [PASSED] VIC 106
[10:51:33] [PASSED] VIC 107
[10:51:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:51:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:51:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:51:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:51:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:51:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:51:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:51:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:51:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:51:33] [PASSED] Automatic
[10:51:33] [PASSED] Full
[10:51:33] [PASSED] Limited 16:235
[10:51:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:51:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:51:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:51:33] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:51:33] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:51:33] [PASSED] RGB
[10:51:33] [PASSED] YUV 4:2:0
[10:51:33] [PASSED] YUV 4:2:2
[10:51:33] [PASSED] YUV 4:4:4
[10:51:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:51:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:51:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:51:33] ============= drm_damage_helper (21 subtests) ==============
[10:51:33] [PASSED] drm_test_damage_iter_no_damage
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:51:33] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:51:33] [PASSED] drm_test_damage_iter_simple_damage
[10:51:33] [PASSED] drm_test_damage_iter_single_damage
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:51:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:51:33] [PASSED] drm_test_damage_iter_damage
[10:51:33] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:51:33] [PASSED] drm_test_damage_iter_damage_one_outside
[10:51:33] [PASSED] drm_test_damage_iter_damage_src_moved
[10:51:33] [PASSED] drm_test_damage_iter_damage_not_visible
[10:51:33] ================ [PASSED] drm_damage_helper ================
[10:51:33] ============== drm_dp_mst_helper (3 subtests) ==============
[10:51:33] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:51:33] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:51:33] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:51:33] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:51:33] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:51:33] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:51:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:51:33] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:51:33] [PASSED] Link rate 2000000 lane count 4
[10:51:33] [PASSED] Link rate 2000000 lane count 2
[10:51:33] [PASSED] Link rate 2000000 lane count 1
[10:51:33] [PASSED] Link rate 1350000 lane count 4
[10:51:33] [PASSED] Link rate 1350000 lane count 2
[10:51:33] [PASSED] Link rate 1350000 lane count 1
[10:51:33] [PASSED] Link rate 1000000 lane count 4
[10:51:33] [PASSED] Link rate 1000000 lane count 2
[10:51:33] [PASSED] Link rate 1000000 lane count 1
[10:51:33] [PASSED] Link rate 810000 lane count 4
[10:51:33] [PASSED] Link rate 810000 lane count 2
[10:51:33] [PASSED] Link rate 810000 lane count 1
[10:51:33] [PASSED] Link rate 540000 lane count 4
[10:51:33] [PASSED] Link rate 540000 lane count 2
[10:51:33] [PASSED] Link rate 540000 lane count 1
[10:51:33] [PASSED] Link rate 270000 lane count 4
[10:51:33] [PASSED] Link rate 270000 lane count 2
[10:51:33] [PASSED] Link rate 270000 lane count 1
[10:51:33] [PASSED] Link rate 162000 lane count 4
[10:51:33] [PASSED] Link rate 162000 lane count 2
[10:51:33] [PASSED] Link rate 162000 lane count 1
[10:51:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:51:33] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:51:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:51:33] [PASSED] DP_POWER_UP_PHY with port number
[10:51:33] [PASSED] DP_POWER_DOWN_PHY with port number
[10:51:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:51:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:51:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:51:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:51:33] [PASSED] DP_QUERY_PAYLOAD with port number
[10:51:33] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:51:33] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:51:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:51:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:51:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:51:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:51:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:51:33] [PASSED] DP_REMOTE_I2C_READ with port number
[10:51:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:51:33] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:51:33] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:51:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:51:33] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:51:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:51:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:51:33] ================ [PASSED] drm_dp_mst_helper ================
[10:51:33] ================== drm_exec (7 subtests) ===================
[10:51:33] [PASSED] sanitycheck
[10:51:33] [PASSED] test_lock
[10:51:33] [PASSED] test_lock_unlock
[10:51:33] [PASSED] test_duplicates
[10:51:33] [PASSED] test_prepare
[10:51:33] [PASSED] test_prepare_array
[10:51:33] [PASSED] test_multiple_loops
[10:51:33] ==================== [PASSED] drm_exec =====================
[10:51:33] =========== drm_format_helper_test (17 subtests) ===========
[10:51:33] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:51:33] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:51:33] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:51:33] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:51:33] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:51:33] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:51:33] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:51:33] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:51:33] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:51:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:51:33] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:51:33] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:51:33] ==================== drm_test_fb_swab  =====================
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ================ [PASSED] drm_test_fb_swab =================
[10:51:33] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:51:33] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:51:33] [PASSED] single_pixel_source_buffer
[10:51:33] [PASSED] single_pixel_clip_rectangle
[10:51:33] [PASSED] well_known_colors
[10:51:33] [PASSED] destination_pitch
[10:51:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:51:33] ================= drm_test_fb_clip_offset  =================
[10:51:33] [PASSED] pass through
[10:51:33] [PASSED] horizontal offset
[10:51:33] [PASSED] vertical offset
[10:51:33] [PASSED] horizontal and vertical offset
[10:51:33] [PASSED] horizontal offset (custom pitch)
[10:51:33] [PASSED] vertical offset (custom pitch)
[10:51:33] [PASSED] horizontal and vertical offset (custom pitch)
[10:51:33] ============= [PASSED] drm_test_fb_clip_offset =============
[10:51:33] =================== drm_test_fb_memcpy  ====================
[10:51:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:51:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:51:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:51:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:51:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:51:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:51:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:51:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:51:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:51:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:51:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:51:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:51:33] =============== [PASSED] drm_test_fb_memcpy ================
[10:51:33] ============= [PASSED] drm_format_helper_test ==============
[10:51:33] ================= drm_format (18 subtests) =================
[10:51:33] [PASSED] drm_test_format_block_width_invalid
[10:51:33] [PASSED] drm_test_format_block_width_one_plane
[10:51:33] [PASSED] drm_test_format_block_width_two_plane
[10:51:33] [PASSED] drm_test_format_block_width_three_plane
[10:51:33] [PASSED] drm_test_format_block_width_tiled
[10:51:33] [PASSED] drm_test_format_block_height_invalid
[10:51:33] [PASSED] drm_test_format_block_height_one_plane
[10:51:33] [PASSED] drm_test_format_block_height_two_plane
[10:51:33] [PASSED] drm_test_format_block_height_three_plane
[10:51:33] [PASSED] drm_test_format_block_height_tiled
[10:51:33] [PASSED] drm_test_format_min_pitch_invalid
[10:51:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:51:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:51:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:51:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:51:33] [PASSED] drm_test_format_min_pitch_two_plane
[10:51:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:51:33] [PASSED] drm_test_format_min_pitch_tiled
[10:51:33] =================== [PASSED] drm_format ====================
[10:51:33] ============== drm_framebuffer (10 subtests) ===============
[10:51:33] ========== drm_test_framebuffer_check_src_coords  ==========
[10:51:33] [PASSED] Success: source fits into fb
[10:51:33] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:51:33] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:51:33] [PASSED] Fail: overflowing fb with source width
[10:51:33] [PASSED] Fail: overflowing fb with source height
[10:51:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:51:33] [PASSED] drm_test_framebuffer_cleanup
[10:51:33] =============== drm_test_framebuffer_create  ===============
[10:51:33] [PASSED] ABGR8888 normal sizes
[10:51:33] [PASSED] ABGR8888 max sizes
[10:51:33] [PASSED] ABGR8888 pitch greater than min required
[10:51:33] [PASSED] ABGR8888 pitch less than min required
[10:51:33] [PASSED] ABGR8888 Invalid width
[10:51:33] [PASSED] ABGR8888 Invalid buffer handle
[10:51:33] [PASSED] No pixel format
[10:51:33] [PASSED] ABGR8888 Width 0
[10:51:33] [PASSED] ABGR8888 Height 0
[10:51:33] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:51:33] [PASSED] ABGR8888 Large buffer offset
[10:51:33] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:51:33] [PASSED] ABGR8888 Invalid flag
[10:51:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:51:33] [PASSED] ABGR8888 Valid buffer modifier
[10:51:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:51:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] NV12 Normal sizes
[10:51:33] [PASSED] NV12 Max sizes
[10:51:33] [PASSED] NV12 Invalid pitch
[10:51:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:51:33] [PASSED] NV12 different  modifier per-plane
[10:51:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:51:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] NV12 Modifier for inexistent plane
[10:51:33] [PASSED] NV12 Handle for inexistent plane
[10:51:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:51:33] [PASSED] YVU420 Normal sizes
[10:51:33] [PASSED] YVU420 Max sizes
[10:51:33] [PASSED] YVU420 Invalid pitch
[10:51:33] [PASSED] YVU420 Different pitches
[10:51:33] [PASSED] YVU420 Different buffer offsets/pitches
[10:51:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:51:33] [PASSED] YVU420 Valid modifier
[10:51:33] [PASSED] YVU420 Different modifiers per plane
[10:51:33] [PASSED] YVU420 Modifier for inexistent plane
[10:51:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:51:33] [PASSED] X0L2 Normal sizes
[10:51:33] [PASSED] X0L2 Max sizes
[10:51:33] [PASSED] X0L2 Invalid pitch
[10:51:33] [PASSED] X0L2 Pitch greater than minimum required
[10:51:33] [PASSED] X0L2 Handle for inexistent plane
[10:51:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:51:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:51:33] [PASSED] X0L2 Valid modifier
[10:51:33] [PASSED] X0L2 Modifier for inexistent plane
[10:51:33] =========== [PASSED] drm_test_framebuffer_create ===========
[10:51:33] [PASSED] drm_test_framebuffer_free
[10:51:33] [PASSED] drm_test_framebuffer_init
[10:51:33] [PASSED] drm_test_framebuffer_init_bad_format
[10:51:33] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:51:33] [PASSED] drm_test_framebuffer_lookup
[10:51:33] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:51:33] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:51:33] ================= [PASSED] drm_framebuffer =================
[10:51:33] ================ drm_gem_shmem (8 subtests) ================
[10:51:33] [PASSED] drm_gem_shmem_test_obj_create
[10:51:33] [PASSED] drm_gem_shmem_test_obj_create_private
[10:51:33] [PASSED] drm_gem_shmem_test_pin_pages
[10:51:33] [PASSED] drm_gem_shmem_test_vmap
[10:51:33] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:51:33] [PASSED] drm_gem_shmem_test_get_sg_table
[10:51:33] [PASSED] drm_gem_shmem_test_madvise
[10:51:33] [PASSED] drm_gem_shmem_test_purge
[10:51:33] ================== [PASSED] drm_gem_shmem ==================
[10:51:33] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:51:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:51:33] [PASSED] Automatic
[10:51:33] [PASSED] Full
[10:51:33] [PASSED] Limited 16:235
[10:51:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:51:33] [PASSED] drm_test_check_disable_connector
[10:51:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:51:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:51:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:51:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:51:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:51:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:51:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:51:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:51:33] [PASSED] drm_test_check_output_bpc_dvi
[10:51:33] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:51:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:51:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:51:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:51:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:51:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:51:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:51:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:51:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:51:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:51:33] [PASSED] drm_test_check_broadcast_rgb_value
[10:51:33] [PASSED] drm_test_check_bpc_8_value
[10:51:33] [PASSED] drm_test_check_bpc_10_value
[10:51:33] [PASSED] drm_test_check_bpc_12_value
[10:51:33] [PASSED] drm_test_check_format_value
[10:51:33] [PASSED] drm_test_check_tmds_char_value
[10:51:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:51:33] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:51:33] [PASSED] drm_test_check_mode_valid
[10:51:33] [PASSED] drm_test_check_mode_valid_reject
[10:51:33] [PASSED] drm_test_check_mode_valid_reject_rate
[10:51:33] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:51:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:51:33] ================= drm_managed (2 subtests) =================
[10:51:33] [PASSED] drm_test_managed_release_action
[10:51:33] [PASSED] drm_test_managed_run_action
[10:51:33] =================== [PASSED] drm_managed ===================
[10:51:33] =================== drm_mm (6 subtests) ====================
[10:51:33] [PASSED] drm_test_mm_init
[10:51:33] [PASSED] drm_test_mm_debug
[10:51:33] [PASSED] drm_test_mm_align32
[10:51:33] [PASSED] drm_test_mm_align64
[10:51:33] [PASSED] drm_test_mm_lowest
[10:51:33] [PASSED] drm_test_mm_highest
[10:51:33] ===================== [PASSED] drm_mm ======================
[10:51:33] ============= drm_modes_analog_tv (5 subtests) =============
[10:51:33] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:51:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:51:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:51:33] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:51:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:51:33] =============== [PASSED] drm_modes_analog_tv ===============
[10:51:33] ============== drm_plane_helper (2 subtests) ===============
[10:51:33] =============== drm_test_check_plane_state  ================
[10:51:33] [PASSED] clipping_simple
[10:51:33] [PASSED] clipping_rotate_reflect
[10:51:33] [PASSED] positioning_simple
[10:51:33] [PASSED] upscaling
[10:51:33] [PASSED] downscaling
[10:51:33] [PASSED] rounding1
[10:51:33] [PASSED] rounding2
[10:51:33] [PASSED] rounding3
[10:51:33] [PASSED] rounding4
[10:51:33] =========== [PASSED] drm_test_check_plane_state ============
[10:51:33] =========== drm_test_check_invalid_plane_state  ============
[10:51:33] [PASSED] positioning_invalid
[10:51:33] [PASSED] upscaling_invalid
[10:51:33] [PASSED] downscaling_invalid
[10:51:33] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:51:33] ================ [PASSED] drm_plane_helper =================
[10:51:33] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:51:33] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:51:33] [PASSED] None
[10:51:33] [PASSED] PAL
[10:51:33] [PASSED] NTSC
[10:51:33] [PASSED] Both, NTSC Default
[10:51:33] [PASSED] Both, PAL Default
[10:51:33] [PASSED] Both, NTSC Default, with PAL on command-line
[10:51:33] [PASSED] Both, PAL Default, with NTSC on command-line
[10:51:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:51:33] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:51:33] ================== drm_rect (9 subtests) ===================
[10:51:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:51:33] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:51:33] [PASSED] drm_test_rect_clip_scaled_clipped
[10:51:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:51:33] ================= drm_test_rect_intersect  =================
[10:51:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:51:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:51:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:51:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:51:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:51:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:51:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:51:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:51:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:51:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:51:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:51:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:51:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:51:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:51:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:51:33] ============= [PASSED] drm_test_rect_intersect =============
[10:51:33] ================ drm_test_rect_calc_hscale  ================
[10:51:33] [PASSED] normal use
[10:51:33] [PASSED] out of max range
[10:51:33] [PASSED] out of min range
[10:51:33] [PASSED] zero dst
[10:51:33] [PASSED] negative src
[10:51:33] [PASSED] negative dst
[10:51:33] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:51:33] ================ drm_test_rect_calc_vscale  ================
[10:51:33] [PASSED] normal use
[10:51:33] [PASSED] out of max range
[10:51:33] [PASSED] out of min range
[10:51:33] [PASSED] zero dst
[10:51:33] [PASSED] negative src
[10:51:33] [PASSED] negative dst
[10:51:33] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:51:33] ================== drm_test_rect_rotate  ===================
[10:51:33] [PASSED] reflect-x
[10:51:33] [PASSED] reflect-y
[10:51:33] [PASSED] rotate-0
[10:51:33] [PASSED] rotate-90
[10:51:33] [PASSED] rotate-180
[10:51:33] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[10:51:33] ============== [PASSED] drm_test_rect_rotate ===============
[10:51:33] ================ drm_test_rect_rotate_inv  =================
[10:51:33] [PASSED] reflect-x
[10:51:33] [PASSED] reflect-y
[10:51:33] [PASSED] rotate-0
[10:51:33] [PASSED] rotate-90
[10:51:33] [PASSED] rotate-180
[10:51:33] [PASSED] rotate-270
[10:51:33] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:51:33] ==================== [PASSED] drm_rect =====================
[10:51:33] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:51:33] ============ drm_test_sysfb_build_fourcc_list  =============
[10:51:33] [PASSED] no native formats
[10:51:33] [PASSED] XRGB8888 as native format
[10:51:33] [PASSED] remove duplicates
[10:51:33] [PASSED] convert alpha formats
[10:51:33] [PASSED] random formats
[10:51:33] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:51:33] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:51:33] ============================================================
[10:51:33] Testing complete. Ran 616 tests: passed: 616
[10:51:33] Elapsed time: 23.444s total, 1.663s configuring, 21.614s building, 0.136s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:51:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:51:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:51:43] Starting KUnit Kernel (1/1)...
[10:51:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:51:43] ================= ttm_device (5 subtests) ==================
[10:51:43] [PASSED] ttm_device_init_basic
[10:51:43] [PASSED] ttm_device_init_multiple
[10:51:43] [PASSED] ttm_device_fini_basic
[10:51:43] [PASSED] ttm_device_init_no_vma_man
[10:51:43] ================== ttm_device_init_pools  ==================
[10:51:43] [PASSED] No DMA allocations, no DMA32 required
[10:51:43] [PASSED] DMA allocations, DMA32 required
[10:51:43] [PASSED] No DMA allocations, DMA32 required
[10:51:43] [PASSED] DMA allocations, no DMA32 required
[10:51:43] ============== [PASSED] ttm_device_init_pools ==============
[10:51:43] =================== [PASSED] ttm_device ====================
[10:51:43] ================== ttm_pool (8 subtests) ===================
[10:51:43] ================== ttm_pool_alloc_basic  ===================
[10:51:43] [PASSED] One page
[10:51:43] [PASSED] More than one page
[10:51:43] [PASSED] Above the allocation limit
[10:51:43] [PASSED] One page, with coherent DMA mappings enabled
[10:51:43] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:51:43] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:51:43] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:51:43] [PASSED] One page
[10:51:43] [PASSED] More than one page
[10:51:43] [PASSED] Above the allocation limit
[10:51:43] [PASSED] One page, with coherent DMA mappings enabled
[10:51:43] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:51:43] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:51:43] [PASSED] ttm_pool_alloc_order_caching_match
[10:51:43] [PASSED] ttm_pool_alloc_caching_mismatch
[10:51:43] [PASSED] ttm_pool_alloc_order_mismatch
[10:51:43] [PASSED] ttm_pool_free_dma_alloc
[10:51:43] [PASSED] ttm_pool_free_no_dma_alloc
[10:51:43] [PASSED] ttm_pool_fini_basic
[10:51:43] ==================== [PASSED] ttm_pool =====================
[10:51:43] ================ ttm_resource (8 subtests) =================
[10:51:43] ================= ttm_resource_init_basic  =================
[10:51:43] [PASSED] Init resource in TTM_PL_SYSTEM
[10:51:43] [PASSED] Init resource in TTM_PL_VRAM
[10:51:43] [PASSED] Init resource in a private placement
[10:51:43] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:51:43] ============= [PASSED] ttm_resource_init_basic =============
[10:51:43] [PASSED] ttm_resource_init_pinned
[10:51:43] [PASSED] ttm_resource_fini_basic
[10:51:43] [PASSED] ttm_resource_manager_init_basic
[10:51:43] [PASSED] ttm_resource_manager_usage_basic
[10:51:43] [PASSED] ttm_resource_manager_set_used_basic
[10:51:43] [PASSED] ttm_sys_man_alloc_basic
[10:51:43] [PASSED] ttm_sys_man_free_basic
[10:51:43] ================== [PASSED] ttm_resource ===================
[10:51:43] =================== ttm_tt (15 subtests) ===================
[10:51:43] ==================== ttm_tt_init_basic  ====================
[10:51:43] [PASSED] Page-aligned size
[10:51:43] [PASSED] Extra pages requested
[10:51:43] ================ [PASSED] ttm_tt_init_basic ================
[10:51:43] [PASSED] ttm_tt_init_misaligned
[10:51:43] [PASSED] ttm_tt_fini_basic
[10:51:43] [PASSED] ttm_tt_fini_sg
[10:51:43] [PASSED] ttm_tt_fini_shmem
[10:51:43] [PASSED] ttm_tt_create_basic
[10:51:43] [PASSED] ttm_tt_create_invalid_bo_type
[10:51:43] [PASSED] ttm_tt_create_ttm_exists
[10:51:43] [PASSED] ttm_tt_create_failed
[10:51:43] [PASSED] ttm_tt_destroy_basic
[10:51:43] [PASSED] ttm_tt_populate_null_ttm
[10:51:43] [PASSED] ttm_tt_populate_populated_ttm
[10:51:43] [PASSED] ttm_tt_unpopulate_basic
[10:51:43] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:51:43] [PASSED] ttm_tt_swapin_basic
[10:51:43] ===================== [PASSED] ttm_tt ======================
[10:51:43] =================== ttm_bo (14 subtests) ===================
[10:51:43] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:51:43] [PASSED] Cannot be interrupted and sleeps
[10:51:43] [PASSED] Cannot be interrupted, locks straight away
[10:51:43] [PASSED] Can be interrupted, sleeps
[10:51:43] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:51:43] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:51:43] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:51:43] [PASSED] ttm_bo_reserve_double_resv
[10:51:43] [PASSED] ttm_bo_reserve_interrupted
[10:51:43] [PASSED] ttm_bo_reserve_deadlock
[10:51:43] [PASSED] ttm_bo_unreserve_basic
[10:51:43] [PASSED] ttm_bo_unreserve_pinned
[10:51:43] [PASSED] ttm_bo_unreserve_bulk
[10:51:43] [PASSED] ttm_bo_put_basic
[10:51:43] [PASSED] ttm_bo_put_shared_resv
[10:51:43] [PASSED] ttm_bo_pin_basic
[10:51:43] [PASSED] ttm_bo_pin_unpin_resource
[10:51:43] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:51:43] ===================== [PASSED] ttm_bo ======================
[10:51:43] ============== ttm_bo_validate (22 subtests) ===============
[10:51:43] ============== ttm_bo_init_reserved_sys_man  ===============
[10:51:43] [PASSED] Buffer object for userspace
[10:51:43] [PASSED] Kernel buffer object
[10:51:43] [PASSED] Shared buffer object
[10:51:43] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:51:43] ============== ttm_bo_init_reserved_mock_man  ==============
[10:51:43] [PASSED] Buffer object for userspace
[10:51:43] [PASSED] Kernel buffer object
[10:51:43] [PASSED] Shared buffer object
[10:51:43] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:51:43] [PASSED] ttm_bo_init_reserved_resv
[10:51:43] ================== ttm_bo_validate_basic  ==================
[10:51:43] [PASSED] Buffer object for userspace
[10:51:43] [PASSED] Kernel buffer object
[10:51:43] [PASSED] Shared buffer object
[10:51:43] ============== [PASSED] ttm_bo_validate_basic ==============
[10:51:43] [PASSED] ttm_bo_validate_invalid_placement
[10:51:43] ============= ttm_bo_validate_same_placement  ==============
[10:51:43] [PASSED] System manager
[10:51:43] [PASSED] VRAM manager
[10:51:43] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:51:43] [PASSED] ttm_bo_validate_failed_alloc
[10:51:43] [PASSED] ttm_bo_validate_pinned
[10:51:43] [PASSED] ttm_bo_validate_busy_placement
[10:51:43] ================ ttm_bo_validate_multihop  =================
[10:51:43] [PASSED] Buffer object for userspace
[10:51:43] [PASSED] Kernel buffer object
[10:51:43] [PASSED] Shared buffer object
[10:51:43] ============ [PASSED] ttm_bo_validate_multihop =============
[10:51:43] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:51:43] [PASSED] Buffer object in system domain, no page vector
[10:51:43] [PASSED] Buffer object in system domain with an existing page vector
[10:51:43] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:51:43] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:51:43] [PASSED] Buffer object for userspace
[10:51:43] [PASSED] Kernel buffer object
[10:51:43] [PASSED] Shared buffer object
[10:51:43] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:51:43] [PASSED] ttm_bo_validate_move_fence_signaled
[10:51:43] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:51:43] [PASSED] Waits for GPU
[10:51:43] [PASSED] Tries to lock straight away
[10:51:44] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:51:44] [PASSED] ttm_bo_validate_swapout
[10:51:44] [PASSED] ttm_bo_validate_happy_evict
[10:51:44] [PASSED] ttm_bo_validate_all_pinned_evict
[10:51:44] [PASSED] ttm_bo_validate_allowed_only_evict
[10:51:44] [PASSED] ttm_bo_validate_deleted_evict
[10:51:44] [PASSED] ttm_bo_validate_busy_domain_evict
[10:51:44] [PASSED] ttm_bo_validate_evict_gutting
[10:51:44] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:51:44] ================= [PASSED] ttm_bo_validate =================
[10:51:44] ============================================================
[10:51:44] Testing complete. Ran 102 tests: passed: 102
[10:51:44] Elapsed time: 10.154s total, 1.675s configuring, 7.812s building, 0.541s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Enable/Disable DC balance along with VRR DSB (rev8)

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev8)
URL   : https://patchwork.freedesktop.org/series/148025/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast fb5dada21e3cfa26179ca58e1d7c26cdad217201
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2002:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2015:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2015:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/i915_irq.c:492:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:492:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:500:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:500:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:505:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:505:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:505:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:543:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:543:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:551:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:551:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:556:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:556:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:556:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:600:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:600:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:603:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:603:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:607:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:607:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:614:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:614:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:614:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:614:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1927:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1995:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2017:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 867 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev8)
URL   : https://patchwork.freedesktop.org/series/148025/
State : success

== Summary ==

CI Bug Log - changes from xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201_BAT -> xe-pw-148025v8_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201 -> xe-pw-148025v8

  IGT_8423: 8423
  xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201: fb5dada21e3cfa26179ca58e1d7c26cdad217201
  xe-pw-148025v8: 148025v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/index.html

[-- Attachment #2: Type: text/html, Size: 1415 bytes --]

✗ Xe.CI.Full: failure for Enable/Disable DC balance along with VRR DSB (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 63657 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev8)
URL   : https://patchwork.freedesktop.org/series/148025/
State : failure

== Summary ==

CI Bug Log - changes from xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201_FULL -> xe-pw-148025v8_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-148025v8_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-148025v8_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-148025v8_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_system_allocator@process-many-malloc-bo-unmap-nomemset:
    - shard-bmg:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@xe_exec_system_allocator@process-many-malloc-bo-unmap-nomemset.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@xe_exec_system_allocator@process-many-malloc-bo-unmap-nomemset.html

  
Known issues
------------

  Here are the changes found in xe-pw-148025v8_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#316])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#3658])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1407]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2327]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#1124]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +5 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [PASS][10] -> [SKIP][11] ([Intel XE#2314] / [Intel XE#2894])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#367])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +26 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#787]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-8/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#787]) +146 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#2887]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2887]) +6 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][20] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2724])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#4417]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#4416]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#306])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#373]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#373])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2252]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2341])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2390])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#307])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][31] ([Intel XE#1178]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-464/igt@kms_content_protection@legacy@pipe-a-dp-4.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     NOTRUN -> [FAIL][32] ([Intel XE#1188]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2321])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2320])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2291])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#2291]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#309])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#323])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#3009])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_dp_aux_dev.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#776])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#1421])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2316]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#2316]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp4:
    - shard-dg2-set2:     [PASS][46] -> [FAIL][47] ([Intel XE#301] / [Intel XE#3321])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6:
    - shard-dg2-set2:     [PASS][48] -> [FAIL][49] ([Intel XE#301])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [PASS][50] -> [INCOMPLETE][51] ([Intel XE#2049] / [Intel XE#2597]) +2 other tests incomplete
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][52] ([Intel XE#2049] / [Intel XE#2597])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a6.html

  * igt@kms_flip@wf_vblank-ts-check@a-hdmi-a1:
    - shard-adlp:         [PASS][53] -> [FAIL][54] ([Intel XE#886]) +1 other test fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-1/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-4/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#455]) +10 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#1401] / [Intel XE#1745])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1401])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2293]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2311]) +9 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#656]) +3 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2312]) +6 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#4141]) +5 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#651]) +11 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2313]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#653]) +10 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [PASS][67] -> [SKIP][68] ([Intel XE#455])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-435/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-bmg:          [PASS][69] -> [SKIP][70] ([Intel XE#1503]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_hdr@static-toggle.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#346])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2501])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#4329])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][74] -> [SKIP][75] ([Intel XE#4596])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#5020])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#870])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#908])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#1489]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#2893] / [Intel XE#4608])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#4608]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#2893])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][83] ([Intel XE#1489]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2387])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_psr2_su@page_flip-xrgb8888.html
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1128])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#1406])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@fbc-psr2-primary-render@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#4609])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-render@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@pr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_psr@pr-primary-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#1127])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#2330])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#1435])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [PASS][93] -> [SKIP][94] ([Intel XE#1435])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [FAIL][95] ([Intel XE#1729])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#362])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#1091] / [Intel XE#2849])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#1091] / [Intel XE#2849])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_eudebug_online@reset-with-attention:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#4837])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@xe_eudebug_online@reset-with-attention.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-dg2-set2:     NOTRUN -> [SKIP][100] ([Intel XE#4837]) +4 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#4837]) +5 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#1392])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#1392])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-dg2-set2:     [PASS][104] -> [SKIP][105] ([Intel XE#1392]) +4 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-rebind.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#2322]) +2 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@many-userptr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#288]) +9 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_exec_fault_mode@many-userptr.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#2360])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_exec_system_allocator@process-many-mmap-huge:
    - shard-dg2-set2:     NOTRUN -> [SKIP][109] ([Intel XE#4915]) +99 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_exec_system_allocator@process-many-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#4943]) +10 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#4943]) +3 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html

  * igt@xe_mmap@pci-membarrier-bad-pagesize:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#5100])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@xe_mmap@pci-membarrier-bad-pagesize.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#512])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_mmap@small-bar.html

  * igt@xe_oa@oa-regs-whitelisted:
    - shard-dg2-set2:     NOTRUN -> [SKIP][114] ([Intel XE#2541] / [Intel XE#3573]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_oa@oa-regs-whitelisted.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#2838] / [Intel XE#979])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][116] ([Intel XE#2284] / [Intel XE#366])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#584])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-6/igt@xe_pm@s3-d3hot-basic-exec.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-adlp:         [PASS][118] -> [DMESG-WARN][119] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-6/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-1/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][120] ([Intel XE#4733]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_pxp@pxp-stale-bo-bind-post-suspend.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#4733])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#944])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-bmg:          NOTRUN -> [SKIP][123] ([Intel XE#4130])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets:
    - shard-dg2-set2:     NOTRUN -> [SKIP][124] ([Intel XE#4351])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-adlp:         [SKIP][125] ([Intel XE#4947]) -> [PASS][126] +3 other tests pass
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [DMESG-FAIL][127] ([Intel XE#4543]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][129] ([Intel XE#3862]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][131] ([Intel XE#3124]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][133] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][135] ([Intel XE#2291]) -> [PASS][136] +1 other test pass
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][137] ([Intel XE#2316]) -> [PASS][138] +1 other test pass
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6:
    - shard-dg2-set2:     [FAIL][139] ([Intel XE#301]) -> [PASS][140] +4 other tests pass
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [INCOMPLETE][141] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][142] +1 other test pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-1/igt@kms_flip@flip-vs-suspend.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][143] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][144] +6 other tests pass
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][145] ([Intel XE#1503]) -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation:
    - shard-adlp:         [SKIP][147] ([Intel XE#4950]) -> [PASS][148] +9 other tests pass
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-adlp:         [SKIP][149] ([Intel XE#4962]) -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_pm_rpm@drm-resources-equal.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_vrr@max-min:
    - shard-lnl:          [FAIL][151] ([Intel XE#4227]) -> [PASS][152] +1 other test pass
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-2/igt@kms_vrr@max-min.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-2/igt@kms_vrr@max-min.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-dg2-set2:     [SKIP][153] ([Intel XE#1392]) -> [PASS][154] +5 other tests pass
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-436/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][155] ([Intel XE#5018]) -> [PASS][156]
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_exec_threads@threads-bal-rebind:
    - shard-adlp:         [SKIP][157] ([Intel XE#4945]) -> [PASS][158] +10 other tests pass
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_threads@threads-bal-rebind.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_exec_threads@threads-bal-rebind.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-adlp:         [FAIL][159] ([Intel XE#3099]) -> [PASS][160] +1 other test pass
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_live_ktest@xe_dma_buf.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_live_ktest@xe_dma_buf.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-adlp:         [SKIP][161] ([Intel XE#4947]) -> [SKIP][162] ([Intel XE#1124]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-adlp:         [SKIP][163] ([Intel XE#4947]) -> [SKIP][164] ([Intel XE#316])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_big_fb@linear-16bpp-rotate-270.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
    - shard-adlp:         [SKIP][165] ([Intel XE#4950]) -> [SKIP][166] ([Intel XE#367])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
    - shard-adlp:         [SKIP][167] ([Intel XE#4947]) -> [SKIP][168] ([Intel XE#455] / [Intel XE#787])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-adlp:         [SKIP][169] ([Intel XE#4950]) -> [SKIP][170] ([Intel XE#306])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_chamelium_color@ctm-0-25.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-adlp:         [SKIP][171] ([Intel XE#4950]) -> [SKIP][172] ([Intel XE#309]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_fbcon_fbt@psr:
    - shard-adlp:         [SKIP][173] ([Intel XE#4947]) -> [SKIP][174] ([Intel XE#776])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_fbcon_fbt@psr.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-adlp:         [SKIP][175] ([Intel XE#4950]) -> [SKIP][176] ([Intel XE#310])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-adlp:         [SKIP][177] ([Intel XE#4947]) -> [SKIP][178] ([Intel XE#651]) +1 other test skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-adlp:         [SKIP][179] ([Intel XE#2351] / [Intel XE#4947]) -> [SKIP][180] ([Intel XE#656])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][181] ([Intel XE#2312]) -> [SKIP][182] ([Intel XE#4141]) +4 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][183] ([Intel XE#4141]) -> [SKIP][184] ([Intel XE#2312]) +4 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-adlp:         [SKIP][185] ([Intel XE#4947]) -> [SKIP][186] ([Intel XE#656]) +3 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][187] ([Intel XE#2312]) -> [SKIP][188] ([Intel XE#2311]) +7 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][189] ([Intel XE#2311]) -> [SKIP][190] ([Intel XE#2312]) +6 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
    - shard-adlp:         [SKIP][191] ([Intel XE#2351] / [Intel XE#4947]) -> [SKIP][192] ([Intel XE#651])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][193] ([Intel XE#2312]) -> [SKIP][194] ([Intel XE#2313]) +8 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-adlp:         [SKIP][195] ([Intel XE#4947]) -> [SKIP][196] ([Intel XE#653]) +1 other test skip
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][197] ([Intel XE#2313]) -> [SKIP][198] ([Intel XE#2312]) +7 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-adlp:         [SKIP][199] ([Intel XE#4947]) -> [SKIP][200] ([Intel XE#1489])
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][201] ([Intel XE#362]) -> [SKIP][202] ([Intel XE#1500])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-435/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-adlp:         [SKIP][203] ([Intel XE#4950]) -> [SKIP][204] ([Intel XE#455]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@kms_vrr@flip-basic.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@kms_vrr@flip-basic.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-adlp:         [SKIP][205] ([Intel XE#4945]) -> [SKIP][206] ([Intel XE#1126])
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_copy_basic@mem-set-linear-0xfffe.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eudebug_online@interrupt-reconnect:
    - shard-adlp:         [SKIP][207] ([Intel XE#4945]) -> [SKIP][208] ([Intel XE#4837])
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_eudebug_online@interrupt-reconnect.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_eudebug_online@interrupt-reconnect.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind:
    - shard-adlp:         [SKIP][209] ([Intel XE#4945]) -> [SKIP][210] ([Intel XE#1392])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm:
    - shard-adlp:         [SKIP][211] ([Intel XE#4945]) -> [SKIP][212] ([Intel XE#288]) +1 other test skip
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         [SKIP][213] ([Intel XE#4945]) -> [DMESG-FAIL][214] ([Intel XE#3868])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_reset@cm-cat-error.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_exec_reset@cm-cat-error.html

  * igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck:
    - shard-adlp:         [SKIP][215] ([Intel XE#4945]) -> [SKIP][216] ([Intel XE#4915]) +34 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_exec_system_allocator@many-large-mmap-remap-dontunmap-eocheck.html

  * igt@xe_oa@invalid-create-userspace-config:
    - shard-adlp:         [SKIP][217] ([Intel XE#4945]) -> [SKIP][218] ([Intel XE#2541] / [Intel XE#3573])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-adlp-4/igt@xe_oa@invalid-create-userspace-config.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-adlp-8/igt@xe_oa@invalid-create-userspace-config.html

  * igt@xe_peer2peer@read:
    - shard-dg2-set2:     [FAIL][219] ([Intel XE#1173]) -> [SKIP][220] ([Intel XE#1061])
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201/shard-dg2-435/igt@xe_peer2peer@read.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/shard-dg2-432/igt@xe_peer2peer@read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3099
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
  [Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
  [Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
  [Intel XE#4962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4962
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201 -> xe-pw-148025v8

  IGT_8423: 8423
  xe-3297-fb5dada21e3cfa26179ca58e1d7c26cdad217201: fb5dada21e3cfa26179ca58e1d7c26cdad217201
  xe-pw-148025v8: 148025v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-148025v8/index.html

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