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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from MN0PR11MB6207.namprd11.prod.outlook.com (2603:10b6:208:3c5::21) by SJ0PR11MB5054.namprd11.prod.outlook.com (2603:10b6:a03:2d3::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9611.16; Mon, 16 Feb 2026 12:27:46 +0000 Received: from MN0PR11MB6207.namprd11.prod.outlook.com ([fe80::52eb:929f:a8b2:139d]) by MN0PR11MB6207.namprd11.prod.outlook.com ([fe80::52eb:929f:a8b2:139d%5]) with mapi id 15.20.9611.013; Mon, 16 Feb 2026 12:27:46 +0000 Message-ID: <0ff0af91-aa7d-4cf5-853f-d457be035c81@intel.com> Date: Mon, 16 Feb 2026 17:57:37 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] drm/xe/xe_ras: Initialize Uncorrectable AER Registers To: Riana Tauro , CC: , , , , , References: <20260122100613.3631582-10-riana.tauro@intel.com> <20260122100613.3631582-15-riana.tauro@intel.com> Content-Language: en-US From: "Mallesh, Koujalagi" In-Reply-To: <20260122100613.3631582-15-riana.tauro@intel.com> Content-Type: text/plain; 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This allows error > detection, containment and recovery in the driver. > > The Uncorrectable Error Severity Register has the 'Uncorrectable > Internal Error Severity' set to fatal by default. Set this to > non-fatal and unmask the error. > > Signed-off-by: Riana Tauro > --- > drivers/gpu/drm/xe/Makefile | 1 + > drivers/gpu/drm/xe/xe_device.c | 3 ++ > drivers/gpu/drm/xe/xe_ras.c | 71 ++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_ras.h | 13 +++++++ > 4 files changed, 88 insertions(+) > create mode 100644 drivers/gpu/drm/xe/xe_ras.c > create mode 100644 drivers/gpu/drm/xe/xe_ras.h > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 5581f2180b5c..85ec53eb0b62 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -110,6 +110,7 @@ xe-y += xe_bb.o \ > xe_pxp_debugfs.o \ > xe_pxp_submit.o \ > xe_query.o \ > + xe_ras.o \ > xe_range_fence.o \ > xe_reg_sr.o \ > xe_reg_whitelist.o \ > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index f418ebf04f0f..be89ffc9eade 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -59,6 +59,7 @@ > #include "xe_psmi.h" > #include "xe_pxp.h" > #include "xe_query.h" > +#include "xe_ras.h" > #include "xe_shrinker.h" > #include "xe_soc_remapper.h" > #include "xe_survivability_mode.h" > @@ -1019,6 +1020,8 @@ int xe_device_probe(struct xe_device *xe) > > xe_vsec_init(xe); > > + xe_ras_init(xe); > + > err = xe_sriov_init_late(xe); > if (err) > goto err_unregister_display; > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c > new file mode 100644 > index 000000000000..ba5ed37aed28 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_ras.c > @@ -0,0 +1,71 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2026 Intel Corporation > + */ > +#include > + > +#include "xe_device_types.h" > +#include "xe_ras.h" > + > +#ifdef CONFIG_PCIEAER > +static void unmask_and_downgrade_internal_error(struct xe_device *xe) > +{ > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); > + struct pci_dev *vsp, *usp; > + u32 aer_uncorr_sev, aer_uncorr_mask; > + u16 aer_cap; > + > + /* Gfx Device Hierarchy: USP-->VSP-->SGunit */ > + vsp = pci_upstream_bridge(pdev); > + if (!vsp) > + return; > + > + usp = pci_upstream_bridge(vsp); > + if (!usp) > + return; > + > + aer_cap = usp->aer_cap; > + > + if (!aer_cap) > + return; > + > + /* > + * All errors are steered to USP which is a PCIe AER Complaint device. > + * Downgrade all the errors to non-fatal to prevent PCIe bus driver > + * from triggering a Secondary Bus Reset (SBR). This allows error > + * detection, containment and recovery in the driver. > + * > + * The Uncorrectable Error Severity Register has the 'Uncorrectable > + * Internal Error Severity' set to fatal by default. Set this to > + * non-fatal and unmask the error. > + */ > + > + /* Initialize Uncorrectable Error Severity Register */ > + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, &aer_uncorr_sev); > + aer_uncorr_sev &= ~PCI_ERR_UNC_INTN; > + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, aer_uncorr_sev); > + > + /* Initialize Uncorrectable Error Mask Register */ > + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, &aer_uncorr_mask); > + aer_uncorr_mask &= ~PCI_ERR_UNC_INTN; > + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, aer_uncorr_mask); Handle pci_read/write_config_dword() failure (return non-zero) scenario for both sev and mask. Impact: Silent failure leads to incorrect assumption about error handling conf. Driver may expect non-fatal errors but still get fatal errors causing unexpected resets. Thanks, -/Mallesh > + > + pci_save_state(usp); > +} > +#endif > + > +/** > + * xe_ras_init - Initialize Xe RAS > + * @xe: xe device instance > + * > + * Initialize Xe RAS > + */ > +void xe_ras_init(struct xe_device *xe) > +{ > + if (!xe->info.has_sysctrl) > + return; > + > +#ifdef CONFIG_PCIEAER > + unmask_and_downgrade_internal_error(xe); > +#endif > +} > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h > new file mode 100644 > index 000000000000..14cb973603e7 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_ras.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#ifndef _XE_RAS_H_ > +#define _XE_RAS_H_ > + > +struct xe_device; > + > +void xe_ras_init(struct xe_device *xe); > + > +#endif