Re: [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 16 Feb 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> The port refclk enable timeout and the soc ready timeout value mentioned
> in the spec is the PHY timings and doesn't include the turnaround time
> from the SoC or OS. So add an overhead timeout value on top of the
> recommended timeouts from the PHY spec.
> The overhead value is based on the stress test results with multiple
> available panels.
>
> Reported-by: Cole Leavitt <cole@unwrap.rs>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714a2bd2d6612cbbd4698 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -78,10 +78,10 @@
>  #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
>  #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
> -#define XELPDP_PORT_RESET_START_TIMEOUT_US		5
> +#define XELPDP_PORT_RESET_START_TIMEOUT_US		10
>  #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS		2
>  #define XELPDP_PORT_RESET_END_TIMEOUT_MS		15
> -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US			10

Side note, *none* of these belong in intel_cx0_phy_regs.h. They should
be moved to intel_cx0_phy.c instead.

The timeouts do not describe the register contents.

BR,
Jani.

>  
>  #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004
>  #define _XELPDP_PORT_BUF_CTL1_LN0_B			0x64104

-- 
Jani Nikula, Intel