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=?utf-8?B?bCtkdFgvQ0FEU1FtQjJDeGMxdHhWL0lRWkU5WUxmZWZ6VTFiQVdlZis3dVNm?= =?utf-8?Q?SQKTWbWqt16U4QLE=3D?= X-Exchange-RoutingPolicyChecked: MB1zO2v0pMmu8duZDF72BA2B68ojIQZUf6Qe2yTtuSXsSWaVQsCfj7p2Qxlwx5nXPXqVAA+hibZU0CozfZqXsGNg964sM7JBeeJYchTsMiDMMnS9U2J6QCo64IsjHRzSOUYAyL/ljnnjniy2PWVme1IlzN5bj5nnhGDxzAr/p1bYhn5NS+8qqo9jXMTtzpQEjuDKjyGGDTz1olLQbb/mVvHOTX4H7Zcyq5Mm7JoE8Dj6Vbcw3RzSKqR1CzSOCHcQ5JoM7t4jFaO2IhQcjFA8NeHqA5PjTyWdVxMShP3GHZdORYS9zdiVjlvuyKjJYLsW3sZj+1QKKaeAdPcu52sbtQ== X-MS-Exchange-CrossTenant-Network-Message-Id: 087578af-7860-43ee-5710-08ded592d92e X-MS-Exchange-CrossTenant-AuthSource: SA3PR11MB7554.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2026 03:59:42.2446 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Xyw4OBN6TgnjwEyloYQemctgd3yRp2wr5UqJtB4NpphVHdHLmMhvITAGGgf+GLRua3vx4TCUcCvtqWJ7DFZMwb6IdbOkyiUvt0glV4tvTfs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR11MB6679 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On 6/13/2026 12:16 AM, Alexander Kaplan wrote: > On Fri, Jun 12, 2026 at 07:32:33PM +0300, Imre Deak wrote: >> So, this would be a generalization for/instead of the HDR logic above >> using a intel_dp_in_hdr_mode() ? 30 : 24 limit (which would also apply a >> lower max-bpc limit for HDR as well). > Hi Imre, > > yes, it follows the same pattern as the HDR logic, with one deliberate > difference. > The extra crtc_state->pipe_bpp check makes an explicit max bpc property > request below 8 win over the new limit, so the uncompressed 6 bpc path > stays reachable. > That keeps the current uAPI behavior under IGT kms_dither and leaves an > escape hatch for sinks with a broken DSC implementation. > The HDR limit currently wins over a lower property request, so a merge > into an intel_dp_in_hdr_mode() ? 30 : 24 block would, as you say, make > HDR honor such a request as well. > If that behavior change for HDR is acceptable I am happy to merge the > two blocks in a v2, otherwise I would keep them separate. > >> There could be other reasons to prefer DSC, like a more finegrained BW >> allocation on MST links. But there are also reasons to prefer non-DSC >> mode like power saving (no need to enable either a DSC encoder in the >> source or a DSC decoder downstream), or reliability issues related to >> DSC. >> >> There's been a lot of talk internally about the above aspects and how to >> handle them in a way suitable in all scenarios. Hence, I'm not sure if >> adding more policies to the driver like the above bpp limit/DSC >> preference is too ad-hoc/early or not at this point. > I understand the hesitation about adding more policy, but for this > series the patch is less a quality preference and more a dependency of > patches 2 and 3. > Those open up RGB configurations on FRL links where previously only the > 4:2:0 fallback existed, and for modes like 4k120 on a 4 lane HBR3 link > the only uncompressed fit is 6 bpc. > Both tested Synaptics PCON device families output corrupted FRL timings > for exactly that configuration and the TV shows a black screen, while > the same mode works with DSC. > So without patch 1 the series would trade the previous 4:2:0 picture > for a black screen on this hardware. > > I also think the 6 bpc case is narrow enough that it does not really > open the general DSC versus non-DSC question. > 6 bpc is a DP and eDP panel concept, HDMI only defines 8, 10, 12 and 16 > bpc output depths. > A PCON that has to forward an 18 bpp stream to an HDMI sink has no > valid HDMI output format for it, which would explain why both device > families fail in the same way. > Windows and macOS drive 4k120 on these devices via DSC, and they have > no other choice, RGB 8 bpc at a 1188 MHz pixel clock needs 28.5 Gbps > against the 25.92 Gbps payload of a 4 lane HBR3 link. > There is also precedent for forcing DSC where the uncompressed 18 bpp > path is broken, commit 55eaef164174 ("drm/i915/dp_mst: Handle the > Synaptics HBlank expansion quirk") does the same for the affected MST > docks. > And only modes which do not fit through the link at 8 bpc are affected > at all, so in the uncompressed case the link already runs at the top of > its capability. > For the power and reliability concerns the max bpc property acts as the > userspace override, setting it to 6 restores today's behavior. > > If the general form is still considered too early, I could narrow the > limit to HDMI sinks behind a PCON, gating it on > intel_dp_has_hdmi_sink(). > There 6 bpc is not a valid output format on the HDMI side, so the > change is a correctness fix rather than a preference, and it would > still unblock patches 2 and 3. I agree to this part. As you have noted, since HDMI does not accept 6 bpc, we should narrow down the check to HDMI sinks behind a DFP. Regards, Ankit > Just let me know which shape you prefer. > > Thanks, > Alex >