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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by CO1PR11MB4833.namprd11.prod.outlook.com (2603:10b6:303:99::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.31; Tue, 5 Nov 2024 19:54:37 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%5]) with mapi id 15.20.8114.028; Tue, 5 Nov 2024 19:54:36 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <87y12gwomu.fsf@intel.com> References: <20241021222744.294371-1-gustavo.sousa@intel.com> <20241021222744.294371-8-gustavo.sousa@intel.com> <87y12gwomu.fsf@intel.com> Subject: Re: [PATCH 07/13] drm/i915/dmc_wl: Check ranges specific to DC states From: Gustavo Sousa CC: Luca Coelho , Rodrigo Vivi To: Jani Nikula , , Date: Tue, 5 Nov 2024 16:54:30 -0300 Message-ID: <173083647049.12577.10180177488392703269@intel.com> User-Agent: alot/0.10 X-ClientProxiedBy: MW4PR04CA0234.namprd04.prod.outlook.com (2603:10b6:303:87::29) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|CO1PR11MB4833:EE_ X-MS-Office365-Filtering-Correlation-Id: 03381ec3-ad07-48ca-e23c-08dcfdd3ad37 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; 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Add the table ranges for them and use >> the correct table depending on the allowed DC states. >> >> Bspec: 71583 >> Signed-off-by: Gustavo Sousa >> --- >> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 112 +++++++++++++++++++- >> 1 file changed, 108 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/d= rm/i915/display/intel_dmc_wl.c >> index d597cc825f64..8bf2f32be859 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c >> @@ -5,6 +5,7 @@ >> =20 >> #include >> =20 >> +#include "i915_reg.h" >> #include "intel_de.h" >> #include "intel_dmc.h" >> #include "intel_dmc_regs.h" >> @@ -52,6 +53,87 @@ static struct intel_dmc_wl_range lnl_wl_range[] =3D { >> {}, >> }; >> =20 >> +static struct intel_dmc_wl_range xe3lpd_dc5_dc6_wl_ranges[] =3D { >> + { .start =3D 0x45500, .end =3D 0x45500 }, /* DC_STATE_SEL */ >> + { .start =3D 0x457a0, .end =3D 0x457b0 }, /* DC*_RESIDENCY_COUN= TER */ >> + { .start =3D 0x45504, .end =3D 0x45504 }, /* DC_STATE_EN */ >> + { .start =3D 0x45400, .end =3D 0x4540c }, /* PWR_WELL_CTL_* */ >> + { .start =3D 0x454f0, .end =3D 0x454f0 }, /* RETENTION_CTRL */ >> + >> + /* DBUF_CTL_* */ >> + { .start =3D 0x44300, .end =3D 0x44300 }, >> + { .start =3D 0x44304, .end =3D 0x44304 }, >> + { .start =3D 0x44f00, .end =3D 0x44f00 }, >> + { .start =3D 0x44f04, .end =3D 0x44f04 }, >> + { .start =3D 0x44fe8, .end =3D 0x44fe8 }, >> + { .start =3D 0x45008, .end =3D 0x45008 }, >> + >> + { .start =3D 0x46070, .end =3D 0x46070 }, /* CDCLK_PLL_ENABLE *= / >> + { .start =3D 0x46000, .end =3D 0x46000 }, /* CDCLK_CTL */ >> + { .start =3D 0x46008, .end =3D 0x46008 }, /* CDCLK_SQUASH_CTL *= / >> + >> + /* TRANS_CMTG_CTL_* */ >> + { .start =3D 0x6fa88, .end =3D 0x6fa88 }, >> + { .start =3D 0x6fb88, .end =3D 0x6fb88 }, >> + >> + { .start =3D 0x46430, .end =3D 0x46430 }, /* CHICKEN_DCPR_1 */ >> + { .start =3D 0x46434, .end =3D 0x46434 }, /* CHICKEN_DCPR_2 */ >> + { .start =3D 0x454a0, .end =3D 0x454a0 }, /* CHICKEN_DCPR_4 */ >> + { .start =3D 0x42084, .end =3D 0x42084 }, /* CHICKEN_MISC_2 */ >> + { .start =3D 0x42088, .end =3D 0x42088 }, /* CHICKEN_MISC_3 */ >> + { .start =3D 0x46160, .end =3D 0x46160 }, /* CMTG_CLK_SEL */ >> + { .start =3D 0x8f000, .end =3D 0x8ffff }, /* Main DMC registers= */ >> + >> + {}, >> +}; >> + >> +static struct intel_dmc_wl_range xe3lpd_dc3co_wl_ranges[] =3D { >> + { .start =3D 0x454a0, .end =3D 0x454a0 }, /* CHICKEN_DCPR_4 */ >> + >> + { .start =3D 0x45504, .end =3D 0x45504 }, /* DC_STATE_EN */ >> + >> + /* DBUF_CTL_* */ >> + { .start =3D 0x44300, .end =3D 0x44300 }, >> + { .start =3D 0x44304, .end =3D 0x44304 }, >> + { .start =3D 0x44f00, .end =3D 0x44f00 }, >> + { .start =3D 0x44f04, .end =3D 0x44f04 }, >> + { .start =3D 0x44fe8, .end =3D 0x44fe8 }, >> + { .start =3D 0x45008, .end =3D 0x45008 }, >> + >> + { .start =3D 0x46070, .end =3D 0x46070 }, /* CDCLK_PLL_ENABLE *= / >> + { .start =3D 0x46000, .end =3D 0x46000 }, /* CDCLK_CTL */ >> + { .start =3D 0x46008, .end =3D 0x46008 }, /* CDCLK_SQUASH_CTL *= / >> + { .start =3D 0x8f000, .end =3D 0x8ffff }, /* Main DMC registers= */ >> + >> + /* Scanline registers */ >> + { .start =3D 0x70000, .end =3D 0x70000 }, >> + { .start =3D 0x70004, .end =3D 0x70004 }, >> + { .start =3D 0x70014, .end =3D 0x70014 }, >> + { .start =3D 0x70018, .end =3D 0x70018 }, >> + { .start =3D 0x71000, .end =3D 0x71000 }, >> + { .start =3D 0x71004, .end =3D 0x71004 }, >> + { .start =3D 0x71014, .end =3D 0x71014 }, >> + { .start =3D 0x71018, .end =3D 0x71018 }, >> + { .start =3D 0x72000, .end =3D 0x72000 }, >> + { .start =3D 0x72004, .end =3D 0x72004 }, >> + { .start =3D 0x72014, .end =3D 0x72014 }, >> + { .start =3D 0x72018, .end =3D 0x72018 }, >> + { .start =3D 0x73000, .end =3D 0x73000 }, >> + { .start =3D 0x73004, .end =3D 0x73004 }, >> + { .start =3D 0x73014, .end =3D 0x73014 }, >> + { .start =3D 0x73018, .end =3D 0x73018 }, >> + { .start =3D 0x7b000, .end =3D 0x7b000 }, >> + { .start =3D 0x7b004, .end =3D 0x7b004 }, >> + { .start =3D 0x7b014, .end =3D 0x7b014 }, >> + { .start =3D 0x7b018, .end =3D 0x7b018 }, >> + { .start =3D 0x7c000, .end =3D 0x7c000 }, >> + { .start =3D 0x7c004, .end =3D 0x7c004 }, >> + { .start =3D 0x7c014, .end =3D 0x7c014 }, >> + { .start =3D 0x7c018, .end =3D 0x7c018 }, >> + >> + {}, >> +}; >> + >> static void __intel_dmc_wl_release(struct intel_display *display) >> { >> struct drm_i915_private *i915 =3D to_i915(display->drm); >> @@ -106,9 +188,31 @@ static bool intel_dmc_wl_addr_in_range(u32 address, >> return false; >> } >> =20 >> -static bool intel_dmc_wl_check_range(u32 address) >> +static bool intel_dmc_wl_check_range(struct intel_display *display, u32= address) >> { >> - return intel_dmc_wl_addr_in_range(address, lnl_wl_range); >> + const struct intel_dmc_wl_range *ranges; >> + >> + ranges =3D lnl_wl_range; >> + >> + if (intel_dmc_wl_addr_in_range(address, ranges)) >> + return true; >> + >> + switch (display->power.domains.dc_state) { > >This file has no business looking at power domain guts. Use or add >interfaces instead of poking at data directly. I started adding a function intel_display_power_get_current_dc_state() here, but then realized that display->power.domains is protected by a mutex and we do not want to use it in an atomic context. So, in v2, to avoid rewriting the whole power domains code to use spinlocks, I decided to go with having a copy of dc_state struct intel_dmc_wl, which is set by intel_dmc_wl_enable(). -- Gustavo Sousa > >> + case DC_STATE_EN_DC3CO: >> + ranges =3D xe3lpd_dc3co_wl_ranges; >> + break; >> + case DC_STATE_EN_UPTO_DC5: >> + case DC_STATE_EN_UPTO_DC6: >> + ranges =3D xe3lpd_dc5_dc6_wl_ranges; >> + break; >> + default: >> + ranges =3D NULL; >> + } >> + >> + if (ranges && intel_dmc_wl_addr_in_range(address, ranges)) >> + return true; >> + >> + return false; >> } >> =20 >> static bool __intel_dmc_wl_supported(struct intel_display *display) >> @@ -195,7 +299,7 @@ void intel_dmc_wl_get(struct intel_display *display,= i915_reg_t reg) >> if (!__intel_dmc_wl_supported(display)) >> return; >> =20 >> - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg.r= eg)) >> + if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(displ= ay, reg.reg)) > >Side note, unrelated to this patch, i915_reg_t is supposed to be opaque, >nobody should look at reg.reg directly, there's i915_mmio_reg_offset() >for it. > >> return; >> =20 >> spin_lock_irqsave(&wl->lock, flags); >> @@ -247,7 +351,7 @@ void intel_dmc_wl_put(struct intel_display *display,= i915_reg_t reg) >> if (!__intel_dmc_wl_supported(display)) >> return; >> =20 >> - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg.r= eg)) >> + if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(displ= ay, reg.reg)) >> return; >> =20 >> spin_lock_irqsave(&wl->lock, flags); > >--=20 >Jani Nikula, Intel