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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from SA1PR11MB8280.namprd11.prod.outlook.com (2603:10b6:806:25d::21) by SN7PR11MB8042.namprd11.prod.outlook.com (2603:10b6:806:2ed::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8207.17; Mon, 2 Dec 2024 12:58:22 +0000 Received: from SA1PR11MB8280.namprd11.prod.outlook.com ([fe80::13a:4240:8d73:3c88]) by SA1PR11MB8280.namprd11.prod.outlook.com ([fe80::13a:4240:8d73:3c88%4]) with mapi id 15.20.8207.014; Mon, 2 Dec 2024 12:58:22 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20241129102503.452272-1-jani.nikula@intel.com> References: <20241129102503.452272-1-jani.nikula@intel.com> Subject: Re: [PATCH] drm/i915/display: replace dig_port->saved_port_bits with flags From: Gustavo Sousa CC: To: Jani Nikula , , Date: Mon, 2 Dec 2024 09:58:16 -0300 Message-ID: <173314429606.2905.1225130957745348760@intel.com> User-Agent: alot/0.10 X-ClientProxiedBy: MW4PR04CA0153.namprd04.prod.outlook.com (2603:10b6:303:85::8) To SA1PR11MB8280.namprd11.prod.outlook.com (2603:10b6:806:25d::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA1PR11MB8280:EE_|SN7PR11MB8042:EE_ X-MS-Office365-Filtering-Correlation-Id: 271928be-1c80-4113-5053-08dd12d10021 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; 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Store them separately as >bools to make their use more logical and less about storing state as >register bits. > >Signed-off-by: Jani Nikula Reviewed-by: Gustavo Sousa >--- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++++++++++--------- > .../drm/i915/display/intel_display_types.h | 4 +- > drivers/gpu/drm/i915/display/intel_tc.c | 2 +- > 4 files changed, 29 insertions(+), 23 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/dr= m/i915/display/intel_cx0_phy.c >index 71dc659228ab..cc734079c3b8 100644 >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >@@ -2987,7 +2987,7 @@ static void intel_cx0pll_enable(struct intel_encoder= *encoder, > struct intel_display *display =3D to_intel_display(encoder); > enum phy phy =3D intel_encoder_to_phy(encoder); > struct intel_digital_port *dig_port =3D enc_to_dig_port(encoder); >- bool lane_reversal =3D dig_port->saved_port_bits & DDI_BUF_PORT_R= EVERSAL; >+ bool lane_reversal =3D dig_port->lane_reversal; > u8 maxpclk_lane =3D lane_reversal ? INTEL_CX0_LANE1 : > INTEL_CX0_LANE0; > intel_wakeref_t wakeref =3D intel_cx0_phy_transaction_begin(encod= er); >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i9= 15/display/intel_ddi.c >index 7d37ddd9ad12..4f9c50996446 100644 >--- a/drivers/gpu/drm/i915/display/intel_ddi.c >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c >@@ -335,10 +335,14 @@ static void intel_ddi_init_dp_buf_reg(struct intel_e= ncoder *encoder, > struct intel_digital_port *dig_port =3D enc_to_dig_port(encoder); >=20 > /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retra= in() later */ >- intel_dp->DP =3D dig_port->saved_port_bits | >- DDI_PORT_WIDTH(crtc_state->lane_count) | >+ intel_dp->DP =3D DDI_PORT_WIDTH(crtc_state->lane_count) | > DDI_BUF_TRANS_SELECT(0); >=20 >+ if (dig_port->lane_reversal) >+ intel_dp->DP |=3D DDI_BUF_PORT_REVERSAL; >+ if (dig_port->ddi_a_4_lanes) >+ intel_dp->DP |=3D DDI_A_4_LANES; >+ > if (DISPLAY_VER(i915) >=3D 14) { > if (intel_dp_is_uhbr(crtc_state)) > intel_dp->DP |=3D DDI_BUF_PORT_DATA_40BIT; >@@ -2402,12 +2406,10 @@ static void intel_ddi_power_up_lanes(struct intel_= encoder *encoder, >=20 > if (intel_encoder_is_combo(encoder)) { > enum phy phy =3D intel_encoder_to_phy(encoder); >- bool lane_reversal =3D >- dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL= ; >=20 > intel_combo_phy_power_up_lanes(i915, phy, false, > crtc_state->lane_count, >- lane_reversal); >+ dig_port->lane_reversal); > } > } >=20 >@@ -2547,7 +2549,7 @@ static void mtl_port_buf_ctl_program(struct intel_en= coder *encoder, > else > val |=3D XELPDP_PORT_BUF_PORT_DATA_10BIT; >=20 >- if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) >+ if (dig_port->lane_reversal) > val |=3D XELPDP_PORT_REVERSAL; >=20 > intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); >@@ -3413,14 +3415,20 @@ static void intel_ddi_enable_hdmi(struct intel_ato= mic_state *state, > * is filled with lane count, already set in the crtc_state. > * The same is required to be filled in PORT_BUF_CTL for C10/20 P= hy. > */ >- buf_ctl =3D dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; >+ buf_ctl =3D DDI_BUF_CTL_ENABLE; >+ >+ if (dig_port->lane_reversal) >+ buf_ctl |=3D DDI_BUF_PORT_REVERSAL; >+ if (dig_port->ddi_a_4_lanes) >+ buf_ctl |=3D DDI_A_4_LANES; >+ > if (DISPLAY_VER(dev_priv) >=3D 14) { > u8 lane_count =3D mtl_get_port_width(crtc_state->lane_co= unt); > u32 port_buf =3D 0; >=20 > port_buf |=3D XELPDP_PORT_WIDTH(lane_count); >=20 >- if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) >+ if (dig_port->lane_reversal) > port_buf |=3D XELPDP_PORT_REVERSAL; >=20 > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, por= t), >@@ -4763,7 +4771,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_d= igital_port *dig_port) > if (dig_port->base.port !=3D PORT_A) > return false; >=20 >- if (dig_port->saved_port_bits & DDI_A_4_LANES) >+ if (dig_port->ddi_a_4_lanes) > return false; >=20 > /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only >@@ -4801,7 +4809,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_p= ort) > if (intel_ddi_a_force_4_lanes(dig_port)) { > drm_dbg_kms(&dev_priv->drm, > "Forcing DDI_A_4_LANES for port A\n"); >- dig_port->saved_port_bits |=3D DDI_A_4_LANES; >+ dig_port->ddi_a_4_lanes =3D true; > max_lanes =3D 4; > } >=20 >@@ -4980,6 +4988,7 @@ void intel_ddi_init(struct intel_display *display, > bool init_hdmi, init_dp; > enum port port; > enum phy phy; >+ u32 ddi_buf_ctl; >=20 > port =3D intel_bios_encoder_port(devdata); > if (port =3D=3D PORT_NONE) >@@ -5229,17 +5238,12 @@ void intel_ddi_init(struct intel_display *display, > else > encoder->hpd_pin =3D intel_hpd_pin_default(dev_priv, port= ); >=20 >- if (DISPLAY_VER(dev_priv) >=3D 11) >- dig_port->saved_port_bits =3D >- intel_de_read(dev_priv, DDI_BUF_CTL(port)) >- & DDI_BUF_PORT_REVERSAL; >- else >- dig_port->saved_port_bits =3D >- intel_de_read(dev_priv, DDI_BUF_CTL(port)) >- & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); >+ ddi_buf_ctl =3D intel_de_read(dev_priv, DDI_BUF_CTL(port)); >+ >+ dig_port->lane_reversal =3D intel_bios_encoder_lane_reversal(devd= ata) || >+ ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; >=20 >- if (intel_bios_encoder_lane_reversal(devdata)) >- dig_port->saved_port_bits |=3D DDI_BUF_PORT_REVERSAL; >+ dig_port->ddi_a_4_lanes =3D DISPLAY_VER(dev_priv) < 11 && ddi_buf= _ctl & DDI_A_4_LANES; >=20 > dig_port->dp.output_reg =3D INVALID_MMIO_REG; > dig_port->max_lanes =3D intel_ddi_max_lanes(dig_port); >diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/= gpu/drm/i915/display/intel_display_types.h >index ec68bbfed442..167aa8ec4948 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_types.h >+++ b/drivers/gpu/drm/i915/display/intel_display_types.h >@@ -1814,11 +1814,13 @@ struct intel_lspcon { >=20 > struct intel_digital_port { > struct intel_encoder base; >- u32 saved_port_bits; > struct intel_dp dp; > struct intel_hdmi hdmi; > struct intel_lspcon lspcon; > enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); >+ >+ bool lane_reversal; >+ bool ddi_a_4_lanes; > bool release_cl2_override; > u8 max_lanes; > /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ >diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i91= 5/display/intel_tc.c >index b16c4d2d4077..0e4d78b146f6 100644 >--- a/drivers/gpu/drm/i915/display/intel_tc.c >+++ b/drivers/gpu/drm/i915/display/intel_tc.c >@@ -390,7 +390,7 @@ void intel_tc_port_set_fia_lane_count(struct intel_dig= ital_port *dig_port, > { > struct drm_i915_private *i915 =3D to_i915(dig_port->base.base.dev= ); > struct intel_tc_port *tc =3D to_tc_port(dig_port); >- bool lane_reversal =3D dig_port->saved_port_bits & DDI_BUF_PORT_R= EVERSAL; >+ bool lane_reversal =3D dig_port->lane_reversal; > u32 val; >=20 > if (DISPLAY_VER(i915) >=3D 14) >--=20 >2.39.5 >