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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by BL1PR11MB5272.namprd11.prod.outlook.com (2603:10b6:208:30a::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8422.12; Wed, 5 Feb 2025 14:19:01 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%5]) with mapi id 15.20.8398.021; Wed, 5 Feb 2025 14:19:01 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20250124191250.56833-1-gustavo.sousa@intel.com> References: <20250124191250.56833-1-gustavo.sousa@intel.com> Subject: Re: [PATCH] drm/i915/dmc_wl: Do not check for DMC payload From: Gustavo Sousa To: , CC: Krzysztof Karas , Lucas De Marchi , Luca Coelho Date: Wed, 5 Feb 2025 11:18:56 -0300 Message-ID: <173876513622.111435.12477179871767663924@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR04CA0309.namprd04.prod.outlook.com (2603:10b6:303:82::14) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|BL1PR11MB5272:EE_ X-MS-Office365-Filtering-Correlation-Id: bc1a0790-4c71-4f30-beb3-08dd45f00975 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; 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As such, we do not need to check if we already >have a DMC payload parsed in __intel_dmc_wl_supported(). > >Furthermore, the presence of such a check causes inconsistencies in the >refcount if the following sequence of events happen: > > 1. A call to one of the register accessors from intel_de.h is done > before the DMC payload is parsed. That causes intel_dmc_wl_get() to > be called. Suppose the register offset qualifies as needing the > wakelock. > > In normal circumstances, the refcount would be incremented, but, > because __intel_dmc_wl_supported() returns false, the refcount is > untouched. > > 2. In a separate worker thread, the DMC firmware is parsed. Parsing of > the DMC payload is finished before the corresponding > intel_dmc_wl_put() from (1) is called. > > 3. When in the context of (1), intel_dmc_wl_put() gets called, now we > have __intel_dmc_wl_supported() returning true and we hit the > warning, because the code doesn't expect a zero refcount. > >Let's remove that check, since it is unnecessary and causes the >inconsistency illustrated above. > >Signed-off-by: Gustavo Sousa Pushed to drm-intel-next. Thank you all for the reviews/feedback! -- Gustavo Sousa >--- > drivers/gpu/drm/i915/display/intel_dmc_wl.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm= /i915/display/intel_dmc_wl.c >index 43884740f8ea..9be6ad11ff5d 100644 >--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c >+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c >@@ -10,7 +10,6 @@ > #include "i915_drv.h" > #include "i915_reg.h" > #include "intel_de.h" >-#include "intel_dmc.h" > #include "intel_dmc_regs.h" > #include "intel_dmc_wl.h" >=20 >@@ -282,7 +281,7 @@ static bool intel_dmc_wl_check_range(struct intel_disp= lay *display, >=20 > static bool __intel_dmc_wl_supported(struct intel_display *display) > { >- return display->params.enable_dmc_wl && intel_dmc_has_payload(dis= play); >+ return display->params.enable_dmc_wl; > } >=20 > static void intel_dmc_wl_sanitize_param(struct intel_display *display) >--=20 >2.48.1 >